PL138-48

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Document overview

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Technical content

Features

• Four Differential 2.5V/3 .3V LVPECL Output Pairs
• Output Frequency: ≤800 MHz
• Two Selectable Differential Input Pairs
• Translates Any Standard Single-Ended or Differential Input Format to LVPECL Output. It Can Accept the Following Standard Input Formats and More: - LVPECL, LVCMOS, LVDS, HCSL, SSTL, LVHSTL, CML
• Output Skew: 25 ps (typ.)
• Part-to-Part Skew: 140 ps (typ.)
• Propagation Delay: 1.5 ns (typ.)
• Additive Jitter: <100 fs (max.)
• Operating Supply Voltage: 2.375V ~ 3.63V
• Operating Temperature Range from –40 °C to +85°C
• Package Availability: 16-Pin QFN and 20-Pin TSSOP General Description The PL138-48 is a high performance low-cost 1:4 outputs differential LVPECL fanout buffer. Microchip’s family of differential LVPECL buffers are designed to operate from a single power supply of 2.5V ±5% or 3.3V ±10%. The differential input pairs are designed to accept most standard input signal levels, using an appropriate resistor bias network, and produce a high quality set of outputs with the lowest possible skew on the outputs, which is guaranteed for part-to-part or lot-to-lot skew. Designed to fit in a small form-factor package, the PL138-48 offers up to 800 MHz of output operation with very low-power consumption and lowest additive jitter of any comparable device. Block Diagram 2.5V to 3.3V , Low-Skew, 1:4 Differential PECL Fanout Buffer

DS20005543B-page 2  2016 Microchip Technology Inc.

1.0 ELECTRICAL CHARACTERISTICS

Absolute Maximum Ratings † † Notice: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operational sections of this s pecification is not intended. Exposure to maximum rating conditions for extended periods may affect device reliability. DC ELECTRICAL CHARACTERISTICS Specifications: VCC = 3.3V; VEE = 0V. Input and output parameters vary 1:1 with VCC when VCC varies ±10%. Parameters Symbol Min. Typ. Max. Units Conditions Output High Voltage, (Note 1)V OH 2.215 2.320 2.420 V At –40°C 2.275 2.350 2.420 At +25°C 2.275 2.350 2.420 At +85°C Output Voltage Low, (Note 1)V OL 1.470 1.610 1.745 V At –40°C 1.490 1.585 1.680 At +25°C 1.490 1.585 1.680 At +85°C Input High Voltage V IH 2.075 — 2.420 V At –40°C 2.135 — 2.420 At +25°C 2.135 — 2.420 At +85°C Input Low Voltage V IL 1.470 — 1.890 V At –40°C 1.490 — 1.825 At +25°C 1.490 — 1.825 At +85°C Output Voltage Reference, (Note 2) VBB 1.86 — 1.98 V At –40°C 1.92 — 2.04 At +25°C 1.92 — 2.04 At +85°C Input High Voltage Common Mode Range, (Note 3, Note 4) VCMR 1.2 — 3.3 V At –40°C 1.2 — 3.3 At +25°C 1.2 — 3.3 At +85°C Input High Current, (Note 5)I IH —— 7 5 µA At –40°C —— 7 5 A t + 2 5 ° C —— 7 5 A t + 8 5 ° C Input Low Current, (Note 5)I IL –75 — — µA At –40°C –75 — — At +25°C –75 — — At +85°C Note 1: Outputs terminated with 50Ω to V CCO–2V. 2: Single-ended input operation is limited to VCC ≥ 3V in LVPECL mode. 3: Common mode voltage is defined as VIH. 4: For single-ended applications, the maximum input voltage for CLK-INx, CLK-INxB is VCC+0.3V. 5: CLK-IN0, CLK-IN1; CLK-IN0B, CLK-IN1B.

 2016 Microchip Technology Inc. DS20005543B-page 3 PL138-48 DC ELECTRICAL CHARACTERISTICS Specifications: VCC = 2.5V; VEE = 0V. Input and output parameters vary 1:1 with VCC when VCC varies ±5%. Parameters Symbol Min. Ty p. Max. Units Conditions Output High Voltage, (Note 1)V OH 1.415 1.520 1.620 V At –40°C 1.475 1.550 1.620 At +25°C 1.475 1.550 1.620 At +85°C Output Voltage Low, (Note 1)V OL 0.670 0.810 0.945 V At –40°C 0.690 0.785 0.880 At +25°C 0.690 0.785 0.880 At +85°C Input High Voltage V IH 1.275 — 1.620 V At –40°C 1.335 — 1.620 At +25°C 1.335 — 1.620 At +85°C Input Low Voltage V IL 0.670 — 1.090 V At –40°C 0.690 — 1.025 At +25°C 0.690 — 1.025 At +85°C Input High Voltage Common Mode Range, (Note 2, Note 3) VCMR 1.2 — 2.5 V At –40°C 1.2 — 2.5 At +25°C 1.2 — 2.5 At +85°C Input High Current, (Note 4)I IH —— 6 0 µA At –40°C — — 60 At +25°C — — 60 At +85°C Input Low Current, (Note 4)I IL –60 — — µA At –40°C –60 — — At +25°C –60 — — At +85°C Note 1: Outputs terminated with 50Ω to VCCO–2V. 2: Common mode voltage is defined as VIH. 3: For single-ended applications, the maximum input voltage for CLK-INx, CLK-INxB is VCC+0.3V. 4: CLK-IN0, CLK-IN1; CLK-IN0B, CLK-IN1B.

DS20005543B-page 4  2016 Microchip Technology Inc. AC ELECTRICAL CHARACTERISTICS f ≤ 800 MHz unless otherwise noted. Parameters Symbol Min. Ty p. Max. Units Conditions Output Frequency f MAX — — 800 MHz At all temperatures Propagation Delay, (Note 1)t PD 600 680 750 ps At –40°C 650 725 790 At +25°C 690 790 890 At +85°C Output Skew, (Note 2, Note 4)t SK(O) — 25 37 ps At all temperatures Part-to-Part Skew, (Note 3, Note 4) tSK(PP) — 85 225 ps At all temperatures Buffer Additive Phase Jitter, RMS tAPJ — — 0.10 ps At all temperatures; refer to Noise Characteristics section Peak-to-Peak Input Voltage (Differential Configuration) VPP 150 800 1200 mV At all temperatures Peak-to-Peak Output Voltage V SWING 470 800 950 mV At –40°C 600 800 930 At +25°C 600 800 930 At +85°C Output Rise/Fall Time t R/tF 200 — 550 ps At all temperatures; 20% to 80% at full output swing. Note 1: Measured from the differential input crossing point to the differential output crossing point. 2: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at the output differential cross points. 3: Defined as skew between outputs on different devices operating at the same supply voltages and with equal load conditions. Using the same type of inputs on each device, the outputs are measured at the dif- ferential cross points. 4: This parameter is defined in accordance with JEDEC Standard 65.

 2016 Microchip Technology Inc. DS20005543B-page 5 PL138-48 TEMPERATURE SPECIFICATIONS (Note 1) Parameters Sym. Min. Typ. Max. Units Conditions Temperature Ranges Ambient Operating Temperature T A –40 — +85 °C Note 2 Junction Temperature T J —— + 1 1 0 ° C — Storage Temperature Range T S –65 — +150 °C — Soldering Temperature — — — +260 °C 10 sec. Note 1: The maximum allowable power dissipation is a function of ambient temperature, the maximum allowable junction temperature, and the thermal resistance from junction to air (i.e., TA, TJ, JA). Exceeding the maximum allowable power dissipation will cause the device operating junction temperature to exceed the maximum +125°C rating. Sustained junction temperatures above +125°C can impact the device reliability. 2: Operating temperature is guaranteed by design for all parts (commercial and industrial), but tested for commercial grade only.

DS20005543B-page 6  2016 Microchip Technology Inc.

2.0 PIN DESCRIPTIONS

FIGURE 2-1: Pin Configuration, 16-Pin QFN. FIGURE 2-2: Pin Configuration, 20-Pin TSSOP. The descriptions of the pins are listed in Table 2-1. TABLE 2-1: PIN FUNCTION TABLE Pin Number QFN-16 Pin Number TSSOP-20 Pin Name Type Description 41 V EE P Power supply pin connection. 16 2 CLK-EN I Synchronizing clock enable. When HIGH, clock outputs follow clock input. When LOW, Q outputs are forced low, QB outputs are forced high. LVTTL/LVCMOS interface levels. 50 kΩ internal pull-up resistor. — 3 CLK-SEL I Clock select input. When HIGH, selects CLK1 input. When LOW, selects CLK0 input. LVTTL/LVCMOS interface levels. 50 kΩ internal pull-down resistor. 2 4 CLK-IN0 I True part of differential clock input signal. 75 k Ω internal pull-down resistor. 3 5 CLK-IN0B I Complementary part of differential clock input signal. 100 kΩ internal pull-up and pull-down resistors.

 2016 Microchip Technology Inc. DS20005543B-page 7 PL138-48 — 6 CLK-IN1 I True part of differential clock input signal. 75 k Ω internal pull-down resistor. — 7 CLK-IN1B I Complementary part of differential clock input signal. 100 kΩ internal pull-up and pull-down resistors. 1, 5 8, 9 DNC — Do Not Connect. 8, 13 10, 13, 18 V CC P Power supply pin connection. 6, 9, 11 ,14 11, 14, 16, 19 QB0 ~ QB3 O LVPECL Complementary output. 7, 10, 12, 15 12, 15, 17, 20 Q0 ~ Q3 O LVPECL True output. TABLE 2-1: PIN FUNCTION TABLE (CONTINUED) Pin Number QFN-16 Pin Number TSSOP-20 Pin Name Type Description

DS20005543B-page 8  2016 Microchip Technology Inc.

3.0 NOISE CHARACTERISTICS

When a buffer is used to pass a signal, the buffer adds a little bit of its own noise. The phase noise on the output of the buffer will be a little bit more than the phase noise of the input signal. To quantify the noise addition in the buffer we compare the Phase Jitter numbers from t he input and the output. The difference is called "Additive Phase Jitter". The formula for the Additive Phase Jitter is as follows: EQUATION 3-1: FIGURE 3-1: PL138-48 Additive Phase Jitter Plot, 622 MHz. TABLE 3-1: PL138-48 NOISE CHARACTERISTICS Parameters Symbol Min. Typ. Max. Units Conditions Additive Phase Jitter t APJ —2 04 0 fs VDD = 3.3V, Frequency = 622.08 MHz Offset = 12 kHz ~ 20 MHz —5 0 1 0 0 V DD = 3.3V, Frequency = 156.25 MHz Offset = 12 kHz ~ 20 MHz —5 0 1 0 0 V DD = 3.3V, Frequency = 50 MHz Offset = 1 kHz ~ 1 MHz —5 0 1 0 0 V DD = 3.3V, Frequency = 25 MHz Offset = 1 kHz ~ 1 MHz AdditivePhaseJitter OutputPhaseJitter 2 InputPhaseJitter 2–=

 2016 Microchip Technology Inc. DS20005543B-page 9 PL138-48

4.0 PARAMETER MEASUR EMENT INFORMATION

FIGURE 4-1: Output Waveform Test Circuit. FIGURE 4-2: Part-to-Part Skew. FIGURE 4-3: Output Rise/Fall Time. FIGURE 4-4: Differential Input Level. FIGURE 4-5: Output Skew. FIGURE 4-6: Propagation Delay.

DS20005543B-page 10  2016 Microchip Technology Inc.

5.0 APPLICATION INFORMATION

5.1 Input Logic Configurations

The following circuits show different configurations for different input logic type signals. For good signal integrity at the PL138 input, the signals need to be properly terminated according to the logic type requirements. The signals need to be presented at the PL138 input according to VCMR, VPP, and other input requirements. FIGURE 5-1: CLK-IN Input Driven by a 3.3V LVPECL Driver. FIGURE 5-2: 3.3V LVPECL Driver, Alternative Termination. FIGURE 5-3: CLK-IN Input Driven by a CML Driver. FIGURE 5-4: CLK-IN Input Driven by an SSTL Driver. FIGURE 5-5: CLK-IN Input Driven by an LVDS Driver. FIGURE 5-6: LVDS Driver, Alternative AC-Coupling. This circuit is for compatibility only. AC-coupling is not really required for LVDS. The VCMR range of the PL138 reaches low enough that LVDS signals can be connected directly to the PL138 input like in the circuit in Figure 5-5. FIGURE 5-7: CLK-IN Input Driven by a CMOS Driver.

 2016 Microchip Technology Inc. DS20005543B-page 11 PL138-48 FIGURE 5-8: CLK-IN Input Driven by a Single-Ended LVPECL. FIGURE 5-9: CLK-IN Input Driven by an HCSL Driver. HCSL presents its signals very close to the ground rail, below the VCMR range, so the HCSL signals cannot be connected to the PL138 input directly. AC-coupling is required for HCSL signals on the PL138 input. FIGURE 5-10: Input Logic Block Diagram.

5.2 Termination for LVPECL Outputs

The required termination for LVPECL is 50 Ω to a VCC-2V DC voltage level. Below are two schematics to implement this termination. FIGURE 5-11: LVPECL Termination Schematic #1.

• V CC = 3.3V - Ideal values: R1 = 127 Ω, R2 = 82.5Ω - Commercial values (E24): R1 = 130 Ω, R2 = 82Ω
• V CC = 2.5V - Ideal values: R1 = 250 Ω, R2 = 62.5Ω - Commercial values (E24): R1 = 240 Ω, R2 = 62Ω TABLE 5-1: INPUT PIN CHARACTERISTICS Input Parameter Min. Typ. Max. Units CLK-IN0, CLK-IN1 Pull-Down Resistor —7 5 — kΩ CLK-IN0B, CLK_IN1B Pull-Up & Pull-Down Resistors —1 0 0 — CLK-EN Pull-Up Resistor —5 0 — CLKSEL Pull-Down Resistor —5 0 — TABLE 5-2: INPUT CLOCK CONTROL SELECTION CLK_SEL Selected Source 0C L K - I N 0 1C L K - I N 1 TABLE 5-3: INPUT CLOCK FUNCTION Inputs Outputs CLK-EN CLKSEL Source Q0:Q3 Q0B:Q3B 0 0 CLK-IN0 Disabled Low Disabled High 0 1 CLK-IN1 Disabled Low Disabled High 1 0 CLK-IN0 Enabled Enabled 1 1 CLK-IN1 Enabled Enabled

DS20005543B-page 12  2016 Microchip Technology Inc. FIGURE 5-12: LVPECL Termination Schematic #2. Schematic #2 is an alternative simplified termination.

• V CC = 3.3V - Ideal value: RT = 48.7 Ω - Commercial value: RT = 50 Ω (E24: 51Ω)
• V CC = 2.5V - Ideal value: RT = 18.7 Ω - Commercial value: RT = 18 Ω

5.3 Power Considerations

Driving LVPECL outputs requires an amount of power that can warm up the chip significantly. The general requirement for the chip is that the junction temperature should not exceed +110°C. The power consumption can be divided into two parts: 1. Core power dissipation 2. Output buffer power dissipation

5.3.1 CORE POWER DISSIPATION

The chip core power is equal to VCC × IEE. With a worst case VCC and IEE, the power dissipation in the core is 3.63V × 45 mA = 163 mW.

5.3.2 OUTPUT BUFFER POWER

The output buffers are not exposed to the full V CC – VEE voltage. On the differential output, one line is at logic 1 with a small voltage across the buffer and a large output current. The othe r line is at logic 0 with a larger voltage across the buffer and a smaller output current. The power dissipation per output buffer is 32 mW. Only buffers that are loaded will have power dissipation. With all 4 buffers loaded the worst case output buffer power dissipation will be 128 mW. Total chip power dissipation, worst case, is 163 mW + 128 mW = 291 mW.

5.3.3 JUNCTION TEMPERATURE

How much the chip is warmed up from the power dissipation depends upon the thermal resistance from the chip to the environment, also known as “junction to ambient”. The thermal resistance depends upon the type of package, how the package is assembled to the PCB and if there is additional air flow for improved cooling. The temperature of the chip (junction) will be higher than the environment (ambient) with an amount equal to θ JA × Power. For an ambient temperature of +85°C, all outputs loaded and no air flow, the junction temperature TJ = 85°C + 73 × 0.291 = 106°C. The temperature of the chip (junction) will be higher than the environment (ambient) with an amount equal to θJA × Power. For an ambient temperature of +85°C, all outputs loaded and no air flow, the junction temperature T TABLE 5-4: 20-PIN TSSOP THERMAL RESISTANCE Air Flow Velocity in Linear Feet/Minute θJA Value for JEDEC Standard Multi-Layer PCB 07 3 ° C / W 200 67°C/W 500 64°C/W TABLE 5-5: 16-PIN QFN THERMAL RESISTANCE Air Flow Velocity in Linear Feet/Minute θJA Value for JEDEC Standard Multi-Layer PCB 06 0 ° C / W 200 53°C/W 500 46°C/W

 2016 Microchip Technology Inc. DS20005543B-page 13 PL138-48

6.0 PACKAGE MARKING INFORMATION

16-Lead QFN 3.0 mm x 3.5 mm Package Outline and Recommended Land Pattern Note: For the most current package drawings, please see the Microchip Packaging S pecification located at http://www.microchip.com/packaging

DS20005543B-page 14  2016 Microchip Technology Inc. 20-Lead TSSOP Package Outline and Recommended Land Pattern Note: For the most current package drawings, please see the Microchip Packaging S pecification located at http://www.microchip.com/packaging

 2016 Microchip Technology Inc. DS20005543B-page 15 PL138-48 APPENDIX A: REVISION HISTORY Revision A (May 2016)

• Converted Micrel data sheet PL138-48 to Micro- chip DS20005543A.
• Minor text changes throughout. Revision B (June 2016)
• Updated output frequency tolerances to 800 MHz.

DS20005543B-page 16  2016 Microchip Technology Inc. NOTES:

 2016 Microchip Technology Inc. DS20005543B-page 17 PL138-48 PRODUCT IDENTIFICATION SYSTEM To order or obtain information, e.g., on pricing or delivery, contact your local Microchip representative or sales office. Examples: a) PL138-48OC-R: 2.5V - 3.3V, Low-Skew, 1:4 Differential PECL Fanout Buf- fer, 20-Pin TSSOP, Commer- cial Temperature Range, Tape & Reel b) PL138-48QI: 2.5V - 3.3V, Low-Skew, 1:4 Differential PECL Fanout Buf- fer, 16-Pin QFN, Industrial Temperature Range, Tube c) PL138-48OI-R: 2.5V - 3.3V, Low-Skew, 1:4 Differential PECL Fanout Buf- fer, 20-Pin TSSOP, Industrial Temperature Range, Tape & Reel d) PL138-48QC: 2.5V - 3.3V, Low-Skew, 1:4 Differential PECL Fanout Buf- fer, 16-Pin QFN, Commercial Temperature Range, Tube PART NO. Device Device: PL138-48: 2.5V - 3.3V, Low-Skew, 1:4 Differential PECL Fanout Buffer Package: O = 20-Pin TSSOP Q = 16-Pin QFN Temperature Range: C= 0 C to +70C (Commercial) I = –40 C to +85C (Industrial) Packing Option: Blank = Tube R = Tape & Reel X Package X Temperature Range Packing Option

DS20005543B-page 18  2016 Microchip Technology Inc. NOTES:

 2016 Microchip Technology Inc. DS20005543B-page 19 Information contained in this publication regarding device applications and the like is provided only for your convenience and may be superseded by updates. It is your responsibility to ensure that your application me ets with your specifications. MICROCHIP MAKES NO REPRESENTATIONS OR WARRANTIES OF ANY KIND WHETHER EXPRESS OR IMPLIED, WRITTEN OR ORAL, STATUTORY OR OTHERWISE, RELATED TO THE INFORMATION, INCLUDING BUT NOT LIMITED TO ITS CONDITION, QUALITY , PERFORMANCE, MERCHANTABILITY OR FITNESS FOR PURPOSE . Microchip disclaims all liability arising from this information and its use. Use of Microchip devices in life support and/or safety applications is entirely at the buyer’s risk, and the buyer agrees to defend, indemnify and hold harmless Microchip from any and all damages, claims, suits, or expenses resulting fr om such use. No licenses are conveyed, implicitly or ot herwise, under any Microchip intellectual property rights unless otherwise stated. Trademarks The Microchip name and logo, the Microchip logo, AnyRate, dsPIC, FlashFlex, flexPWR, Heldo, JukeBlox, KeeLoq, KeeLoq logo, Kleer, LANCheck, LINK MD, MediaLB, MOST, MOST logo, MPLAB, OptoLyzer, PIC, PICSTART, PIC32 logo, RightTouch, SpyNIC, SST, SST Logo, SuperFlash and UNI/O are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. ClockWorks, The Embedded Control Solutions Company, ETHERSYNCH, Hyper Speed Control, HyperLight Load, IntelliMOS, mTouch, Precision Edge, and QUIET-WIRE are registered trademarks of Microchip Technology Incorporated in the U.S.A. Analog-for-the-Digital Age, Any Capacitor, AnyIn, AnyOut, BodyCom, chipKIT, chipKIT logo, CodeGuard, dsPICDEM, dsPICDEM.net, Dynamic Average Matching, DAM, ECAN, EtherGREEN, In-Circuit Serial Programming, ICSP, Inter-Chip Connectivity, JitterBlocker, KleerNet, KleerNet logo, MiWi, motorBench, MPASM, MPF, MPLAB Certified logo, MPLIB, MPLINK, MultiTRAK, NetDetach, Omniscient Code Generation, PICDEM, PICDEM.net, PICkit, PICtail, PureSilicon, RightTouch logo, REAL ICE, Ripple Blocker, Serial Quad I/O, SQI, SuperSwitcher, SuperSwitcher II, Total Endurance, TSHARC, USBCheck, VariSense, ViewSpan, WiperLock, Wireless DNA, and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. Silicon Storage Technology is a registered trademark of Microchip Technology Inc. in other countries. GestIC is a registered trademarks of Microchip Technology Germany II GmbH & Co. KG, a subsidiary of Microchip Technology Inc., in other countries. All other trademarks mentioned herein are property of their respective companies. © 2016, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved. ISBN: 978-1-5224-0540-5 Note the following details of the code protection feature on Microchip devices:

• Microchip products meet the specification cont ained in their particular Microchip Data Sheet.
• Microchip believes that its family of products is one of the mo st secure families of its kind on the market today, when used in the intended manner and under normal conditions.
• There are dishonest and possibly illegal meth ods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
• Microchip is willing to work with the customer who is concerned about the integrity of their code.
• Neither Microchip nor any other semiconduc tor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as “unbreakable.” Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act. Microchip received ISO/TS-16949:2009 certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona; Gresham, Oregon and design centers in California and India. The Company’s quality system processes and procedures are for its PIC ® MCUs and dsPIC® DSCs, KEELOQ® code hopping devices, Serial EEPROMs, microperipherals, nonvolatile memory and analog products. In addition, Microchip’s quality system for the design and manufacture of development systems is ISO 9001:2000 certified. QUALITY MANAGEMENT SYSTEM CERTIFIED BY DNV == ISO/TS 16949 ==

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