PL133-97QE

PL133-97_V01 MICROCHIP | Alldatasheet

Document overview

• Manufacturer or author: Provided By alldatasheet.com(free datasheet download site)
• PDF pages: 19

Technical content

Features

• 1:9 LVCMOS Output Fanout Buffer from DC to

160 MHz

• Low Additive Phase Jitter of 60 fsRMS
• 8 mA Output Drive Strength
• Low Power Consumption for Portable

Applications

• Low Input-Output Delay
• Output-Output Skew <250 ps
• 2.5V to 3.3V, ±10% Operation
• 1.8V +10%/–5% Operation up to 67 MHz
• Operating Temperature Range: 0°C to +70°C, –40°C to +85°C, or –40°C to +105°C
• Available in 16-Lead WQFN Package
• Low Power Applications
• ePPS General Description The PL133-97 is an advanced fanout buffer designed for high performance, low-power, small form factor applications. The PL133-97 accepts a reference clock input from DC to 160 MHz and provides nine outputs of the same frequency with ultra-low additive jitter. The PL133-97 is offered in a small 3 mm x 3 mm WQFN-16L package. The PL133-97 outputs can be disabled to a high impedance (tri-state) by pulling low the OE pin. When the OE pin is high, the outputs are enabled and follow the REF input signal. When the OE pin is left open, a pull-up resistor on the chip will default the OE pin to logic 1 so the outputs are enabled. CLK8 is a free running output that remains enabled when the OE pin is pulled low. Functional Block Diagram REF CLK1 CLK2 CLK3 CLK4 CLK5 CLK6 OE CLK8 CLK7 CLK9 Low-Power DC to 160 MHz 1:9 Fanout Buffer IC

DS20007036A-page 2  2025 Microchip Technology Inc. and its subsidiaries

1.0 ELECTRICAL CHARACTERISTICS

Absolute Maximum Ratings † Static Discharge Voltage Operating Ratings † † Notice: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operational sections of this specification is not intended. Exposure to maximum rating conditions for extended periods may affect device reliability.

ELECTRICAL CHARACTERISTICS

Electrical Characteristics: Parameter Symbol Min. Typ. Max. Units Conditions Input Low Voltage VIL — — 0.3xV DD V Note 1 Input High Voltage VIH 0.7xVDD — — V Note 1 Input Low Current IIL — — 50 µA V IN = 0V Input High Current IIH — — 100 µA V IN = VDD Supply Current IDD — — 32 mA 66.67 MHz with unloaded outputs Output Low Voltage VOL — — 0.5 V IO = 8 mA, VDD = 3.3V — — 0.5 IO = 6 mA, VDD = 2.5V — — 0.5 IO = 4 mA, VDD = 1.8V Output High Voltage V OH VDD - 0.5 — — V IO = –8 mA, VDD = 3.3V VDD - 0.5 — — IO = –6 mA, VDD = 2.5V VDD - 0.5 — — IO = –4 mA, VDD = 1.8V OE Pin Pull-Up Resistance R PU — 120 — kΩ — Load Capacitance CL — — 30 pF Load Capacitance, below 100 MHz, VDD > 2.25V — — 10 Load Capacitance between 100 MHz and 134 MHz, VDD > 2.25V — — 5 Load Capacitance, above 134 MHz, VDD > 2.25V — — 15 Load Capacitance, below 67 MHz, 1.71V < VDD < 2.25V Input Capacitance CIN — — 7 pF — Power-Up Time tPU 0.05 — 50 ms Power-up time for all VDD to reach minimum specified voltage (power ramps must be monotonic) Note 1: REF input has a threshold voltage of VDD/2.

 2025 Microchip Technology Inc. and its subsidiaries DS20007036A-page 3 PL133-97 SWITCHING CHARACTERISTICS Note 2 Electrical Characteristics: Parameter Symbol Min. Typ. Max. Units Conditions Operating Frequency f DC — 160 MHz V DD = 3.3V, 2.5V DC — 67 MHz V DD = 1.8V Duty Cycle = t2 ÷ t1 — 40 50 60 % Measured at V DD/2, Input is 50% Rise Time t3 — — 1.5 ns Measured between 0.8V and 2.0V Fall Time t4 — — 1.5 ns Measured between 0.8V and 2.0V Output to Output Skew Note 1 t5 — — 250 ps All outputs equally loaded Propagation Delay, REF Rising Edge to CLKX Rising Edge Note 1 t6 1 5 9.2 ns Measured at V DD/2 Note 1: Parameter is ensured by design and characterization. 2: All parameters are specified with loaded outputs. NOISE CHARACTERISTICS Electrical Characteristics: Parameter Symbol Min. Typ. Max. Units Conditions Additive Phase Jitter — — 60 — fs VDD = 3.3V, Frequency = 100 MHz Integration range 12 kHz to 20 MHz

DS20007036A-page 4  2025 Microchip Technology Inc. and its subsidiaries TEMPERATURE SPECIFICATIONS (Note 1) Parameters Symbol Min. Typ. Max. Units Conditions Temperature Ranges Ambient Operating Temperature TA –40 — +105 °C Ordering Option E –40 — +85 °C Ordering Option I 0 — +70 °C Ordering Option C Junction Temperature TJ — — +150 °C — Storage Temperature Range TS –65 — +150 °C — Package Thermal Resistance 16-Lead VQFN RθJA — — 82.3 °C/W — Note 1: The maximum allowable power dissipation is a function of ambient temperature, the maximum allowable junction temperature and the thermal resistance from junction to air (i.e., TA, TJ, JA). Exceeding the maximum allowable power dissipation will cause the device operating junction temperature to exceed the maximum +150°C rating. Sustained junction temperatures above +150°C can impact the device reliability.

 2025 Microchip Technology Inc. and its subsidiaries DS20007036A-page 5 PL133-97

2.0 PIN DESCRIPTIONS

FIGURE 2-1: Pin Configuration, 16-Lead WQFN Package. The descriptions of the pins are listed in Table 2-1. TABLE 2-1: PIN FUNCTION TABLE Pin Number P8in Name Type Description 15 REF I Input reference frequency. 1 CLK1 O Buffered clock output. 4 CLK2 O Buffered clock output. 5 CLK3 O Buffered clock output. 8 CLK4 O Buffered clock output. 9 CLK5 O Buffered clock output. 12 CLK6 O Buffered clock output. 13 CLK7 O Buffered clock output. 14 CLK8 O Buffered clock output. 16 CLK9 O Buffered clock output. 2, 11 VDD P VDD connection. 3, 7, 10 GND P GND connection. 6 OE I Output enable control input with 120 kΩ pull-up. ePAD — — Center Pad for Thermal Relief. Connect to GND. CLK4 OE CLK3 GNDCLK8 CLK7 REF CLK1 VDD GND CLK2 CLK6 VDD GND CLK5 12 34 12 11 10 9 16CLK9

DS20007036A-page 6  2025 Microchip Technology Inc. and its subsidiaries

3.0 NOMINAL PERFORMANCE CHARACTERISTICS

U FIGURE 3-1: PL133-97 Additive Phase Jitter: VDD = 3.3V, CLK-100 MHz, Integration Range 12 kHz to 20 MHz. When a buffer is used to pass a signal, the buffer will add a little bit of its own noise. The phase noise on the output of the buffer will be a little bit more than the phase noise in the input signal. The noise added by the buffer to the input signal is quantified by the additive phase jitter defined by the following formula: EQUATION 3-1: Note: The graphs and tables provided following this note are a statistical summary based on a limited number of samples and are provided for informational purposes only. The performance characteristics listed herein are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified operating range (e.g., outside specified power supply range) and therefore outside the warranted range. PLA133-97 AdditivePhaseJitter OutputPhaseJitter 2 InputPhaseJitter 2–=

 2025 Microchip Technology Inc. and its subsidiaries DS20007036A-page 7 PL133-97

4.0 SWITCHING WAVEFORMS

FIGURE 4-1: Duty Cycle Timing. FIGURE 4-2: All Outputs rise/Fall Time. FIGURE 4-3: Output to Output Skew. FIGURE 4-4: Input-Output Propagation Delay. VDD/2 VDD/2 t3 t 4 OUTPUT 0.8V 2.0V 3.3V 0.8V 2.0V OUTPUT OUTPUT VDD/2 VDD/2 INPUT OUTPUT VDD/2 VDD/2

DS20007036A-page 8  2025 Microchip Technology Inc. and its subsidiaries

5.0 TEST CIRCUIT

FIGURE 5-1: Test Circuit. VDD VDD GND GND OUTPUTS CLOAD CLK 0.1 PF 0.1 PF

 2025 Microchip Technology Inc. and its subsidiaries DS20007036A-page 9 PL133-97

6.0 LAYOUT RECOMMENDATIONS

The following guidelines are to assist you with a performance optimized PCB design:

6.1 Signal Integrity and Termination

• Keep traces short - Trace = Inductor. With a capacitive load this equals ringing - Long trace = Transmission Line. Without proper termination this will cause reflections ringing and waveforms and degradations. - Use stripline or microstrip with defined impedance for long traces (>1 inch) - Match traces on one side of the board to avoid reflections bouncing back and forth.

6.2 Decoupling and Power Supply

• Place decoupling capacitors as close as pos- sible to the VDD pin(s) to limit noise from the power supply - Addition of a ferrite bead in series with VDD can help prevent noise from other board sources - Value of decoupling capacitor is frequency dependent. Typical values to use are 0.1 µF for designs using frequencies <50 MHz and 0.01 µF for designs using frequencies >50 MHz FIGURE 6-1: Typical CMOS Termination. Place Series Resistor as close as possible to CMOS output CMOS Output Buffer ( Typical buffer impedance 20 ohm) To CMOS Input Connect a 33 ohm series resistor at each of the output clocks to enhance the stability of the output signal 50 ohm line

DS20007036A-page 10  2025 Microchip Technology Inc. and its subsidiaries

7.0 PACKAGING INFORMATION

7.1 Package Marking Information

16-Lead WQFN* NNN 97E P133 7ES Legend: XX...X Product code, customer-specific information, or frequency in MHz without printed decimal point Y Year code (last digit of calendar year) YY Year code (last 2 digits of calendar year) WW Week code (week of January 1 is week ‘01’) NNN Alphanumeric traceability code Pb-free JEDEC ® designator for Matte Tin (Sn) * This package is Pb-free. The Pb-free JEDEC designator ( ) can be found on the outer packaging for this package.

• , ▲, ▼ Pin one index is identified by a dot, delta up, or delta down (triangle mark). Note: In the event the full Microchip part number cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for customer-specific information. Package may or may not include the corporate logo. Underbar (_) and/or Overbar (‾) symbol may not be to scale.

 2025 Microchip Technology Inc. and its subsidiaries DS20007036A-page 11 PL133-97

0.10 C A B

0.05 C C SIDE VIEW BOTTOM VIEW 0.10 C 0.08 C Sheet 1 of 2 16X Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging Microchip Technology Drawing C04-01264 Rev A SEATING PLANE BA 0.10 C 0.10 C 2X TOP VIEW NOTE1 (DATUM B) (DATUM A) E E (K) 16X b L e e (A3) A 16-Lead Very, Very Thin Quad Flatpack No-Lead (Q) 3x3x0.8 mm Body [WQFN] Package Code: NEA

DS20007036A-page 12  2025 Microchip Technology Inc. and its subsidiaries Number of Terminals Overall Height Terminal Width Overall Width Terminal Length Exposed Pad Width Terminal Thickness Pitch Standoff Units Dimension Limits A b e L E N

0.50 BSC

0.20 REF

1.65 0.35 0.20 0.70 0.00 0.25 0.40 1.70 0.75

3.00 BSC

1.75 4.45 0.30 0.80 0.05 MAX K 0.25 REFTerminal-to-Exposed-Pad For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging Note: Overall Length Exposed Pad Length D D2 1.65 1.70 1.75 REF: Reference Dimension, usually without tolerance, for information purposes only. BSC: Basic Dimension. Theoretically exact value shown without tolerances. Notes: Pin 1 visual index feature may vary, but must be located within the hatched area. Package is saw singulated Dimensioning and tolerancing per ASME Y14.5M Sheet 2 of 2Microchip Technology Drawing C04-01264 Rev A 16-Lead Very, Very Thin Quad Flatpack No-Lead (Q) 3x3x0.8 mm Body [WQFN] Package Code: NEA

 2025 Microchip Technology Inc. and its subsidiaries DS20007036A-page 13 PL133-97 RECOMMENDED LAND PATTERN Dimension Limits Units Center Pad Width Contact Pad Spacing Center Pad Length Contact Pitch 1.75 1.75 MILLIMETERS E MAX 3.00 Contact Pad Length (X16) Contact Pad Width (X16) 0.80 0.30 NOM C1Contact Pad Spacing 3.00 Contact Pad to Contact Pad (X12) G2 0.20 Thermal Via Diameter V Thermal Via Pitch EV 0.30 1.00 BSC: Basic Dimension. Theoretically exact value shown without tolerances. Notes: Dimensioning and tolerancing per ASME Y14.5M For best soldering results, pleease refer to current industry standard IPC-7093. For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging Note: Contact Pad to Center Pad (X16) G1 0.20 Microchip Technology Drawing C04-03264 Rev A SILK SCREEN X11X E 16-Lead Very, Very Thin Quad Flatpack No-Lead (Q) 3x3x0.8 mm Body [WQFN] Package Code: NEA EV EV ØV

DS20007036A-page 14  2025 Microchip Technology Inc. and its subsidiaries NOTES:

 2025 Microchip Technology Inc. and its subsidiaries DS20007036A-page 15 PL133-97 APPENDIX A: REVISION HISTORY Revision A (December 2025)

• Converted Micrel legacy data sheet PL133-97 to Microchip data sheet DS20007036A.
• Minor text edits throughout.

DS20007036A-page 16  2025 Microchip Technology Inc. and its subsidiaries NOTES:

 2025 Microchip Technology Inc. and its subsidiaries DS20007036A-page 17 PL133-97 PRODUCT IDENTIFICATION SYSTEM To order or obtain information, e.g., on pricing or delivery, contact your local Microchip representative or sales office. Examples: Device: PL133-97: Low-Power DC to 160 MHz 1:9 Fanout Buffer IC Package: Q = 16-Lead 3 mm x 3 mmWQFN Package Temperature Range: E = –40°C to +105°C I = –40°C to +85°C C = 0°C to +70°C Media Type: (blank) = 20/Bag R = 3,000/Reel Note 1: Tape and Reel identifier only appears in the catalog part number description. This identifier is used for ordering purposes and is not printed on the device package. Check with your Microchip Sales Office for package availability with the Tape and Reel option. a) PL133-97QE Low-Power DC to 160 MHz 1:9 Fanout Buffer IC, WQFN Pack- age, –40°C to +105°C, 20/Bag b) PL133-97QE-R Low-Power DC to 160 MHz 1:9 Fanout Buffer IC, WQFN Pack- age, –40°C to +105°C, 3,000/Reel c) PL133-97QI Low-Power DC to 160 MHz 1:9 Fanout Buffer IC, WQFN Pack- age, –40°C to +85°C, 20/Bag d) PL133-97QI-R Low-Power DC to 160 MHz 1:9 Fanout Buffer IC, WQFN Pack- age, –40°C to +85°C, 3,000/Reel e) PL133-97QC Low-Power DC to 160 MHz 1:9 Fanout Buffer IC, WQFN Pack- age, 0°C to +70°C, 20/Bag f) PL133-97QC-R Low-Power DC to 160 MHz 1:9 Fanout Buffer IC, WQFN Pack- age, 0°C to +170°C, 3,000/Reel PART NO. X X -X Device Package Temperature Range Media Type

DS20007036A-page 18  2025 Microchip Technology Inc. and its subsidiaries NOTES:

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