PL133-97QC

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Document overview

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• PDF pages: 18

Technical content

Features

• 1:9 LVCMOS Output Fanout Buffer from DC to150 MHz
• Low Additive Phase Jitter of 60 fs RMS
• 8 mA Output Drive Strength
• Low Power Consumption for Portable

Applications

• Low Input-Output Delay
• Output-Output Skew <250 ps
• 2.5V to 3.3V, ±10% Operation
• 1.8V ±5% Operation up to 67 MHz
• Operating Temperature Range: - Commercial: 0°C to +70°C - Industrial: –40°C to +85°C
• Available in 16-Pin QFN Package General Description The PL133-97 is an advanced fanout buffer designed for high performance, low-power, small form factor applications. The PL133-97 accepts a reference clock input from DC to 150 MHz and provides nine outputs of the same frequency. The PL133-97 is offered in a small 3 mm x 3 mm QFN-16L package and it offers the best phase noise, additive jitter performance, and lowest power consumption of any comparable IC. The PL133-97 outputs can be disabled to a high impedance (tri-state) by pulling low the OE pin. When the OE pin is high, the outputs are enabled and follow the REF input signal. When the OE pin is left open, a pull-up resistor on the chip will default the OE pin to logic 1 so the outputs are enabled. CLK8 is a free running output that remains enabled when the OE pin is pulled low. Functional Block Diagram REF CLK1 CLK2 CLK3 CLK4 CLK5 CLK6 OE CLK8 CLK7 CLK9 Low-Power DC to 150 MHz 1:9 Fanout Buffer IC

DS20006672A-page 2  2022 Microchip Technology Inc. and its subsidiaries

1.0 ELECTRICAL CHARACTERISTICS

Absolute Maximum Ratings † Static Discharge Voltage Operating Ratings † † Notice: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operational sections of this specification is not intended. Exposure to maximum rating conditions for extended periods may affect device reliability.

ELECTRICAL CHARACTERISTICS

Electrical Characteristics: Parameter Symbol Min. Typ. Max. Units Conditions Input Low Voltage VIL — — 0.3xV DD V Note 1 Input High Voltage VIH 0.7xVDD — — V Note 1 Input Low Current IIL — — 50 µA V IN = 0V Input High Current IIH — — 100 µA V IN = VDD Supply Current IDD — — 32 mA 66.67 MHz with unloaded outputs Output Low Voltage VOL — — 0.5 V IO = 8 mA, VDD = 3.3V — — 0.5 IO = 6 mA, VDD = 2.5V — — 0.5 IO = 4 mA, VDD = 1.8V Output High Voltage V OH VDD - 0.5 — — V IO = –8 mA, VDD = 3.3V VDD - 0.5 — — IO = –6 mA, VDD = 2.5V VDD - 0.5 — — IO = –4 mA, VDD = 1.8V OE Pin Pull-Up Resistance R PU — 120 — kΩ — Load Capacitance CL — — 30 pF Load Capacitance, below 100 MHz, VDD > 2.25V — — 10 Load Capacitance between 100 MHz and 134 MHz, VDD > 2.25V — — 5 Load Capacitance, above 134 MHz, VDD > 2.25V — — 15 Load Capacitance, below 67 MHz, 1.71V < VDD < 2.25V Input Capacitance CIN — — 7 pF — Power-Up Time tPU 0.05 — 50 ms Power-up time for all VDD to reach minimum specified voltage (power ramps must be monotonic) Note 1: REF input has a threshold voltage of VDD/2.

 2022 Microchip Technology Inc. and its subsidiaries DS20006672A-page 3 PL133-97 SWITCHING CHARACTERISTICS Note 2 Electrical Characteristics: Parameter Symbol Min. Typ. Max. Units Conditions Operating Frequency f DC — 160 MHz V DD = 3.3V, 2.5V DC — 67 MHz V DD = 1.8V Duty Cycle = t2 ÷ t1 — 40 50 60 % Measured at V DD/2, Input = 50% Rise Time t3 — — 1.5 ns Measured between 0.8V and 2.0V Fall Time t4 — — 1.5 ns Measured between 0.8V and 2.0V Output to Output Skew Note 1 t5 — — 250 ps All outputs equally loaded Propagation Delay, REF Rising Edge to CLKX Rising Edge Note 1 t6 1 5 9.2 ns Measured at V DD/2 Note 1: Parameter is guaranteed by design and characterization. 2: All parameters are specified with loaded outputs. NOISE CHARACTERISTICS Electrical Characteristics: Parameter Symbol Min. Typ. Max. Units Conditions Additive Phase Jitter — — 60 — fs VDD = 3.3V, Frequency = 100 MHz Integration range 12 kHz - 20 MHz

DS20006672A-page 4  2022 Microchip Technology Inc. and its subsidiaries TEMPERATURE SPECIFICATIONS (Note 1) Parameters Symbol Min. Typ. Max. Units Conditions Temperature Ranges Ambient Operating Temperature (TA) T A 0 — +70 °C Commercial –40 — +85 Industrial Junction Temperature TJ — — +150 °C — Storage Temperature Range TS –65 — +150 °C — Package Thermal Resistance 16-Lead QFN RθJA — 82.5 — °C/W — Note 1: The maximum allowable power dissipation is a function of ambient temperature, the maximum allowable junction temperature and the thermal resistance from junction to air (i.e., TA, TJ, JA). Exceeding the maximum allowable power dissipation will cause the device operating junction temperature to exceed the maximum +150°C rating. Sustained junction temperatures above +150°C can impact the device reliability.

 2022 Microchip Technology Inc. and its subsidiaries DS20006672A-page 5 PL133-97

2.0 PIN DESCRIPTIONS

FIGURE 2-1: Pin Configuration, 16-Lead QFN Package. The descriptions of the pins are listed in Table 2-1. TABLE 2-1: PIN FUNCTION TABLE Pin Number P8in Name Type Description

15 REF I Input reference frequency

1 CLK1 O Buffered clock output

4 CLK2 O Buffered clock output

5 CLK3 O Buffered clock output

8 CLK4 O Buffered clock output

9 CLK5 O Buffered clock output

12 CLK6 O Buffered clock output

13 CLK7 O Buffered clock output

14 CLK8 O Buffered clock output, free running, does not disable with OE

16 CLK9 O Buffered clock output

2, 11 VDD P VDD connection 3, 7, 10 GND P GND connection

6 OE I Output enable control input with 130 kΩ pull-up

ePAD — — Center Pad for thermal relief. Connect to GND CLK4 OE CLK3 GNDCLK8 CLK7 REF CLK1 VDD GND CLK2 CLK6 VDD GND CLK5 12 34 12 11 10 9 16CLK9

DS20006672A-page 6  2022 Microchip Technology Inc. and its subsidiaries

3.0 NOMINAL PERFORMANCE CHARACTERISTICS

U FIGURE 3-1: PL133-97 Additive Phase Jitter: VDD = 3.3V, CLK-100 MHz, Integration Range 12 kHz - 20 MHz. When a buffer is used to pass a signal then the buffer will add a little bit of its own noise. The phase noise on the output of the buffer will be a little bit more than the phase noise in the input signal. The noise added by the buffer to the input signal is quantified by the additive phase jitter defined by the following formula: EQUATION 3-1: Note: The graphs and tables provided following this note are a statistical summary based on a limited number of samples and are provided for informational purposes only. The performance characteristics listed herein are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified operating range (e.g., outside specified power supply range) and therefore outside the warranted range. PL133-97 AdditivePhaseJitter OutputPhaseJitter 2 InputPhaseJitter 2–=

 2022 Microchip Technology Inc. and its subsidiaries DS20006672A-page 7 PL133-97

4.0 SWITCHING WAVEFORMS

FIGURE 4-1: Duty Cycle Timing. FIGURE 4-2: All Outputs Rise/Fall Time. FIGURE 4-3: Output to Output Skew. FIGURE 4-4: Input-Output Propagation Delay. VDD/2 VDD/2 t3 t 4 OUTPUT 0.8V 2.0V 3.3V 0.8V 2.0V OUTPUT OUTPUT VDD/2 VDD/2 INPUT OUTPUT VDD/2 VDD/2

DS20006672A-page 8  2022 Microchip Technology Inc. and its subsidiaries

5.0 TEST CIRCUIT

FIGURE 5-1: Test Circuit. VDD VDD GND GND OUTPUTS CLOAD CLK 0.1 PF 0.1 PF

 2022 Microchip Technology Inc. and its subsidiaries DS20006672A-page 9 PL133-97

6.0 LAYOUT RECOMMENDATIONS

The following guidelines are to assist you with a performance optimized PCB design:

6.1 Signal Integrity and Termination

• Keep traces short - Trace = Inductor. With a capacitive load this equals ringing - Long trace = Transmission Line. Without proper termination this will cause reflections ringing and waveforms degradations. - Use stripline or microstrip with defined impedance for long traces (> 1 inch) - Match traces on one side of the board to avoid reflections bouncing back and forth.

6.2 Decoupling and Power Supply

• Place decoupling capacitors as close as pos- sible to the VDD pin(s) to limit noise from the power supply - Addition of a ferrite bead in series with VDD can help prevent noise from other board sources - Value of decoupling capacitor is frequency dependant. Typical values to use are 0.1 µF for designs using frequencies <50 MHz and 0.01 µF for designs using frequencies >50 MHz FIGURE 6-1: Typical CMOS Termination. Place Series Resistor as close as possible to CMOS output CMOS Output Buffer ( Typical buffer impedance 20 ohm) To CMOS Input Connect a 33 ohm series resistor at each of the output clocks to enhance the stability of the output signal 50 ohm line

DS20006672A-page 10  2022 Microchip Technology Inc. and its subsidiaries

7.0 PACKAGING INFORMATION

7.1 Package Marking Information

16-Lead QFN* NNN P133 820 Legend: XX...X Product code, customer-specific information, or frequency in MHz without printed decimal point Y Year code (last digit of calendar year) YY Year code (last 2 digits of calendar year) WW Week code (week of January 1 is week ‘01’) NNN Alphanumeric traceability code Pb-free JEDEC ® designator for Matte Tin (Sn) * This package is Pb-free. The Pb-free JEDEC designator ( ) can be found on the outer packaging for this package.

• , ▲, ▼ Pin one index is identified by a dot, delta up, or delta down (triangle mark). Note: In the event the full Microchip part number cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for customer-specific information. Package may or may not include the corporate logo. Underbar (_) and/or Overbar (‾) symbol may not be to scale.

 2022 Microchip Technology Inc. and its subsidiaries DS20006672A-page 11 PL133-97 16-Lead QFN Package Outline and Recommended Land Pattern Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging.

DS20006672A-page 12  2022 Microchip Technology Inc. and its subsidiaries NOTES:

 2022 Microchip Technology Inc. and its subsidiaries DS20006672A-page 13 PL133-97 APPENDIX A: REVISION HISTORY Revision A (April 2022)

• Converted Micrel document PL133-97 to Micro- chip data sheet DS20006672A.
• Minor text changes throughout.

DS20006672A-page 14  2022 Microchip Technology Inc. and its subsidiaries NOTES:

 2022 Microchip Technology Inc. and its subsidiaries DS20006672A-page 15 PLA133-97 PRODUCT IDENTIFICATION SYSTEM To order or obtain information, e.g., on pricing or delivery, contact your local Microchip representative or sales office. Examples: Device: PL133-97: Low-Power DC to 150 MHz 1:9 Fanout Buffer IC Package: Q = 16-Lead QFN Package (RoHS Compliant) Temperature Range: C = 0°C to +70°C (Commercial) I = –40°C to +85°C (Industrial) Media Type: (blank) = 20/Bag R = 3,000/Reel Note 1: Tape and Reel identifier only appears in the catalog part number description. This identifier is used for ordering purposes and is not printed on the device package. Check with your Microchip Sales Office for package availability with the Tape and Reel option. a) PL133-97QC Low-Power DC to 150 MHz 1:9 Fanout Buffer IC, QFN Package, 0°C to +70°C, 20/Bag b) PL133-97QC-R Low-Power DC to 150 MHz 1:9 Fanout Buffer IC, QFN Package, 0°C to +70°C, 3,000/Reel c) PL133-97QI Low-Power DC to 150 MHz 1:9 Fanout Buffer IC, QFN Package, –40°C to +85°C, 20/Bag b) PL133-97QI-R Low-Power DC to 150 MHz 1:9 Fanout Buffer IC, QFN Package, –40°C to +85°C, 3,000/Reel PART NO. X XX X Device Package Temperature Range Media Type

DS20006672A-page 16  2022 Microchip Technology Inc. and its subsidiaries NOTES:

 2022 Microchip Technology Inc. and its subsidiaries DS20006672A-page 17 This publication and the information herein may be used only with Microchip products, including to design, test, and integrate Microchip products with your application. Use of this informa- tion in any other manner violates these terms. Information regarding device applications is provided only for your conve- nience and may be superseded by updates. It is your responsi- bility to ensure that your application meets with your specifications. Contact your local Microchip sales office for additional support or, obtain additional support at https:// www.microchip.com/en-us/support/design-help/client-support- services. THIS INFORMATION IS PROVIDED BY MICROCHIP "AS IS". MICROCHIP MAKES NO REPRESENTATIONS OR WAR- RANTIES OF ANY KIND WHETHER EXPRESS OR IMPLIED, WRITTEN OR ORAL, STATUTORY OR OTHERWISE, RELATED TO THE INFORMATION INCLUDING BUT NOT LIMITED TO ANY IMPLIED WARRANTIES OF NON- INFRINGEMENT, MERCHANTABILITY , AND FITNESS FOR A PARTICULAR PURPOSE, OR WARRANTIES RELATED TO ITS CONDITION, QUALITY , OR PERFORMANCE. IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDI- RECT, SPECIAL, PUNITIVE, INCIDENTAL, OR CONSE - QUENTIAL LOSS, DAMAGE, COST, OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE INFORMATION OR ITS USE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY RELATED TO THE INFORMATION OR ITS USE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY , THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THE INFORMATION. Use of Microchip devices in life support and/or safety applica- tions is entirely at the buyer's risk, and the buyer agrees to defend, indemnify and hold harmless Microchip from any and all damages, claims, suits, or expenses resulting from such use. No licenses are conveyed, implicitly or otherwise, under any Microchip intellectual property rights unless otherwise stated. Trademarks The Microchip name and logo, the Microchip logo, Adaptec, AnyRate, AVR, AVR logo, AVR Freaks, BesTime, BitCloud, CryptoMemory, CryptoRF, dsPIC, flexPWR, HELDO, IGLOO, JukeBlox, KeeLoq, Kleer, LANCheck, LinkMD, maXStylus, maXTouch, MediaLB, megaAVR, Microsemi, Microsemi logo, MOST, MOST logo, MPLAB, OptoLyzer, PIC, picoPower, PICSTART, PIC32 logo, PolarFire, Prochip Designer, QTouch, SAM-BA, SenGenuity, SpyNIC, SST, SST Logo, SuperFlash, Symmetricom, SyncServer, Tachyon, TimeSource, tinyAVR, UNI/O, Vectron, and XMEGA are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. AgileSwitch, APT, ClockWorks, The Embedded Control Solutions Company, EtherSynch, Flashtec, Hyper Speed Control, HyperLight Load, IntelliMOS, Libero, motorBench, mTouch, Powermite 3, Precision Edge, ProASIC, ProASIC Plus, ProASIC Plus logo, Quiet- Wire, SmartFusion, SyncWorld, Temux, TimeCesium, TimeHub, TimePictra, TimeProvider, TrueTime, WinPath, and ZL are registered trademarks of Microchip Technology Incorporated in the U.S.A. Adjacent Key Suppression, AKS, Analog-for-the-Digital Age, Any Capacitor, AnyIn, AnyOut, Augmented Switching, BlueSky, BodyCom, CodeGuard, CryptoAuthentication, CryptoAutomotive, CryptoCompanion, CryptoController, dsPICDEM, dsPICDEM.net, Dynamic Average Matching, DAM, ECAN, Espresso T1S, EtherGREEN, GridTime, IdealBridge, In-Circuit Serial Programming, ICSP, INICnet, Intelligent Paralleling, Inter-Chip Connectivity, JitterBlocker, Knob-on-Display, maxCrypto, maxView, memBrain, Mindi, MiWi, MPASM, MPF, MPLAB Certified logo, MPLIB, MPLINK, MultiTRAK, NetDetach, NVM Express, NVMe, Omniscient Code Generation, PICDEM, PICDEM.net, PICkit, PICtail, PowerSmart, PureSilicon, QMatrix, REAL ICE, Ripple Blocker, RTAX, RTG4, SAM-ICE, Serial Quad I/O, simpleMAP, SimpliPHY, SmartBuffer, SmartHLS, SMART-I.S., storClad, SQI, SuperSwitcher, SuperSwitcher II, Switchtec, SynchroPHY, Total Endurance, TSHARC, USBCheck, VariSense, VectorBlox, VeriPHY, ViewSpan, WiperLock, XpressConnect, and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. The Adaptec logo, Frequency on Demand, Silicon Storage Technology, Symmcom, and Trusted Time are registered trademarks of Microchip Technology Inc. in other countries. GestIC is a registered trademark of Microchip Technology Germany II GmbH & Co. KG, a subsidiary of Microchip Technology Inc., in other countries. All other trademarks mentioned herein are property of their respective companies. © 2022, Microchip Technology Incorporated and its subsidiaries. All Rights Reserved. ISBN: 978-1-6683-0275-0 Note the following details of the code protection feature on Microchip products:

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