PL133-67

PL133-67_V01 MICROCHIP | Alldatasheet

Document overview

• Manufacturer or author: Provided By alldatasheet.com(free datasheet download site)
• PDF pages: 19

Technical content

Features

• 1:6 LVCMOS Output Fanout Buffer from DC to

160 MHz

• Low Additive Phase Jitter of 60 fsRMS
• 8 mA Output Drive Strength
• Low Power Consumption for Portable

Applications

• Low Input-Output Delay
• Output-Output Skew <250 ps
• 2.5V to 3.3V, +10% Operation
• 1.8V +10%/–5% Operation up to 67 MHz
• Operating Temperature Range: 0°C to +70°C, –40°C to +85°C, or –40°C to +105°C
• Available in 16-Pin TSSOP Package
• Low Power Applications General Description The PL133-67 is an advanced fanout buffer designed for high performance, low-power, small form factor applications. The PL133-67 accepts a reference clock input from DC to 160 MHz and provides six outputs of the same frequency with ultra-low additive jitter. The PL133-67 is available in a TSSOP-16L package. The PL133-67 outputs can be disabled to a high impedance (tri-state) by pulling low the OE pin. When the OE pin is high, the outputs are enabled and follow the REF input signal. When the OE pin is left open, a pull-up resistor on the chip will default the OE pin to logic 1 so the outputs are enabled. Functional Block Diagram Low-Power DC to 160 MHz 1:6 Fanout Buffer IC

DS20007035A-page 2  2026 Microchip Technology Inc. and its subsidiaries

1.0 ELECTRICAL CHARACTERISTICS

Absolute Maximum Ratings † Static Discharge Voltage Operating Ratings † † Notice: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operational sections of this specification is not intended. Exposure to maximum rating conditions for extended periods may affect device reliability.

ELECTRICAL CHARACTERISTICS

Electrical Characteristics: Parameter Symbol Min. Typ. Max. Units Conditions Input Low Voltage VIL — — 0.3xV DD V Note 1 Input High Voltage VIH 0.7xVDD — — V Note 1 Input Low Current IIL — — 50 µA V IN = 0V Input High Current IIH — — 100 µA V IN = VDD Supply Current IDD — — 32 mA 66.67 MHz with unloaded outputs Output Low Voltage VOL — — 0.5 V IO = 8 mA, VDD = 3.3V — — 0.5 IO = 6 mA, VDD = 2.5V — — 0.5 IO = 4 mA, VDD = 1.8V Output High Voltage V OH VDD - 0.5 — — V IO = –8 mA, VDD = 3.3V VDD - 0.5 — — IO = –6 mA, VDD = 2.5V VDD - 0.5 — — IO = –4 mA, VDD = 1.8V OE Pin Pull-Up Resistance R PU — 120 — k9 — Load Capacitance CL — — 30 pF Load Capacitance, below 100 MHz, VDD > 2.25V — — 10 Load Capacitance between 100 MHz and 134 MHz, VDD > 2.25V — — 5 Load Capacitance, above 134 MHz, VDD > 2.25V — — 15 Load Capacitance, below 67 MHz, 1.71V < VDD < 2.25V Input Capacitance CIN — — 7 pF — Power-Up Time tPU 0.05 — 50 ms Power-up time for all VDD to reach minimum specified voltage (power ramps must be monotonic) Note 1: REF input has a threshold voltage of VDD/2.

 2026 Microchip Technology Inc. and its subsidiaries DS20007035A-page 3 PL133-67 SWITCHING CHARACTERISTICS Note 2 Electrical Characteristics: Parameter Symbol Min. Typ. Max. Units Conditions Operating Frequency f DC — 160 MHz V DD = 3.3V, 2.5V DC — 67 MHz V DD = 1.8V Duty Cycle = t2 ÷ t1 — 40 50 60 % Measured at V DD/2, Input is 50% Rise Time t3 — — 1.5 ns Measured between 0.8V and 2.0V Fall Time t4 — — 1.5 ns Measured between 0.8V and 2.0V Output to Output Skew Note 1 t5 — — 250 ps All outputs equally loaded. Propagation Delay, REF Rising Edge to CLKX Rising Edge Note 1 t6 1 5 9.2 ns Measured at V DD/2 Note 1: Parameter is ensured by design and characterization. 2: All parameters are specified with loaded outputs. NOISE CHARACTERISTICS Electrical Characteristics: Parameter Symbol Min. Typ. Max. Units Conditions Additive Phase Jitter — — 60 — fs VDD = 3.3V, Frequency = 100 MHz Integration range 12 kHz to 20 MHz

DS20007035A-page 4  2026 Microchip Technology Inc. and its subsidiaries TEMPERATURE SPECIFICATIONS (Note 1) Parameters Symbol Min. Typ. Max. Units Conditions Temperature Ranges Ambient Operating Temperature (T) T A –40 — +105 °C Ordering Option E –40 — +85 °C Ordering Option I 0 — +70 °C Ordering Option C Junction Temperature TJ — — +150 °C — Storage Temperature Range TS –65 — +150 °C — Package Thermal Resistance 16-Lead TSSOP RθJA — — 90 °C/W — Note 1: The maximum allowable power dissipation is a function of ambient temperature, the maximum allowable junction temperature and the thermal resistance from junction to air (i.e., TA, TJ, JA). Exceeding the maximum allowable power dissipation will cause the device operating junction temperature to exceed the maximum +150°C rating. Sustained junction temperatures above +150°C can impact the device reliability.

 2026 Microchip Technology Inc. and its subsidiaries DS20007035A-page 5 PL133-67

2.0 PIN DESCRIPTIONS

FIGURE 2-1: Pin Configuration, 16-Lead TSSOP Package. The descriptions of the pins are listed in Table 2-1. TABLE 2-1: PIN FUNCTION TABLE Pin Number P8in Name Type Description

1 REF I Input reference frequency

3 CLK0 O Buffered clock output

6 CLK1 O Buffered clock output

7 CLK2 O Buffered clock output

10 CLK3 O Buffered clock output

11 CLK4 O Buffered clock output

14 CLK5 O Buffered clock output

4, 13 VDD P VDD connection 5, 9, 12 GND P GND connection

8 OE I Output enable control input with 130 kΩ pull-up

2, 15, 16 DNC — Do not connect

DS20007035A-page 6  2026 Microchip Technology Inc. and its subsidiaries

3.0 NOMINAL PERFORMANCE CHARACTERISTICS

FIGURE 3-1: PL133-67 Additive Phase Jitter: VDD = 3.3V, CLK-100 MHz, Integration Range 12 kHz to 20 MHz, 0.059 ps Typical. When a buffer is used to pass a signal, the buffer will add a little bit of its own noise. The phase noise on the output of the buffer will be a little bit more than the phase noise in the input signal. The noise added by the buffer to the input signal is quantified by the additive phase jitter defined by the following formula: EQUATION 3-1: Note: The graphs and tables provided following this note are a statistical summary based on a limited number of samples and are provided for informational purposes only. The performance characteristics listed herein are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified operating range (e.g., outside specified power supply range) and therefore outside the warranted range. PLA133-67 AdditivePhaseJitter OutputPhaseJitter 2 InputPhaseJitter 2–=

 2026 Microchip Technology Inc. and its subsidiaries DS20007035A-page 7 PL133-67

4.0 SWITCHING WAVEFORMS

FIGURE 4-1: Duty Cycle Timing. FIGURE 4-2: All Outputs rise/Fall Time. FIGURE 4-3: Output to Output Skew. FIGURE 4-4: Input-Output Propagation Delay. VDD/2 VDD/2 t3 t 4 OUTPUT 0.8V 2.0V 3.3V 0.8V 2.0V OUTPUT OUTPUT VDD/2 VDD/2 INPUT OUTPUT VDD/2 VDD/2

DS20007035A-page 8  2026 Microchip Technology Inc. and its subsidiaries

5.0 TEST CIRCUIT

FIGURE 5-1: Test Circuit. VDD VDD GND GND OUTPUTS CLOAD CLK 0.1 PF 0.1 PF

 2026 Microchip Technology Inc. and its subsidiaries DS20007035A-page 9 PL133-67

6.0 LAYOUT RECOMMENDATIONS

The following guidelines are to assist you with a performance optimized PCB design:

6.1 Signal Integrity and Termination

• Keep traces short - Trace = Inductor. With a capacitive load this equals ringing - Long trace = Transmission Line. Without proper termination this will cause reflections ringing and waveforms and degradations. - Use stripline or microstrip with defined impedance for long traces (> 1 inch) - Match traces on one side of the board to avoid reflections bouncing back and forth.

6.2 Decoupling and Power Supply

• Place decoupling capacitors as close as pos- sible to the VDD pin(s) to limit noise from the power supply - Addition of a ferrite bead in series with VDD can help prevent noise from other board sources - Value of decoupling capacitor is frequency dependent. Typical values to use are 0.1 µF for designs using frequencies <50 MHz and 0.01 µF for designs using frequencies >50 MHz FIGURE 6-1: Typical CMOS Termination. Note: RS + R O (RO: Driver’s output impedance) should match the transmission line characteristic impedance (50Ω) to prevent reflections from the driver back to the receiver. Place Series Resistor as close as possible to CMOS output CMOS Output Buffer ( Typical buffer impedance 20 ohm) To CMOS Input 50 ohm line RS ȍ

DS20007035A-page 10  2026 Microchip Technology Inc. and its subsidiaries

7.0 PACKAGING INFORMATION

7.1 Package Marking Information

16-Lead TSSOP* WWNNN OC P133-67 25MA1 Legend: XX...X Product code, customer-specific information, or frequency in MHz without printed decimal point Y Year code (last digit of calendar year) YY Year code (last 2 digits of calendar year) WW Week code (week of January 1 is week ‘01’) NNN Alphanumeric traceability code Pb-free JEDEC ® designator for Matte Tin (Sn) * This package is Pb-free. The Pb-free JEDEC designator ( ) can be found on the outer packaging for this package.

• , ▲, ▼ Pin one index is identified by a dot, delta up, or delta down (triangle mark). Note: In the event the full Microchip part number cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for customer-specific information. Package may or may not include the corporate logo. Underbar (_) and/or Overbar (‾) symbol may not be to scale.

 2026 Microchip Technology Inc. and its subsidiaries DS20007035A-page 11 PL133-67 1 2 N TOP VIEW EE1 D A e 16X b NOTE 1 B A C

0.10 C B A

0.20 C B A

L (L1) c END VIEW SIDE VIEW Sheet 1 of 2Microchip Technology Drawing C04-00068 Rev B 16-Lead Plastic Thin Shrink Small Outline Package (D8X) 4.4mm Body [TSSOP]

DS20007035A-page 12  2026 Microchip Technology Inc. and its subsidiaries MILLIMETERS

0.65 BSC

5.00

6.40 BSC

-AOverall Height Foot Length Lead Width Standoff Overall Width Molded Package Length Molded Package Thickness L b 0.19 D E A1 0.05 Dimension Limits Pitch Number of Pins N e Units MIN 1.20- - 0.30 - 0.15 NOM MAX 0.600.45 0.75 BSC: Basic Dimension. Theoretically exact value shown without tolerances. REF: Reference Dimension, usually without tolerance, for information purposes only. Notes: protrusions shall not exceed 0.15mm per side. Molded Package Width E1 Foot Angle Footprint (L1)

1.00 REF

• 8° Lead Thickness c 0.09 - 0.20 4.30 4.40 4.50 1.051.000.80 4.90 5.10 Pin 1 visual index feature may vary, but must be located within the hatched area. Dimensions D and E1 do not include mold flash or protrusions. Mold flash or Dimensioning and tolerancing per ASME Y14.5M Sheet 2 of 2Microchip Technology Drawing C04-00068 Rev B 16-Lead Plastic Thin Shrink Small Outline Package (D8X) 4.4mm Body [TSSOP]

 2026 Microchip Technology Inc. and its subsidiaries DS20007035A-page 13 PL133-67 Dimension Limits Units G Optional Center Pad Width Contact Pad To Center Pad Contact Pad Spacing Clearance Between Contact Pads Contact Pitch X2 2.70 MILLIMETERS E MAX 5.90 Contact Pad Length (X16) Contact Pad Width (X16) 1.50 0.45 BSC: Basic Dimension. Theoretically exact value shown without tolerances. Notes: 1. Dimensioning and tolerancing per ASME Y14.5M Microchip Technology Drawing No. C04-02068 Rev B GXDistance Between Pads 0.20 NOM Optional Center Pad Length Y2 2.70 4.40 0.73 Z1Overall Width 7.40 E G GX SILK SCREEN RECOMMENDED LAND PATTERN 16-Lead Plastic Thin Shrink Small Outline Package (D8X) 4.4mm Body [TSSOP]

DS20007035A-page 14  2026 Microchip Technology Inc. and its subsidiaries NOTES:

 2026 Microchip Technology Inc. and its subsidiaries DS20007035A-page 15 PL133-67 APPENDIX A: REVISION HISTORY Revision A (January 2026)

• Converted Micrel legacy data sheet PL133-67 to Microchip data sheet DS20007035A.
• Minor text edits throughout.

DS20007035A-page 16  2026 Microchip Technology Inc. and its subsidiaries NOTES:

 2026 Microchip Technology Inc. and its subsidiaries DS20007035A-page 17 PL133-67 PRODUCT IDENTIFICATION SYSTEM To order or obtain information, e.g., on pricing or delivery, contact your local Microchip representative or sales office. Examples: Device: PL133-67: Low-Power DC to 160 MHz 1:6 Fanout Buffer IC Package: O = 16-Lead TSSOP Temperature Range: E = –40°C to +105°C I = –40°C to +85°C C = 0°C to +70°C Media Type: (blank) = 96/Tube R = 2,500/Reel Note 1: Tape and Reel identifier only appears in the catalog part number description. This identifier is used for ordering purposes and is not printed on the device package. Check with your Microchip Sales Office for package availability with the Tape and Reel option. a) PL133-67OE Low-Power DC to 160 MHz 1:6 Fanout Buffer IC, TSSOP Pack- age, –40°C to +105°C, 96/Tube b) PL133-67OE-R Low-Power DC to 160 MHz 1:6 Fanout Buffer IC, TSSOP Pack- age, –40°C to +105°C, 2,500/Reel c) PL133-67OI Low-Power DC to 160 MHz 1:6 Fanout Buffer IC, TSSOP Pack- age, –40°C to +85°C, 96/Tube d) PL133-67OI-R Low-Power DC to 160 MHz 1:6 Fanout Buffer IC, TSSOP Pack- age, –40°C to +85°C, 2,500/Reel e) PL133-67OC Low-Power DC to 160 MHz 1:6 Fanout Buffer IC, TSSOP Pack- age, 0°C to +70°C, 96/Tube f) PL133-67OC-R Low-Power DC to 160 MHz 1:6 Fanout Buffer IC, TSSOP Pack- age, 0°C to +70°C, 2,500/Reel PART NO. X X -X Device Package Temperature Range Media Type

DS20007035A-page 18  2026 Microchip Technology Inc. and its subsidiaries NOTES:

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