PL133-67 MICREL | Alldatasheet
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Technical content
Low -Power 2. 25V to 3. 63V DC to 150MHz 1:6 Fanout Buffer IC Micrel Inc. • 2180 Fortune Drive • San Jose, CA 95131 • USA • tel +1(408) 944 -0800 • fax +1(408) 474 -1000 • www.micrel.com Rev 03/18/11 Page 1
FEATURES
1:6 LVCMOS output fanout buffer for DC to 150 MHz 8mA Output Drive Strength Low power consumption for portable applications Low input -output delay Output -Output skew less than 250ps Low Additive Phase J itter of 6 0fs RMS 2.5V to 3.3V, ±10% operation Operating temperature range from -40°C to 85°C Available in 16 -Pin SOP GREEN/RoHS package
DESCRIPTION
The PL133 -67 is an advanced fanout buffer design for high performance, low -power, small form factor applic a- tions . The PL133 -67 accepts a reference clock input from DC to 150MHz and provides 6 outputs of the same fr e- quency. The PL133 -67 is offered in a TSSOP-16L package and it offers the best phase noise, additive jitter performance , and lowest power consumption of any compar able IC. The PL133 -67 outputs c an be disabled to a high impe d- ance (tri -state) by pulling low the OE pin. When the OE pin is high, the outputs are enabled and follow the REF input signal. When the OE pin is left open, a pull -up resistor on the chip will default the OE pin to logic 1 so t he outputs are enabled. BLOCK DIAGRAM AND PAC KAGE PINOUT REF CLK1 CLK2 CLK3 CLK4 CLK5 CLK6 1REF DNC CLK0 VDD DNC DNC CLK5 VDD GND CLK4 CLK3 GND OE^ CLK2 CLK1 GND TSSOP-16LOE
Low -Power 2. 25V to 3. 63V DC to 150MHz 1:6 Fanout Buffer IC Micrel Inc. • 2180 Fortune Drive • San Jose, CA 95131 • USA • tel +1 (408) 944 -0800 • fax +1(408) 474 -1000 • www.micrel.com Rev 03/18 /11 Page 2 PIN DESCRIPTIONS Name TSSOP-16L Type Description REF 1 I Input reference frequency. CLK0 3 O Buffered clock output CLK1 6 O Buffered clock output CLK2 7 O Buffered clock output CLK3 10 O Buffered clock output CLK4 11 O Buffered clock output CLK5 14 O Buffered clock output VDD 4, 1 3 P VDD connection GND 5, 9, 1 2 P GND connection OE 8 I Output Enable Control Input with 130K Pull -Up DNC 2, 8, 15, 16 - Do Not Connect LAYOUT RECOMMENDATIONS The following guidelines are to assist you with a performance optimized PCB d esign: Signal Integrity and Termination Consider ations - Keep traces short! - Trace = Inductor. Wit h a ca pacitive load this equals ringing! - Long trace = Transmission Line. Without proper term i- nation this will cause reflections ( looks like rin ging ). - Design long traces (> 1 inch) as “striplines” or “micr ostrips” with defined i mpedance. - Match trace at o ne side to avoid reflections bounc ing back and forth. Decoupling and Power Supply Considerations - Place decoupling capacitors as close as possible to the VDD pin(s) to limit noise from the power supply - Addition of a ferrite bead in series with VDD can help prevent noise from other board sources - Value of decoupling capacitor is frequency d e- pendant. Typical values to use are 0.1 F for d e- signs using frequencies < 50MHz and 0.01 F for designs using frequencies > 50MHz. Typical CMOS termination Place Series Resistor as close as possible to CMOS output CMOS Output Buffer ( Typical buffer impedance 20 ohm) To CMOS Input Connect a 33 ohm series resistor at each of the output clocks to enhance the stability of the output signal 50 ohm line
Low -Power 2. 25V to 3. 63V DC to 150MHz 1:6 Fanout Buffer IC Micrel Inc. • 2180 Fortune Drive • San Jose, CA 95131 • USA • tel +1 (408) 944 -0800 • fax +1(408) 474 -1000 • www.micrel.com Rev 03/18 /11 Page 3 ABSOLUTE MAXIMUM COND ITIONS Static Discharge Voltage (per MIL -STD -883, Method 3015)………… ..> 2000 V OPERATING CONDITIONS Parameter Description Min. Max. Unit VDD Supply Voltage 2.25 3.63 V TA Commercial Operating Temperature (ambient te mperature) 0 70 C Industrial Operating Temperature (ambient te mperature) -40 85 C CL Load Capacitance, below 1 00 MHz ― 30 pF Load Capacitance between 100 MHz and 134 MHz ― 10 pF Load Capacitance, above 134 MHz ― 5 pF CIN Input Capacitance ― 7 pF REF, CLK[1:6 ] Operating Frequency, I nput=Output DC 150 MHz tPU Power -up time for all V DD s to reach minimum specif ied vol tage (power ramps must be monotonic) 0.05 50 ms ELECTRICAL CHARACTERISTICS (Commercial and Industrial Temperature D evices) Parameter Description Test Conditions Min. Max. Unit VIL Input LOW Voltage [1] – 0.8 V VIH Input HIGH Voltage [1] 2.0 – V IIL Input LOW Current VIN = 0V – 50 µA IIH Input HIGH Current VIN = VDD – 100 µA VOL Output LOW Voltage [2] IOL = 8 mA – 0.4 V VOH Output HIGH Voltage [2] IOH = –8 mA 2.4 – V IDD Supply Current 66.67MHz with unloaded outputs – 32 mA RPU OE Pin Pull-Up Resistance 100 – K
Low -Power 2. 25V to 3. 63V DC to 150MHz 1:6 Fanout Buffer IC Micrel Inc. • 2180 Fortune Drive • San Jose, CA 95131 • USA • tel +1 (408) 944 -0800 • fax +1(408) 474 -1000 • www.micrel.com Rev 03/18 /11 Page 4 SWITCHING CHARACTERISTICS (Commercial and Industrial Temperature D evices) [3] Parameter Description Test Conditions Min. Typ. Max. Unit Duty Cycle [2] = t2 ÷ t1 Measured at 1.4V, Input is 50% 40 50 60 % t3 Rise Time [2] Measured between 0.8V and 2.0V – – 1.5 ns t4 Fall Time [2] Measured between 0.8V and 2.0V – – 1.5 ns t5 Output to Output Skew [2] All outputs equally loaded – – 250 ps t6 Propagation Delay, REF Rising Edge to CLKX Rising Edge [2] Measured at VDD/2 1 5 9.2 ns Notes: 1. REF input has a threshold voltage of V DD /2 2. Parameter is guaranteed by design and characterization. Not 100% tested in produ ction . 3. All parameters are specified with loaded outputs . NOISE CHARACTERISTICS (Commercia l and Industrial Temperature D evices ) Parameter Description Test Conditions Min. Typ. Max. Unit Additive Phase Jitter V DD=3.3V, Frequency=100MHz Offset=12KHz ~ 20MHz 60 fs PL133-67 Additive Phase Jitter: VDD=3.3V, CLK=100MHz, Integration Range 12KHz to 20MHz: 0.059ps typical. -160 -150 -140 -130 -120 -110 -100 -90 -80 -70 -60 10 100 1000 10000 100000 1000000 10000000 100000000 Offset Frequency (Hz) Phase Noise (dBc/Hz) REF Input PL133-67 Output When a buffer is used to pass a signal then the buffer will add a little bit of its own noise. The phase noise on the output of the buffer will be a little bit more than the phase noise in the input signal. To quantify the noise addition in the buffer we compare the Phase Jitter numbers from the input and the output. The difference is called "Additive Phase Jitter". The formula for the Additive Phase Jitter is as follows: Additive Phase Jitter = (Output Phase Jitter) - (Input Phase Jitter)
Low -Power 2. 25V to 3. 63V DC to 150MHz 1:6 Fanout Buffer IC Micrel Inc. • 2180 Fortune Drive • San Jose, CA 95131 • USA • tel +1 (408) 944 -0800 • fax +1(408) 474 -1000 • www.micrel.com Rev 03/18 /11 Page 5 SWITCHING WAVEFORMS TEST CIRCUIT 1.4V 1.4V VDD/2 INPUT OUTPUT VDD/2 1.4V OUTPUT OUTPUT 1.4V Duty Cycle Ti ming All Outputs Rise/Fall Time Output -Output Skew Input -Output Prop agation Delay t3 t4 OUTPUT 0.8V 2.0V 3.3V V 0.8V 2.0V VDD VDD GND GND OUTPUTS CL OAD CLK 0.1 F 0.1 F
Low -Power 2. 25V to 3. 63V DC to 150MHz 1:6 Fanout Buffer IC Micrel Inc. • 2180 Fortune Drive • San Jose, CA 95131 • USA • tel +1 (408) 944 -0800 • fax +1(408) 474 -1000 • www.micrel.com Rev 03/18 /11 Page 6 PACKAGE DRAWING (GREEN PACKAGE COMPLIANT) C L A E H D e B
16 PIN TSSOP ( mm )
Symbol Min. Max. A - 1.20 A1 0.05 0.15 B 0.19 0.30 C 0.09 0.20 D 4.90 5.10 E 4.30 4.50 H 6.40 BSC L 0.45 0.75 e 0.65 BSC
ORDERING INFORMATION
Micrel Inc., reserves the right to make changes in its products or specifications, or both at any time without notice. The in formation furnished by Micrel is believed to be accurate and reliable. However, Micrel makes no guarantee or warranty concerning the accuracy of said information and shall not be responsible for any loss or damage of whatever nature resulting from the use of, or reliance upon this product. LIFE SUPPORT POLICY : Micrel’s produ cts are not authorized for use as critical components in life support devices or systems without the express written approval of the President of Micrel Inc. For part ordering, please contact our Sales Department:
2180 Fortune Drive , San Jose, CA 95131 , USA
Tel: (408) 944 -0800 Fax: (408) 474 -1000 PART NUMBER The order number for this device is a combination of the follo wing: Part number, Package type and Opera ting temperature range PL133-67 X X - X Part Number Package Type O=TSSOP None=Tubes R=Tape & Reel Temperature Range C=Commercial (0°C to 70°C) I=Industrial (-40°C to 85°C) Part/Order Nu mber Marking Package Option Green (Lead -Free) Package PL13 3-67OC P133-67 OC LLLLL 16-Pin TSSOP Tube PL133-67OC-R 16-Pin TSSOP (Tape and Reel) PL133-67OI P133-67 OI LLLLL 16-Pin TSSOP Tu be PL13 3-67OI-R 16-Pin TSSOP (Tape and Reel) *Note: LLL LL designates lot number