PL133-47SI-R

PL133-47_V01 MICROCHIP | Alldatasheet

Document overview

• Manufacturer or author: Provided By alldatasheet.com(free datasheet download site)
• PDF pages: 17

Technical content

Features

• 1:4 LVCMOS Output Fanout Buffer from DC to160 MHz
• Low Additive Phase Jitter of 60 fsRMS
• 8 mA Output Drive Strength
• Low Power Consumption for Portable

Applications

• Low Input-Output Delay
• Output-Output Skew <250 ps
• 2.5V to 3.3V, ±10% Operation
• 1.8V +10%/–5% Operation up to 67 MHz
• Operating Temperature Range: –40°C to +85°C or 0°C to +70°C
• Available in 8-Lead SOIC Package
• Low Power Applications General Description The PL133-47 is an advanced fanout buffer designed for high performance, low-power, small form factor applications. The PL133-47 accepts a reference clock input from DC to 160 MHz and provides four outputs of the same frequency with ultra-low additive jitter. The PL133-47 is available in a SOIC-8L package. Functional Block Diagram REF CLK0 CLK1 CLK2 CLK3 Low-Power DC to 160 MHz 1:4 Fanout Buffer IC

DS20007034A-page 2  2026 Microchip Technology Inc. and its subsidiaries

1.0 ELECTRICAL CHARACTERISTICS

Absolute Maximum Ratings † Static Discharge Voltage Operating Ratings † † Notice: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operational sections of this specification is not intended. Exposure to maximum rating conditions for extended periods may affect device reliability.

ELECTRICAL CHARACTERISTICS

Parameter Symbol Min. Typ. Max. Units Conditions Input Low Voltage VIL — — 0.3xV DD V Note 1 Input High Voltage VIH 0.7xVDD — — V Note 1 Input Low Current IIL — — 50 µA V IN = 0V Input High Current IIH — — 100 µA V IN = VDD Supply Current IDD — — 32 mA 66.67 MHz with unloaded outputs Output Low Voltage VOL — — 0.5 V IO = 8 mA, VDD = 3.3V — — 0.5 IO = 6 mA, VDD = 2.5V — — 0.5 IO = 4 mA, VDD = 1.8V Output High Voltage V OH VDD - 0.5 — — V IO = –8 mA, VDD = 3.3V VDD - 0.5 — — IO = –6 mA, VDD = 2.5V VDD - 0.5 — — IO = –4 mA, VDD = 1.8V Load Capacitance CL — — 30 pF Load Capacitance, below 100 MHz, VDD > 2.25V — — 10 Load Capacitance between 100 MHz and 134 MHz, VDD > 2.25V — — 5 Load Capacitance, above 134 MHz, VDD > 2.25V — — 15 Load Capacitance, below 67 MHz, 1.71V < VDD < 2.25V Input Capacitance CIN — — 7 pF — Power-Up Time tPU 0.05 — 50 ms Power-up time for all VDD to reach minimum specified voltage (power ramps must be monotonic) Note 1: REF input has a threshold voltage of VDD/2.

 2026 Microchip Technology Inc. and its subsidiaries DS20007034A-page 3 PL133-47 SWITCHING CHARACTERISTICS Note 2 Parameter Symbol Min. Typ. Max. Units Conditions Operating Frequency f DC — 160 MHz V DD = 3.3V, 2.5V DC — 67 MHz V DD = 1.8V Duty Cycle = t2 ÷ t1 — 40 50 60 % Measured at 1.4V, Input is 50% Rise Time t3 — — 1.5 ns Measured between 0.8V and 2.0V Fall Time t4 — — 1.5 ns Measured between 0.8V and 2.0V Output to Output Skew Note 1 t5 — — 250 ps All outputs equally loaded Propagation Delay, REF Rising Edge to CLKX Rising Edge Note 1 t6 1 5 9.2 ns Measured at V DD/2 Note 1: Parameter is ensured by design and characterization. 2: All parameters are specified with loaded outputs. NOISE CHARACTERISTICS Parameter Symbol Min. Typ. Max. Units Conditions Additive Phase Jitter — — 60 — fs VDD = 3.3V, Frequency = 100 MHz Integration range 12 kHz to 20 MHz TEMPERATURE SPECIFICATIONS (Note 1) Parameters Symbol Min. Typ. Max. Units Conditions Temperature Ranges Ambient Operating Temperature TA –40 — +85 °C Ordering Option I 0 — +70 °C Ordering Option C Junction Temperature TJ — — +150 °C — Storage Temperature Range TS –65 — +150 °C — Package Thermal Resistance 8-Lead SOIC RθJA — — 103.2 °C/W — Note 1: The maximum allowable power dissipation is a function of ambient temperature, the maximum allowable junction temperature and the thermal resistance from junction to air (i.e., TA, TJ, JA). Exceeding the maximum allowable power dissipation will cause the device operating junction temperature to exceed the maximum +150°C rating. Sustained junction temperatures above +150°C can impact the device reliability.

DS20007034A-page 4  2026 Microchip Technology Inc. and its subsidiaries

2.0 PIN DESCRIPTIONS

FIGURE 2-1: Pin Configuration, 8-Lead SOIC Package. The descriptions of the pins are listed in Table 2-1. TABLE 2-1: PIN FUNCTION TABLE Pin Number Pin Name Type Description 1, 2 VDD P VDD connection

3 REF I Input reference frequency

4 GND P GND connection

5 CLK0 O Buffered clock output

6 CLK1 O Buffered clock output

7 CLK2 O Buffered clock output

8 CLK3 O Buffered clock output

 2026 Microchip Technology Inc. and its subsidiaries DS20007034A-page 5 PL133-47

3.0 NOMINAL PERFORMANCE CHARACTERISTICS

FIGURE 3-1: PL133-47 Additive Phase Jitter: VDD = 3.3V, CLK-100 MHz, Integration Range 12 kHz to 20 MHz, 0.059 ps Typical. When a buffer is used to pass a signal, the buffer will add a little bit of its own noise. The phase noise on the output of the buffer will be a little bit more than the phase noise in the input signal. The noise added by the buffer to the input signal is quantified by the additive phase jitter defined by the following formula: EQUATION 3-1: Note: The graphs and tables provided following this note are a statistical summary based on a limited number of samples and are provided for informational purposes only. The performance characteristics listed herein are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified operating range (e.g., outside specified power supply range) and therefore outside the warranted range. PLA133-47 AdditivePhaseJitter OutputPhaseJitter 2 InputPhaseJitter 2–=

DS20007034A-page 6  2026 Microchip Technology Inc. and its subsidiaries

4.0 SWITCHING WAVEFORMS

FIGURE 4-1: Duty Cycle Timing. FIGURE 4-2: All Outputs Rise/Fall Time. FIGURE 4-3: Output to Output Skew. FIGURE 4-4: Input-Output Propagation Delay. VDD/2 VDD/2 t3 t 4 OUTPUT 0.8V 2.0V 3.3V 0.8V 2.0V OUTPUT OUTPUT VDD/2 VDD/2 INPUT OUTPUT VDD/2 VDD/2

 2026 Microchip Technology Inc. and its subsidiaries DS20007034A-page 7 PL133-47

5.0 TEST CIRCUIT

FIGURE 5-1: Test Circuit. VDD VDD GND GND OUTPUTS CLOAD CLK 0.1 PF 0.1 PF

DS20007034A-page 8  2026 Microchip Technology Inc. and its subsidiaries

6.0 LAYOUT RECOMMENDATIONS

The following guidelines are to assist you with a performance optimized PCB design:

6.1 Signal Integrity and Termination

• Keep traces short - Trace = Inductor. With a capacitive load this equals ringing - Long trace = Transmission Line. Without proper termination this will cause reflections ringing and waveforms and degradations. - Use stripline or microstrip with defined impedance for long traces (> 1 inch) - Match traces on one side of the board to avoid reflections bouncing back and forth.

6.2 Decoupling and Power Supply

• Place decoupling capacitors as close as pos- sible to the VDD pin(s) to limit noise from the power supply - Addition of a ferrite bead in series with VDD can help prevent noise from other board sources - Value of decoupling capacitor is frequency dependent. Typical values to use are 0.1 µF for designs using frequencies <50 MHz and 0.01 µF for designs using frequencies >50 MHz FIGURE 6-1: Typical CMOS Termination. Place Series Resistor as close as possible to CMOS output CMOS Output Buffer ( Typical buffer impedance 20 ohm) To CMOS Input 50 ohm line RS ȍ

 2026 Microchip Technology Inc. and its subsidiaries DS20007034A-page 9 PL133-47

7.0 PACKAGING INFORMATION

7.1 Package Marking Information

8-Lead SOIC* WWNNN SI P133-47 25DK2 Legend: XX...X Product code, customer-specific information, or frequency in MHz without printed decimal point Y Year code (last digit of calendar year) YY Year code (last 2 digits of calendar year) WW Week code (week of January 1 is week ‘01’) NNN Alphanumeric traceability code Pb-free JEDEC ® designator for Matte Tin (Sn) * This package is Pb-free. The Pb-free JEDEC designator ( ) can be found on the outer packaging for this package.

• , ▲, ▼ Pin one index is identified by a dot, delta up, or delta down (triangle mark). Note: In the event the full Microchip part number cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for customer-specific information. Package may or may not include the corporate logo. Underbar (_) and/or Overbar (‾) symbol may not be to scale.

DS20007034A-page 10  2026 Microchip Technology Inc. and its subsidiaries

0.25 C A–B D

C SEATING PLANE TOP VIEW SIDE VIEW VIEW A–A 0.10 C 0.10 C Microchip Technology Drawing No. C04-057-C2X Rev K Sheet 1 of 2 For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging Note: 8-Lead Plastic Small Outline (C2X) - Narrow, 3.90 mm (.150 In.) Body [SOIC] 1 2 N ș c 4X ș1 4X ș1 (L1) L h h A2A A B e D E E 2E1 NOTE 5 NOTE 5 NX b

0.10 C A–B

H R VIEW C SEE VIEW C NOTE 1 D Atmel Legacy Global Package Code SWB

 2026 Microchip Technology Inc. and its subsidiaries DS20007034A-page 11 PL133-47 Microchip Technology Drawing No. C04-057-C2X Rev K Sheet 2 of 2 8-Lead Plastic Small Outline (C2X) - Narrow, 3.90 mm (.150 In.) Body [SOIC] For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging Note: protrusions shall not exceed 0.15mm per side. 3. Dimensions D and E1 do not include mold flash or protrusions. Mold flash or REF: Reference Dimension, usually without tolerance, for information purposes only. BSC: Basic Dimension. Theoretically exact value shown without tolerances. 1. Pin 1 visual index feature may vary, but must be located within the hatched area. 2. § Significant Characteristic 4. Dimensioning and tolerancing per ASME Y14.5M Notes: 5. Datums A & B to be determined at Datum H. Atmel Legacy Global Package Code SWB Foot Angle 0° – 8° ––0°Lead Angle 0.51–0.31bLead Width 0.25–0.17cLead Thickness 1.27–0.40LFoot Length 0.50–0.25hChamfer (Optional)

4.90 BSCDOverall Length

3.90 BSCE1Molded Package Width

6.00 BSCEOverall Width

0.25–0.10A1Standoff -–1.25A2Molded Package Thickness 1.75–– AOverall Height

1.27 BSCePitch

Footprint L1 1.04 REF Mold Draft Angle 5° – 15° ș ––0.07R1Lead Bend Radius ––0.07RLead Bend Radius

DS20007034A-page 12  2026 Microchip Technology Inc. and its subsidiaries RECOMMENDED LAND PATTERN Microchip Technology Drawing C04-2057-C2X Rev K BSC: Basic Dimension. Theoretically exact value shown without tolerances. Notes: Dimensioning and tolerancing per ASME Y14.5M1. For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging Note: Dimension Limits Units CContact Pad Spacing Contact Pitch MILLIMETERS

1.27 BSC

E MAX 5.40 Contact Pad Length (X8) Contact Pad Width (X8) 1.55 0.60 NOM E C SILK SCREEN 8-Lead Plastic Small Outline (C2X) - Narrow, 3.90 mm (.150 In.) Body [SOIC]

 2026 Microchip Technology Inc. and its subsidiaries DS20007034A-page 13 PL133-47 APPENDIX A: REVISION HISTORY Revision A (January 2026)

• Converted Micrel legacy data sheet PL133-47 to Microchip data sheet DS20007034A.
• Minor text edits throughout.

DS20007034A-page 14  2026 Microchip Technology Inc. and its subsidiaries NOTES:

 2026 Microchip Technology Inc. and its subsidiaries DS20007034A-page 15 PL133-47 PRODUCT IDENTIFICATION SYSTEM To order or obtain information, e.g., on pricing or delivery, contact your local Microchip representative or sales office. Examples: Device: PL133-47: Low-Power DC to 160 MHz 1:4 Fanout Buffer IC Package: S = 8-Lead SOIC Package Temperature Range: C = 0°C to +70°C I = –40°C to +85°C Media Type: (blank) = 100/Tube R = 2,500/Reel Note 1: Tape and Reel identifier only appears in the catalog part number description. This identifier is used for ordering purposes and is not printed on the device package. Check with your Microchip Sales Office for package availability with the Tape and Reel option. a) PL133-47SC Low-Power DC to 160 MHz 1:4 Fanout Buffer IC, SOIC Package, 0°C to +70°C, 100/ Tube b) PL133-47SC-R Low-Power DC to 160 MHz 1:4 Fanout Buffer IC, SOIC Package, 0°C to +70°C, 2,500/Reel c) PL133-47SI Low-Power DC to 160 MHz 1:4 Fanout Buffer IC, SOIC Package, –40°C to +85°C, 100/ Tube d) PL133-47SI-R Low-Power DC to 160 MHz 1:4 Fanout Buffer IC, SOIC Package, –40°C to +85°C, 2,500/Reel PART NO. X X -X Device Package Temperature Range Media Type

DS20007034A-page 16  2026 Microchip Technology Inc. and its subsidiaries NOTES:

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