PL133-21

PL133-21 MICROCHIP | Alldatasheet

Document overview

• Manufacturer or author: Provided By alldatasheet.com(free datasheet download site)
• PDF pages: 14

Technical content

Features

• Two LVCMOS Outputs
• Input/Output Frequency: 1 MHz to 150 MHz
• Supports LVCMOS or Sine-Wave Input Clock
• Output Enable (OE) only Controls CLK0. CLK1 is Always On.
• Extremely Low Additive Jitter
• 8 mA Output Drive Strength
• Low Current Consumption
• Single 1.8V, 2.5V, or 3.3V ±10% Power Supply
• Operating Temperature Range: - 0° to +70°C (Commercial) - –40° to +85°C (Industrial)
• Available in TDFN-6L Green/RoHS-Compliant Package Package Type General Description The PL133-21 is an advanced inverting fanout buffer design for high performance, low-power, small form-factor applications. The PL133-21 accepts a reference clock input of 1 MHz to 150 MHz and produces two outputs of the same frequency. Reference clock inputs may be LVCMOS or sine-wave signals (the inputs are internally AC-coupled). PL133-21 is designed to fit in a small 2mm x 1.3 mm x 0.6 mm TDFN package and offers the best phase noise, jitter performance, and lowest power consumption of any comparable IC. Functional Block Diagram PL133-21 2 mm x 1.3 mm TDFN (Top View) FIN GND OE VDD CLK0 CLK1 FIN CLK1 CLK0 OE Low-Power, 1.62V to 3.63V , 1:2 Inverting Fanout Buffer IC

DS20006309B-page 2  2020 Microchip Technology Inc.

1.0 ELECTRICAL CHARACTERISTICS

Absolute Maximum Ratings † † Notice: Exposure of the device under conditions beyond the limits specified by Maximum Ratings for extended periods may cause permanent damage to the device and affect product reliability. These conditions represent a stress rating only, and functional operations of the device at these or any other conditions above the operational limits noted in this specification is not implied. Parts are tested to commercial grade only. AC ELECTRICAL CHARACTERISTICS Parameter Symbol Min. Typ. Max. Units Conditions Input Frequency fIN 1 — 150 MHz @ VDD = 2.5V and 3.3V 1 — 65 @ VDD = 1.8V Input Signal Amplitude 0.8 — VDD VPP Internally AC-coupled Output Rise Time tr — 2 3 ns 15 pF Load, 10/90%VDD, 3.3V Output Fall Time tf — 2 3 ns 15 pF Load, 90/10%VDD, 3.3V Output-to-Output Skew — — 500 ps — Duty Cycle 45 50 55 % Input duty cycle is 50% DC ELECTRICAL CHARACTERISTICS Parameter Symbol Min. Typ. Max. Units Condition Supply Current, Dynamic IDD — 1.8 — mA VDD = 3.3V, 25 MHz, No Load — 1.3 — VDD = 2.5V, 25 MHz, No Load — 0.8 — VDD = 1.8V, 25 MHz, No Load Operating Voltage VDD 1.62 — 3.63 V — Output Low Voltage VOL — — 0.4 V IOL = +4 mA, VDD = 3.3V Output High Voltage VOH 2.4 — — V IOL = –4 mA, VDD = 3.3V Output Current IOSD 8 — — mA VOL = 0.4V, VOH = 2.4V, VDD = 3.3V TEMPERATURE SPECIFICATIONS Parameters Sym. Min. Typ. Max. Units Conditions Temperature Ranges Ambient Operating Temperature TA –40 — +85 °C — Storage Temperature TS –65 — +150 °C —

 2020 Microchip Technology Inc. DS20006309B-page 3 PL133-21

2.0 NOISE CHARACTERISTICS

FIGURE 2-1: PL133-21 Additive Phase Jitter. VDD = 3.3V, CLK = 26 MHz, Integration Range: 12 kHz to 5 MHz, 0.127 ps Typical. When a buffer is used to pass a signal then the buffer will add a little bit of its own noise. The phase noise on the output of the buffer will be a little bit more than the phase noise in the input signal. To quantify the noise addition in the buffer we compare the Phase Jitter numbers from the input and the output. The difference is called Additive Phase Jitter. The formula for the Additive Phase Jitter is as follows: EQUATION 2-1: TABLE 2-1: NOISE CHARACTERISTICS Parameter Symbol Min. Typ. Max. Units Conditions Additive Phase Jitter — 130 — fs VDD = 3.3V, Frequency = 26 MHz Offset = 12 kHz ~ 5 MHz — 150 — VDD = 3.3V, Frequency = 100 MHz Offset = 12 kHz ~ 20 MHz -170 -160 -150 -140 -130 -120 -110 -100 -90 -80 -70 10 100 1000 10000 100000 1000000 10000000 Offset Frequency (Hz) Phase Noise (dBc/Hz) REF Input PL133-21 Output Additive Phase Jitter Output Phase Jitter2 Input Phase Jitter2–=

DS20006309B-page 4  2020 Microchip Technology Inc.

3.0 PIN DESCRIPTIONS

The descriptions of the pins are listed in Table 3-1.

3.1 Layout Recommendations

The following guidelines are to assist you with a performance-optimized PCB design.

3.1.1 SIGNAL INTEGRITY AND

TERMINATION CONSIDERATIONS

• Keep traces short.
• Trace = Inductor. With a capacitive load this equals ringing.
• Long trace = Transmission Line. Without proper termination this will cause reflections (looks like ringing).
• Design long traces as “striplines” or “microstrips” with defined impedance.
• Match trace at one side to avoid reflections bouncing back and forth.

3.1.2 DECOUPLING AND POWER

• Place decoupling capacitors as close as possible to the VDD pin to limit noise from the power supply.
• Multiple VDD pins should be decoupled separately for best performance.
• The addition of a ferrite bead in series with VDD can help prevent noise from other board sources.
• The value of decoupling capacitor is frequency dependent. Typical values to use are 0.1 µF for designs using crystals <50 MHz and 0.01 µF for designs using crystals >50 MHz. FIGURE 3-1: Typical CMOS Termination. TABLE 3-1: PIN FUNCTION TABLE Pin Number Pin Name Pin Type Description 1 FIN I Reference clock input. 2 CLK1 O Clock output (inverted). 3 GND P Ground connection. 4 CLK0 O Clock output (inverted). 5 VDD P VDD connection. 6 OE I Output enable input. ȍ/LQH 7R&026,QSXW &0262XWSXW%XIIHU 7\\SLFDOEXIIHULPSHGDQFH ȍ 3ODFHVHULHVUHVLVWRUDVFORVHDVSRVVLEOHWR&026RXWSXW 6HULHV5HVLVWRU 8VHYDOXHWRPDWFKRXWSXWEXIIHULPSHGDQFHWR ȍWUDFH7\\SLFDOYDOXHȍ

 2020 Microchip Technology Inc. DS20006309B-page 5 PL133-21

4.0 PACKAGING INFORMATION

4.1 Package Marking Information

Example6-Lead TDFN* XXX NNN H21 511 Legend: XX...X Product code or customer-specific information Y Year code (last digit of calendar year) YY Year code (last 2 digits of calendar year) WW Week code (week of January 1 is week ‘01’) NNN Alphanumeric traceability code Pb-free JEDEC® designator for Matte Tin (Sn) * This package is Pb-free. The Pb-free JEDEC designator ( ) can be found on the outer packaging for this package.

• , ▲, ▼ Pin one index is identified by a dot, delta up, or delta down (triangle mark). Note: In the event the full Microchip part number cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for customer-specific information. Package may or may not include the corporate logo. Underbar (_) and/or Overbar (‾) symbol may not be to scale.

DS20006309B-page 6  2020 Microchip Technology Inc. Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging.

 2020 Microchip Technology Inc. DS20006309B-page 7 PL133-21 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging.

DS20006309B-page 8  2020 Microchip Technology Inc. NOTES:

 2020 Microchip Technology Inc. DS20006309B-page 9 PL133-21 APPENDIX A: REVISION HISTORY Revision A (February 2020)

• Converted Micrel document PL133-21 to Micro- chip data sheet DS20006309A.
• Minor text changes throughout. Revision B (October 2020)
• Added the word Inverting in the data sheet title and updated Functional Block Diagram.

DS20006309B-page 10  2020 Microchip Technology Inc. NOTES:

 2020 Microchip Technology Inc. DS20006309B-page 11 PL133-21 PRODUCT IDENTIFICATION SYSTEM To order or obtain information, e.g., on pricing or delivery, contact your local Microchip representative or sales office. Device: PL133-21: Low-Power, 1.62V to 3.63V, 1:2 Fanout Buffer IC Package: G = 6-Lead 2 mm x 1.3 mm TDFN Temperature Range: C = 0°C to +70°C (NiPdAu Lead-Free) Tape and Reel: <blank>= 20/Bag R = 3,000/Reel Note 1: Tape and Reel identifier only appears in the catalog part number description. This identifier is used for ordering purposes and is not printed on the device package. Check with your Microchip Sales Office for package availability with the Tape and Reel option. Examples: a) PL133-21GC: PL133-21, 6-Lead TDFN, 0°C to +70°C Temperature Range, 20/Bag b) PL133-21GC-R: PL133-21, 6-Lead TDFN, 0°C to +70°C Temperature Range, 3,000/Reel Part No. X X -X Device Package Temp. Range Packing

DS20006309B-page 12  2020 Microchip Technology Inc. NOTES:

 2020 Microchip Technology Inc. DS20006309B-page 13 Information contained in this publication is provided for the sole purpose of designing with and using Microchip products. Infor- mation regarding device applications and the like is provided only for your convenience and may be superseded by updates. It is your responsibility to ensure that your application meets with your specifications. THIS INFORMATION IS PROVIDED BY MICROCHIP "AS IS". MICROCHIP MAKES NO REPRESENTATIONS OR WAR - RANTIES OF ANY KIND WHETHER EXPRESS OR IMPLIED, WRITTEN OR ORAL, STATUTORY OR OTHERWISE, RELATED TO THE INFORMATION INCLUDING BUT NOT LIMITED TO ANY IMPLIED WARRANTIES OF NON- INFRINGEMENT, MERCHANTABILITY, AND FITNESS FOR A PARTICULAR PURPOSE OR WARRANTIES RELATED TO ITS CONDITION, QUALITY, OR PERFORMANCE. IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDI- RECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUEN- TIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE INFORMATION OR ITS USE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY RELATED TO THE INFORMATION OR ITS USE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY , THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THE INFORMATION. Use of Microchip devices in life sup- port and/or safety applications is entirely at the buyer's risk, and the buyer agrees to defend, indemnify and hold harmless Microchip from any and all damages, claims, suits, or expenses resulting from such use. No licenses are conveyed, implicitly or otherwise, under any Microchip intellectual property rights unless otherwise stated. Trademarks The Microchip name and logo, the Microchip logo, Adaptec, AnyRate, AVR, AVR logo, AVR Freaks, BesTime, BitCloud, chipKIT, chipKIT logo, CryptoMemory, CryptoRF, dsPIC, FlashFlex, flexPWR, HELDO, IGLOO, JukeBlox, KeeLoq, Kleer, LANCheck, LinkMD, maXStylus, maXTouch, MediaLB, megaAVR, Microsemi, Microsemi logo, MOST, MOST logo, MPLAB, OptoLyzer, PackeTime, PIC, picoPower, PICSTART, PIC32 logo, PolarFire, Prochip Designer, QTouch, SAM-BA, SenGenuity, SpyNIC, SST, SST Logo, SuperFlash, Symmetricom, SyncServer, Tachyon, TempTrackr, TimeSource, tinyAVR, UNI/O, Vectron, and XMEGA are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. APT, ClockWorks, The Embedded Control Solutions Company, EtherSynch, FlashTec, Hyper Speed Control, HyperLight Load, IntelliMOS, Libero, motorBench, mTouch, Powermite 3, Precision Edge, ProASIC, ProASIC Plus, ProASIC Plus logo, Quiet-Wire, SmartFusion, SyncWorld, Temux, TimeCesium, TimeHub, TimePictra, TimeProvider, Vite, WinPath, and ZL are registered trademarks of Microchip Technology Incorporated in the U.S.A. Adjacent Key Suppression, AKS, Analog-for-the-Digital Age, Any Capacitor, AnyIn, AnyOut, BlueSky, BodyCom, CodeGuard, CryptoAuthentication, CryptoAutomotive, CryptoCompanion, CryptoController, dsPICDEM, dsPICDEM.net, Dynamic Average Matching, DAM, ECAN, EtherGREEN, In-Circuit Serial Programming, ICSP, INICnet, Inter-Chip Connectivity, JitterBlocker, KleerNet, KleerNet logo, memBrain, Mindi, MiWi, MPASM, MPF, MPLAB Certified logo, MPLIB, MPLINK, MultiTRAK, NetDetach, Omniscient Code Generation, PICDEM, PICDEM.net, PICkit, PICtail, PowerSmart, PureSilicon, QMatrix, REAL ICE, Ripple Blocker, SAM-ICE, Serial Quad I/O, SMART-I.S., SQI, SuperSwitcher, SuperSwitcher II, Total Endurance, TSHARC, USBCheck, VariSense, ViewSpan, WiperLock, Wireless DNA, and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. The Adaptec logo, Frequency on Demand, Silicon Storage Technology, and Symmcom are registered trademarks of Microchip Technology Inc. in other countries. GestIC is a registered trademark of Microchip Technology Germany II GmbH & Co. KG, a subsidiary of Microchip Technology Inc., in other countries. All other trademarks mentioned herein are property of their respective companies. © 2020, Microchip Technology Incorporated, All Rights Reserved. ISBN: 978-1-5224-6893-6 Note the following details of the code protection feature on Microchip devices:

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