PL123E-09HOI-R

PL123E-09 MICREL | Alldatasheet

Document overview

• Manufacturer or author: Provided By ALLDATASHEET.COM(FREE DATASHEET DOWNLOAD SITE)
• PDF pages: 10

Technical content

(Preliminary ) PL123E -09 Low Skew Zero Delay Buffer Micrel Inc. • 2180 Fortune Drive • San Jose, CA 95131 • USA • tel +1(408) 944 -0800 • fax +1(408) 474 -1000 • www.micrel.com Rev 12 /13 /11 Page 1

FEATURES

 Frequency R ange 10MHz to 220MHz  Zero input - output delay.  Low Output to Output Skew  Optional Drive Strength: Standard (8mA) PL123E -09 High (12mA) PL123E -09H  2.5V or 3.3V , ±10% operation.  Available in 16 -Pin SOP or TSSOP packages

DESCRIPTION

The PL123E -09 (-09H for High Drive) is a high pe rfor- mance, low skew, low jitter zero delay buffer d esigned to distribute high speed clocks . It has two low -skew output banks , of 4 outputs each , that a re sy nchronized with the input. Control of the two banks o f outputs is achieved by using the S1 and S2 inputs as shown in the Selector Definition table on page 2. The synchronization is esta blished via CLKOUT feed back to the input of the PLL. Since the skew between the input and ou tput is less than 100 ps, the device acts as a zero delay buffer. The input output propag a- tion delay can be advanced or delayed by a djusting the load on the CLKOUT pin. These parts are not intended for 5V input -tolerant a p- plica tions. BLOCK DIAGRAM PLLREF CLKOUT CLKA1 CLKA2 CLKA3 CLKA4 Selector Inputs Mux CLKB1 CLKB2 CLKB3 CLKB4 1REF CLKA1 CLKA2 VDD CLKOUT CLKA4 CLKA3 VDD GND CLKB4 CLKB3 CLKB2 CLKB1 GND Bank B Bank A

(Preliminary ) PL123E -09 Low Skew Zero Delay Buffer Micrel Inc. • 2180 Fortune Drive • San Jose, CA 95131 • USA • tel +1(408) 944 -0800 • fax +1(408) 474 -1000 • www.micrel.com Rev 12 /13 /11 Page 2 PIN DESCRIPTIONS Name Package T ype Type Description TSSOP -16L SOP-16L REF[1 ] 1 1 I Input reference frequency. CLKA1[2 ] 2 2 O Buffered clock output, Bank A CLKA2[2 ] 3 3 O Buffered clock output, Bank A VDD 4,13 4,13 P VDD connection GND 5,12 5,12 P GND connection CLKB1[2 ] 6 6 O Buffered clock output, Bank B CLKB2[2 ] 7 7 O Buffered clock output, Bank B S2[3 ] 8 8 I Selector input S1[3 ] 9 9 I Selector input CLKB3[2 ] 10 10 O Buffered clock output, Bank B CLKB4[2 ] 11 11 O Buffered clock output, Bank B CLKA3[2 ] 14 14 O Buffered clock output, Bank A CLKA4[2 ] 15 15 O Buffered clock output, Bank A CLKOUT [2 ] 16 16 O Buffered clock output. Internal feedback on this pin. Notes: 1: Weak pull -down. 2: Weak pull -down on all outputs. 3: Weak Pull -Up on S1 and S2 SELECTOR DEFINITION S2 S1 CLOCK A1–A4 (Bank A) CLOCK B1–B4 (Bank B) CLKOU T Output Source PLL Shutdown 0 0 Three -state Three -state Driven PLL N 0 1 Driven Three -state Driven PLL N 1 0 Driven Driven Driven Reference Y 1 1 Driven Driven Driven PLL N INPUT / OUTPUT SKEW CO NTROL The PL 123E -09 will achieve Zero Delay from input to output when all the outputs are loaded equally . Adjus t- ments to the input/output delay can be made by adding additional loading to the CLKOUT pin. Please contact Micrel for more information.

(Preliminary ) PL123E -09 Low Skew Zero Delay Buffer Micrel Inc. • 2180 Fortune Drive • San Jose, CA 95131 • USA • tel +1(408) 944 -0800 • fax +1(408) 474 -1000 • www.micrel.com Rev 12 /13 /11 Page 3 LAYOUT RECOMMENDATIONS The following guidelines are to assist you with a pe rformance optimized PCB design: Signal Integrity and Termination Consider ations - Keep traces short! - Trace = Inductor. With a capacitive load this equals ringing! - Long trace = T ransmission Line. Without proper term i- nation this will cause reflections ( looks like rin ging ). - Design long traces as “striplines” or “m icrostrips” with defined impedance. - Match trace at one side to avoid reflections boun cing back and forth. Decoupl ing and Power Supply Considerations - Place decoupling capacitors as close as possible to the VDD pin(s) to limit noise from the power supply - Addition of a ferrite bead in series with VDD can help prevent noise from other board sources - Value of decoup ling capacitor is frequency depen d- ant. Typical values to use are 0.1 F for designs using frequencies < 50MHz and 0.01 F for designs using frequencies > 50MHz. Typical CMOS termination Place Series Resistor as close as possible to CMOS output CMOS Output Buffer ( Typical buffer impedance 20  To CMOS Input 50 line Connect a 33 series resistor at each of the output clocks to enhance the stability of the output signal

(Preliminary ) PL123E -09 Low Skew Zero Delay Buffer Micrel Inc. • 2180 Fortune Drive • San Jose, CA 95131 • USA • tel +1(408) 944 -0800 • fax +1(408) 474 -1000 • www.micrel.com Rev 12 /13 /11 Page 4 ABSOLUTE MAXIMUM CONDITIONS Static Discharge Voltage (per MIL -STD -883, Method 3015)………… …..> 2000V OPERATING CONDITIONS Description Param eter Min Max Unit Supply V oltage VDD 2.25 3.63 V Load Capacitance, <100 MHz, 3.3V CL [4 ] – 30 pF Load Capacitance, <100 MHz, 2.5V with High Drive – 30 pF Load Capacitance, <133.3 MHz, 3.3V – 22 pF Load Capacitance, <133.3 MHz, 2.5V with High Drive – 22 pF Load Capacitance, < 133.3 MHz, 2.5V with Standard Drive – 15 pF Load Capacitance, >133.3 MHz, 3.3V – 15 pF Load Capacitance, >133.3 MHz, 2.5V with High Drive – 15 pF Input Capacitance [5] CIN – 5 pF Closed -loop bandwidth (typical), 3.3V BW 1 MHz Closed -loop bandwidth ( typical), 2.5V 0.5 MHz Output Impedance (typical), 3.3V High Drive ROUT 23 Ω Output Impedance (typical), 3.3V Standard Drive 33 Ω Output Impedance (typical), 2.5V High Drive 26 Ω Output Impedance (typical), 2.5V Standard Drive 39 Ω Power -up time for all V DD ’s to reach minimum specified vol tage (power ramps must be monotoni c) tPU 0.01 250 ms Notes: 4. Applies to Test Circuit #1. 5. Applies to both REF Clock and internal feedback path on CLKOUT. 6. Theta Ja, EIA JEDEC 51 test board conditions, 2S2P; Theta Jc Mil -Spec 883E Method 1012.1.

(Preliminary ) PL123E -09 Low Skew Zero Delay Buffer Micrel Inc. • 2180 Fortune Drive • San Jose, CA 95131 • USA • tel +1(408) 944 -0800 • fax +1(408) 474 -1000 • www.micrel.com Rev 12 /13 /11 Page 5 3.3V DC ELECTRICAL SPECIFICATIONS Descri ption Parameter Test Conditions Min Max Unit Supply Voltage VDD 2.97 3.63 V Input LOW Voltage VIL – 0.8 V Input HIGH Voltage VIH 2.5 VDD + 0.3 V Input Leakage Current IIL 0 < V IN < V IL – ±10 µA Input HIGH Current IIH VIN = V DD – 100 µA Output LOW Voltage VOL IOL = 8 mA ( Standard Drive) IOL = 12 m A (High D rive) 0.4 0.4 V V Output HIGH Voltage VOH IOH = –8 mA (Standard Drive) IOH = –12 mA (High Drive) 2.4 2.4 V V Supply Current IDD Unloaded outputs, 66 -MHz REF – 45 mA 2.5V DC ELECTRICAL SPECIFICATIONS Description Param eter Test Conditions Min Max Unit Supply Voltage VDD 2.25 2.75 V Input LOW Voltage VIL – 0.7 V Input HIGH Voltage VIH 1.7 VDD + 0.3 V Input Leakage Current IIL 0<V IN < V IL – ±10 µA Input HIGH Current IIH VIN = V DD – 100 µA Output LOW Voltage VOL IOL = 8 mA (Standard Drive ) IOL = 12 mA (High Drive) 0.5 0.5 V Output HIGH Voltage VOH IOH = –8 mA (Standard Drive ) IOH = –12 mA (High Drive) VDD – 0.6 VDD – 0.6 – V Supply Current IDD Unloaded outputs, 66 -MHz REF – 30 mA

(Preliminary ) PL123E -09 Low Skew Zero Delay Buffer Micrel Inc. • 2180 Fortune Drive • San Jose, CA 95131 • USA • tel +1(408) 944 -0800 • fax +1(408) 474 -1000 • www.micrel.com Rev 12 /13 /11 Page 6 3.3V AND 2.5V AC ELECTRICAL SPECIFICATIONS Descri ption Parameter Test Conditions Min Typ Max Unit Maximum Fr equency [7] (Input/Output) 1/t1 3.3V High Drive 10 – 220 MHz 3.3V Standard Drive 10 – 167 MHz 2.5V High Drive 10 – 200 MHz 2.5V S tandard Drive 10 – 134 MHz Input Duty Cycle (PLL Mode only) TIDC <133.3 MHz 25 – 75 % >133.3 MHz 40 – 60 % Output Duty C ycle [8 ] t2 ÷ t 1 <133.3 MHz 47 – 53 % >133.3 MHz 45 – 55 % Rise, Fall Time (3.3V) [8 ] t3,t4 Standard Drive, CL = 30 pF, <100 MHz – 1.6 – ns Standard Drive, CL = 22 pF, <133.3 MHz – 1.6 – ns Standard Drive, CL = 15 pF, <167 MHz – 0.6 – ns High Drive, CL = 30 pF, <100 MHz – 1.2 – ns High Drive, CL = 22 pF, <133.3 MHz – 1.2 – ns High Drive, CL = 15 pF, >133.3 MHz – 0.5 – ns Rise, Fall Time (2.5V) [8 ] t3, t 4 Standard Drive, CL = 15 pF, <133.33 MHz – 1.5 – ns High Drive, CL = 30 pF, <100 MHz – 2.1 – ns High Drive, CL = 22 pF, <133.3 MHz – 1.3 – ns High Drive, CL = 15 pF, >133.3 MHz – 1.2 – ns Output to Output Skew [8 ] t5 All outputs equally loaded – – 100 ps Delay, REF Rising Edge to CLKOUT Rising Edge [8 ] t6 PLL enabled @ 3.3V –100 – 100 ps PLL enabled @2.5V –200 – 200 ps Part to Part Skew [8 ] t7 Measured at V DD /2. Any output to any output, 3.3V supply – – ±150 ps Measured at V DD /2. Any output to any output, 2.5V supply – – ±300 ps PLL Lock Time [8 ] tLOCK Stable power supply, valid clocks pr e- sented on REF and CLKOUT pins – – 1.0 ms Cycle -to-Cycle Jitter, Peak [8 , 9 ] TJCC 3.3V, >66 MHz, <15 pF – – 55 ps 3.3V, >66 MHz, <30 pF, Standard. Drive – – 125 ps 3.3V, >66 MHz, <30 pF, High Drive – – 100 ps 2.5V, >66 MHz, <15 pF, Standard. Drive – – 95 ps 2.5V, >66 MHz, <15 pF, High Drive – – 65 ps 2.5V, >66 MHz, <30 pF, High Drive – – 145 ps

(Preliminary ) PL123E -09 Low Skew Zero Delay Buffer Micrel Inc. • 2180 Fortune Drive • San Jose, CA 95131 • USA • tel +1(408) 944 -0800 • fax +1(408) 474 -1000 • www.micrel.com Rev 12 /13 /11 Page 7 3.3V AND 2.5V AC ELECTRICAL SPECIFICATIONS (continued) Descri ption Parameter Test Conditions Min Typ Max Unit Period Ji tter, Peak [8 ,9] TPER 3.3V, 66 –100 MHz, <15 pF – – 75 ps 3.3V, >100 MHz, <15 pF – – 45 ps 3.3V, >66 MHz, <30 pF, Standard Drive – – 100 ps 3.3V, >66 MHz, <30 pF, High Drive – – 70 ps 2.5V, >66 MHz, <15 pF, Standard. Drive – – 60 ps 2.5V, 66 –100 MHz, <15 pF, High Drive – – 60 ps 2.5V, >100 MHz, <15 pF, High Drive – – 45 ps Notes: 7. For the given maximum loading conditions. See C L in Operating Conditions Table. 8. Parameter is guaranteed by design and characterization. Not 100% tested in production. 9. Typical j itter is measured at 3.3V or 2.5V, 29 °C, with all outputs driven into the maximum spec ified load.

(Preliminary ) PL123E -09 Low Skew Zero Delay Buffer Micrel Inc. • 2180 Fortune Drive • San Jose, CA 95131 • USA • tel +1(408) 944 -0800 • fax +1(408) 474 -1000 • www.micrel.com Rev 12 /13 /11 Page 8 SWITCHING WAVEFO RMS VDD/2 VDD/2 t3 t4 VDD/2 INPUT CLKOUT VDD/2 VDD/2 OUTPUT OUTPUT VDD/2 VDD/2 Any Output, Part 1 or 2 VDD/2 Duty Cycle Ti ming All Outputs Rise/Fall Time Output -Output Skew Input -Output Propagation Delay Device -Device Skew OUTPUT 0.8V(0.6V) Any Output, Part 1 or 2 0.8V(0.6V) 2.0V(1.8V)

(Preliminary ) PL123E -09 Low Skew Zero Delay Buffer Micrel Inc. • 2180 Fortune Drive • San Jose, CA 95131 • USA • tel +1(408) 944 -0800 • fax +1(408) 474 -1000 • www.micrel.com Rev 12 /13 /11 Page 9 TEST CIRCUITS PACKAGE DRAWINGS ( GREEN PACKAGE COMPLIANT) VDD VDD GND GND OUTPUTS CL OAD CLK 0.1 F 0.1 F Test Circuit #1 C L A

16 PIN Narrow SOP, TSSOP ( mm )

Symbol Min. Max. Min. Max. A 1.35 1.75 - 1.20 A1 0.10 0.25 0.05 0.15 B 0.33 0.51 0.19 0.30 C 0.19 0.25 0.09 0.20 D 9.80 10.00 4.90 5.10 E 3.80 4.00 4.30 4.50 H 5.80 6.20 6.40 BSC L 0.40 1.27 0.45 0.75 e 1.27 BSC 0.65 BSC E H D e B

(Preliminary ) PL123E -09 Low Skew Zero Delay Buffer Micrel Inc. • 2180 Fortune Drive • San Jose, CA 95131 • USA • tel +1(408) 944 -0800 • fax +1(408) 474 -1000 • www.micrel.com Rev 12 /13 /11 Page 10

ORDERING INFORMATION

Micrel Inc., reserves the right to make changes in its products or specifications, o r both at any time without notice. The information furnished by Micrel is believed to be accurate and reliable. However, Micrel makes no guarantee or warranty concerning the accuracy of said info rmation and shall not be responsible for any loss or damage of whatever nature resulting from the use of, or reliance upon this product. LIFE SUPPORT POLICY : Micrel’s products are not authorized for use as critical components in life support devices or systems without the express written approval of the President o f Micrel Inc. For part ordering, please contact our Sales Depa rtment:

2180 Fortune Drive , San Jose, CA 95131 , USA

Tel: (408) 944 -0800 Fax: (408) 474 -1000 PART NUMBER The order number for this device is a combination of the following: Device number, Package type and Operating temperature range PL123E-09(H) X X - X Part Number H=High Drive None = Standard Drive Package Type O=TSSOP S=SOP None=Tubes R=Tape & Reel Temperature Range C=Commercial (0°C to 70°C) I=Industrial (-40°C to 85°C) Part/Order Nu mber Marking Package Option PL123E -09 OC P123E09 OC LLLLL 16-Pin TSSOP Tube PL123E -09 OC-R 16-Pin TSSOP (Tape and Reel) PL123E -09HOC P123E09H OC LLLLL 16-Pin TSSOP Tube PL123E -09HOC -R 16-Pin TSSOP (Tape and Reel) PL123E -09 SC P123E09 SC LLLLL 16-Pin SOP Tube PL123E -09 SC-R 16-Pin SOP (Tape and Reel) PL123E -09HSC P123E09H SC LLLLL 16-Pin SOP Tube PL123E -09HSC -R 16-Pin SOP (Tape and Reel) PL123E -09 OI P123E09 OI LLLLL 16-Pin TSSOP Tube PL123E -09 OI-R 16-Pin TSSOP (Tape and R eel) PL123E -09HOI P123E09H OI LLLLL 16-Pin TSSOP Tube PL123E -09HOI -R 16-Pin TSSOP (Tape and Reel) PL123E -09 SI P123E09 SI LLLLL 16-Pin SOP Tube PL123E -09 SI-R 16-Pin SOP (Tape and Reel) PL123E -09HSI P123E09H SI LLLLL 16-Pin SOP Tube PL123E -09HSI -R 16-Pin SOP (Tape and Reel) *Note: LLL LL designates lot number