PL123E-05HSC

PL123E-05SC MICREL | Alldatasheet

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Technical content

(Preliminary )PL123 E-05 Low Skew Zero Delay Buffer Micrel Inc. • 2180 Fortune Drive • San Jose, CA 95131 • USA • tel +1(408) 944 -0800 • fax +1(408) 474 -1000 • www.micrel.com Rev 12 /13 /11 Page 1

FEATURES

 Frequency R ange 10MHz to 220MHz  Zero input - output delay.  Low output -to-output s kew .  Optional Drive Strength: Standard (8mA) PL123E -05 High (12mA) PL123E -05H  2.5V or 3.3V , ±10% operation.  Available in 8 -pin SOP packaging .

DESCRIPTION

The PL123 E-05 (-05H for High Drive) is a high pe rfor- mance, low skew, low jitter zero delay buffer d esigned to distribute high speed clocks . It has five low -skew outputs that are synchronized with the input. The sy n- chronization is esta blished via CLKOUT feed back t o the input of the PLL. Since the skew between the input and ou tput is less than 100 ps, the device acts as a zero d elay buffer. The input output propagation delay can be advanced or delayed by a djusting the load on the CLKOUT pin. These parts are not int ended for 5V input -tolerant a p- plications. PIN CO NFIGURATION SOP-8L BLOCK DIAGRAM REF CLK2 CLK1 GND CLKOUT CLK4 VDD CLK3 PLLREF CLKOUT CLK1 CLK2 CLK3 CLK4

(Preliminary )PL123 E-05 Low Skew Zero Delay Buffer Micrel Inc. • 2180 Fortune Drive • San Jose, CA 95131 • USA • tel +1(408) 944 -0800 • fax +1(408) 474 -1000 • www.micrel.com Rev 12 /13 /11 Page 2 PIN DESCRIPTION Name Package Type Type Description SOP-8L REF[1 ] 1 I Input reference fr equency. CLK2 [2 ] 2 O Buffered clock output. CLK1 [2 ] 3 O Buffered clock output. GND 4 P Ground connection . CLK3 [2 ] 5 O Buffered clock output. VDD 6 P VDD connection. CLK4 [2 ] 7 O Buffered clock output. CLKOUT [2 ,3 ] 8 O Buffered clock output. Inte rnal feed back on this pin. Notes: 1: Weak pull -down. 2: Weak pull -down on a ll outputs. 3. This output is driven and has an internal feedback for the PLL. The load on this output can be adjusted to change the skew b etween the reference and output. INPUT / OUTPUT SKEW CONTROL The PL 123E -05 will achieve Zero Delay from input to ou tput when all the outputs are loaded equally. Adjus t- ments to the input/output delay can be made by adjusting the loading on the CLKOUT pin. Please contact Micrel for more information.

(Preliminary )PL123 E-05 Low Skew Zero Delay Buffer Micrel Inc. • 2180 Fortune Drive • San Jose, CA 95131 • USA • tel +1(408) 944 -0800 • fax +1(408) 474 -1000 • www.micrel.com Rev 12 /13 /11 Page 3 LAYOUT RECOMMENDATIONS The following guidelines are to assist y ou with a performance optimized PCB design: Signal Integrity and Termination Consider ations - Keep traces short! - Trace = Inductor. With a capacitive load this equals ringing! - Long trace = Transmission Line. Without proper termination this will c ause reflections ( looks like ringing ). - Design long traces as “striplines” or “m icrostrips” with defined impedance. - Match trace at one side to avoid reflections boun c- ing back and forth. Decoupling and Power Supply Considerations - Place decoupling c apacitors as close as possible to the VDD pin(s) to limit noise from the power supply - Addition of a ferrite bead in series with VDD can help prevent noise from other board sources - Value of decoupling capacitor is frequency d e- pendant. Typical values to use are 0.1 F for d e- signs using frequencies < 50MHz and 0.01 F for designs using frequencies > 50MHz. Typical CMOS termination Place Series Resistor as close as possible to CMOS output CMOS Output Buffer ( Typical buffer impedance 20  To CMOS Input 50 line Connect a 33 series resistor at each of the output clocks to enhance the stability of the output signal

(Preliminary )PL123 E-05 Low Skew Zero Delay Buffer Micrel Inc. • 2180 Fortune Drive • San Jose, CA 95131 • USA • tel +1(408) 944 -0800 • fax +1(408) 474 -1000 • www.micrel.com Rev 12 /13 /11 Page 4 Absolute Maximum Conditions Static Discharge Voltage (per MIL -STD -883, Method 3015)………… ……> 2000V Operating Condition Description Param eter Min Max Unit Supply Voltage VDD 2.25 3.63 V Load Capacitance, <100 MHz, 3.3V CL [4] – 30 pF Load Capacitance, <100 MHz, 2.5V with High Drive – 30 pF Load Capacitance, <133.3 MHz, 3.3V – 22 pF Load Capacitance, <133.3 MHz, 2.5V with High Drive – 22 pF Load Capacitance, <133.3 MHz, 2.5V with Standard Drive – 15 pF Load Capacitan ce, >133.3 MHz, 3.3V – 15 pF Load Capacitance, >133.3 MHz, 2.5V with High Drive – 15 pF Input Capacitance [5] CIN – 5 pF Closed -loop bandwidth (typical), 3.3V BW 1 MHz Closed -loop bandwidth (typical), 2.5V 0.5 MHz Output Impedance (typical), 3.3V Hi gh Drive ROUT 23 Ω Output Impedance (typical), 3.3V Standard Drive 33 Ω Output Impedance (typical), 2.5V High Drive 26 Ω Output Impedance (typical), 2.5V Standard Drive 39 Ω Power -up time for all V DD ’s to reach minimum specified vol tage (power ramps must be monotoni c) tPU 0.01 250 ms Notes: 4. Applies to Test Circuit #1. 5. Applies to both REF Clock and internal feedback path on CLKOUT. 6. Theta Ja, EIA JEDEC 51 test board conditions, 2S2P; Theta Jc Mil -Spec 883E Method 1012.1.

(Preliminary )PL123 E-05 Low Skew Zero Delay Buffer Micrel Inc. • 2180 Fortune Drive • San Jose, CA 95131 • USA • tel +1(408) 944 -0800 • fax +1(408) 474 -1000 • www.micrel.com Rev 12 /13 /11 Page 5 3.3V DC Electrical Specifications Descript ion Parameter Test Conditions Min Max Unit Supply Voltage VDD 2.97 3.63 V Input LOW Voltage VIL – 0.8 V Input HIGH Voltage VIH 2.5 VDD + 0.3 V Input Leakage Current IIL 0 < V IN < V IL – ±10 µA Input HIGH Current IIH VIN = V DD – 100 µA Output LOW Vo ltage VOL IOL = 8 mA ( Standard Drive) IOL = 12 m A (High D rive) 0.4 0.4 V V Output HIGH Voltage VOH IOH = –8 mA (Standard Drive) IOH = –12 mA (High Drive) 2.4 2.4 V V Supply Current IDD Unloaded outputs, 66 -MHz REF – 45 mA 2.5V DC Electrical Sp ecifications Description Param eter Test Conditions Min Max Unit Supply Voltage VDD 2.25 2.75 V Input LOW Voltage VIL – 0.7 V Input HIGH Voltage VIH 1.7 VDD + 0.3 V Input Leakage Current IIL 0<V IN < V DD – 10 µA Input HIGH Current IIH VIN = V DD – 100 µA Output LOW Voltage VOL IOL = 8 mA (Standard Drive ) IOL = 12 mA (High Drive) 0.5 0.5 V Output HIGH Voltage VOH IOH = –8 mA (Standard Drive ) IOH = –12 mA (High Drive) VDD – 0.6 VDD – 0.6 – V Supply Current IDD Unloaded outputs, 66 -MHz REF – 30 mA

(Preliminary )PL123 E-05 Low Skew Zero Delay Buffer Micrel Inc. • 2180 Fortune Drive • San Jose, CA 95131 • USA • tel +1(408) 944 -0800 • fax +1(408) 474 -1000 • www.micrel.com Rev 12 /13 /11 Page 6 3.3V and 2.5V AC Electrical Specifications Descri ption Parameter Test Conditions Min Typ Max Unit Maximum Fr equency [7] (Input/Output) 1/t1 3.3V High Drive 10 – 220 MHz 3.3V Standard Drive 10 – 167 MHz 2.5V High Drive 10 – 200 MHz 2.5V Standa rd Drive 10 – 134 MHz Input Duty Cycle (PLL Mode only) TIDC <133.3 MHz 25 – 75 % >133.3 MHz 40 – 60 % Output Duty C ycle [8 ] t2 ÷ t 1 <133.3 MHz 47 – 53 % >133.3 MHz 45 – 55 % Rise, Fall Time (3.3V) [8 ] t3,t4 Standard Drive, CL = 30 pF, <100 MHz – 1.6 – ns Standard Drive, CL = 22 pF, <133.3 MHz – 1.6 – ns Standard Drive, CL = 15pF, <167 MHz – 0.6 – ns High Drive, CL = 30 pF, <100 MHz – 1.2 – ns High Drive, CL = 22 pF, <133.3 MHz – 1.2 – ns High Drive, CL = 15 pF, >133.3 MHz – 0.5 – ns Rise, Fall Time (2.5V) [8 ] t3, t 4 Standard Drive, CL = 15 pF, <133.33 MHz – 1.5 – ns High Drive, CL = 30 pF, <100 MHz – 2.1 – ns High Drive, CL = 22 pF, <133.3 MHz – 1.3 – ns High Drive, CL = 15 pF, >133.3 MHz – 1.2 – ns Output to Output Skew [8 ] t5 All out puts equally loaded – – 100 ps Delay, REF Rising Edge to CLKOUT Rising Edge [8 ] t6 PLL enabled @ 3.3V –100 – 100 ps PLL enabled @2.5V –200 – 200 ps Part to Part Skew [8] t7 Measured at V DD /2. Any output to any output, 3.3V supply – – ±150 ps Measured at V DD /2. Any output to any output, 2.5V supply – – ±300 ps PLL Lock Time [8 ] tLOCK Stable power supply, valid clocks pr e- sented on REF and CLKOUT pins – – 1.0 ms Cycle -to-Cycle Jitter, Peak [8 ,9 ] TJCC 3.3V, >66 MHz, <15 pF – – 55 ps 3.3V, >66 MHz, <30 pF, Standard. Drive – – 125 ps 3.3V, >66 MHz, <30 pF, High Drive – – 100 ps 2.5V, >66 MHz, <15 pF, Standard. Drive – – 100 ps 2.5V, >66 MHz, <15 pF, High Drive – – 80 ps 2.5V, >66 MHz, <30 pF, High Drive – – 125 ps

(Preliminary )PL123 E-05 Low Skew Zero Delay Buffer Micrel Inc. • 2180 Fortune Drive • San Jose, CA 95131 • USA • tel +1(408) 944 -0800 • fax +1(408) 474 -1000 • www.micrel.com Rev 12 /13 /11 Page 7 3.3V and 2.5V AC Electrical Speci fications (continued) Descri ption Parameter Test Conditions Min Typ Max Unit Period Jitter, Peak [8 ,9 ] TPER 3.3V, 66 –100 MHz, <15 pF – – 60 ps 3.3V, >100 MHz, <15 pF – – 35 ps 3.3V, >66 MHz, <30 pF, Standard Drive – – 75 ps 3.3V, >66 MHz, <30 pF, High Drive – – 70 ps 2.5V, >66 MHz, <15 pF, Standard. Drive – – 60 ps 2.5V, 66 –100 MHz, <15 pF, High Drive – – 60 ps 2.5V, >100 MHz, <15 pF, High Drive – – 45 ps Notes: 7. For the given maximum loading conditions. See C L in Operating Conditions Tab le. 8. Parameter is guaranteed by design and characterization. Not 100% tested in production. 9. Typical j itter is measured at 3.3V or 2.5V, 29 °C, with all outputs driven into the maximum spec ified load.

(Preliminary )PL123 E-05 Low Skew Zero Delay Buffer Micrel Inc. • 2180 Fortune Drive • San Jose, CA 95131 • USA • tel +1(408) 944 -0800 • fax +1(408) 474 -1000 • www.micrel.com Rev 12 /13 /11 Page 8 SWITCHING WAVEFORMS VDD/2 VDD/2 t3 t4 VDD/2 INPUT CLKOUT VDD/2 VDD/2 OUTPUT OUTPUT VDD/2 VDD/2 Any Output, Part 1 or 2 VDD/2 Duty Cycle Ti ming All Outputs Rise/Fall Time Output -Output Skew Input -Output Propagation Delay Device -Device Skew OUTPUT 0.8V(0.6V) Any Output, Part 1 or 2 0.8V(0.6V) 2.0V(1.8V)

(Preliminary )PL123 E-05 Low Skew Zero Delay Buffer Micrel Inc. • 2180 Fortune Drive • San Jose, CA 95131 • USA • tel +1(408) 944 -0800 • fax +1(408) 474 -1000 • www.micrel.com Rev 12 /13 /11 Page 9 TEST CIRCUITS PACKAGE DRAWINGS ( GREEN PACKAGE COMPLIANT) Recommended Land Pattern (MM) 2.31 ±0.05

2.40 REF

6.985 ±0.050 Min Max A 1.35 1.75 A1 0.10 0.25 A2 1.25 1.50 b 0.33 0.53 C 0.19 0.27 D 4.80 5.00 E 3.80 4.00 H 5.80 6.20 L 0.40 0.89 e Symbol Dimension (MM)

1.27 BSC

L C e b A

3.80 REF

4.65 REF

1.27 Nom 0.53 ±0.05 VDD VDD GND GND OUTPUTS CL OAD CLK 0.1 F 0.1 F Test Circuit #1

(Preliminary )PL123 E-05 Low Skew Zero Delay Buffer Micrel Inc. • 2180 Fortune Drive • San Jose, CA 95131 • USA • tel +1(408) 944 -0800 • fax +1(408) 474 -1000 • www.micrel.com Rev 12 /13 /11 Page 10 ORDERING INFORMATION (GREEN PACKAGE COMPLIANT) Micrel Inc., reserves the right to make changes in its products or specif ications, or both at any time without notice. The information furnished by Micrel is believed to be accurate and reliable. However, Micrel makes no guarantee or warranty concerning the accuracy of said info rmation and shall not be responsible for any loss or damage of whatever nature resulting from the use of, or reliance upon this product. LIFE SUPPORT POLICY : Micrel’s products are not authorized for use as critical components in life support devices or systems without the express written approval of the President of Micrel Inc. For part ordering, please co ntact our Sales Department:

2180 Fortune Drive , San Jose, CA 95131 , USA

Tel: (408) 944 -0800 Fax: (408) 474 -1000 PART NUMBER The order number for this device is a combination of the following: Part number, Package type and Operating temperature range PL123E-05(H) S X - X Part Number H=High Drive None = Standard Drive Package Type S=SOP None=Tubes R=Tape & Reel Temperature Range C=Commercial (0°C to 70°C) I=Industrial (-40°C to 85°C) Part/Order Nu mber Marking * Package Option PL123E -05SC P123E05 SC LLLLL 8-Pin SOP Tube PL123E -05SC-R 8-Pin SOP (Tape and Reel) PL123E -05HSC P123E05H SC LLLLL 8-Pin SOP Tube PL123E -05HSC -R 8-Pin SOP (Tape and Reel) PL123E -05SI P123E05 SI LLLLL 8-Pin SOP Tube PL123E -05SI-R 8-Pin SOP (Tape and Reel) PL123E -05HSI P123E05H SI LLLLL 8-Pin SOP Tube PL123E -05HSI -R 8-Pin SOP (Tape and Reel) *Note: LLL LL designates lot number