PL123-05

PL123-05 MICREL | Alldatasheet

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Technical content

Low Skew Zero Delay Buffer Micrel Inc. • 2180 Fortune Drive • San Jose, CA 95131 • USA • tel +1(408) 944 -0800 • fax +1(408) 474 -1000 • www.micrel.com Rev 4/22/1 3 Page 1

FEATURES

 Frequency R ange 10MHz to 134 MHz  Output Options: o 5 outputs PL123 -05 o 9 outputs PL123 -09  Zero input - output delay  Optional Drive Strength: Standard (8mA) PL123 -05/ -09 High (12mA) PL123 -05H/ -09H  3.3V , ±10% operation  Available in Commercial and Indu strial temperature ranges  Available in 16 -Pin SOP or TSSOP (PL123 -09), and 8 -Pin SOP (PL123 -05) packages

DESCRIPTION

The PL123 -05/ -09 (-05H/ -09H for High Drive) are high performance, low skew, low jitter zero delay buffer s designed to distri bute high spee d clocks . They have one (PL123 -05) or two (PL123 -09) low -skew output banks , of 4 outputs each , that a re synchronized with the input. The PL123 -09 allows c ontrol of the banks of outputs by using the S1 and S2 inputs as shown in the Selector Defin ition tab le on page 2. The synchronization is esta blished via CLKOUT feed back to the input of the PLL. Since the skew between the input and ou tput is less than 100 ps, the device acts as a zero delay buffer. The input output propag a- tion delay can be advanced or d elayed by adjusting the load on the CLKOUT pin. These parts are not intended for 5V input -tolerant a p- plications. BLOCK DIAGRAM PLLREF CLKOUT CLKA1 CLKA2 CLKA3 CLKA4 Mux CLKB1 CLKB2 CLKB3 CLKB4 1REF CLKA1 CLKA2 VDD CLKOUT CLKA4 CLKA3 VDD PL123-09 GND CLKB4 CLKB3 CLKB2 CLKB1 GND Bank B Bank A Selector Inputs (PL123-09 Only) REF CLKA2 CLKA1 GND CLKOUT CLKA4 VDD CLKA3 PL123-05

Low Skew Zero Delay Buffer Micrel Inc. • 2180 Fortune Drive • San Jose, CA 95131 • USA • tel +1(408) 944 -0800 • fax +1(408) 474 -1000 • www.micrel.com Rev 4/22/13 Page 2 PIN DESCRIPTIONS Name PL123 -09 PL123 -05 Type Description TSSOP -16L SOP -16L SOP -8L REF [1] 1 1 1 I Input reference fr equency. CLK A1[2] 2 2 3 O Buffered clock ou tput, Bank A CLK A2[2] 3 3 2 O Buffered clock ou tput, Bank A VDD 4,13 4,13 6 P VDD connection GND 5,12 5,12 4 P GND connection CLK B1[2] 6 6 - O Buffered clock ou tput, Bank B CLK B2[2] 7 7 - O Buffered clock o utput, Bank B S2[3] 8 8 - I Selector input S1[3] 9 9 - I Selector input CLK B3[2] 10 10 - O Buffered clock ou tput, Bank B CLK B4[2] 11 11 - O Buffered clock ou tput, Bank B CLK A3[2] 14 14 5 O Buffered clock ou tput, Bank A CLK A4[2] 15 15 7 O Buffered clo ck ou tput, Bank A CLKOUT [2] 16 16 8 O Buffered clock output. Internal fee dback on this pin. Notes: 1: Weak pull -down. 2: Weak pull -down on all outputs. 3: Weak Pull -Up on S1 and S2 SELECTOR DEFINITION FOR PL123 -09 S2 S1 CLOCK A1–A4 (Bank A) CLOCK B1–B4 (Bank B) CLKOU T Output Source PLL Shu tdown 0 0 Three -state Three -state Driven PLL N 0 1 Driven Three -state Driven PLL N 1 0 Driven Driven Driven Reference Y 1 1 Driven Driven Driven PLL N INPUT / OUTPUT SKEW CO NTROL The PL 123 -05/ -09 will achieve Zero Delay from input to output when all the outputs are loaded equally . Adjus t- ments to the i nput/output delay can be made by adding additional loading to the CLKOUT pin. Please contact Micrel for more inform ation.

Low Skew Zero Delay Buffer Micrel Inc. • 2180 Fortune Drive • San Jose, CA 95131 • USA • tel +1(408) 944 -0800 • fax +1(408) 474 -1000 • www.micrel.com Rev 4/22/13 Page 3 LAYOUT RECOMMENDATIONS The following gu idelines are to assist you with a pe rformance optimized PCB design: Signal Integrity and Termination Consider ations - Keep traces short! - Trace = Inductor. With a capacitive load this equals ringing! - Long trace = Transmission Line. Without proper term i- nation this will cause reflections ( looks like rin ging ). - Design long traces as “striplines” or “m icrostrips” with defined impedance. - Match trace at one side to avoid reflections bounc ing back and forth. Decoupling and Power Supply Considerati ons - Place decoupling capacitors as close as possible to the VDD pin(s) to limit noise from the power supply - Addition of a ferrite bead in series with VDD can help prevent noise from other board sources - Value of decoupling capacitor is frequency d e- pen dant. Typical values to use are 0.1 F for d e- signs using frequencies < 50MHz and 0.01 F for designs using frequencies > 50MHz. Typical CMOS termination Place Series Resistor as close as possible to CMOS output CMOS Output Buffer ( Typical buffer impedance 20  To CMOS Input Connect a 33 series resistor at each of the output clocks to enhance the stability of the output signal 50 line

Low Skew Zero Delay Buffer Micrel Inc. • 2180 Fortune Drive • San Jose, CA 95131 • USA • tel +1(408) 944 -0800 • fax +1(408) 474 -1000 • www.micrel.com Rev 4/22/13 Page 4 ABSOLUTE MAXIMUM COND ITIONS Static Discharge Voltage (per MIL -STD -883, Method 3015)………… ..> 2000V OPERATING CONDITIONS Parameter Description Min. Max. Unit VDD Supply Voltage 3.0 3.6 V TA Commercial Operating Temperatur e (ambient te mperature) 0 70 C Industrial Operating Temperature (ambient te mperature) -40 85 C CL Load Capacitance, below 100 MHz ― 30 pF Load Capacitance, above 100 MHz ― 10 pF CIN Input Capacitance ― 7 pF tPU Power -up time for all V DD s to reach minimum specified voltage (power ramps must be monotonic) 0.05 250 ms ELECTRICAL CHARACTERI STICS Parameter Description Test Conditio ns Min. Max. Unit VIL Input LOW Voltage – 0.8 V VIH Input HIGH Voltage 2.5 – V IIL Input LOW Current VIN = 0V – 50 µA IIH Input HIGH Current VIN = VDD – 100 µA VOL Output LOW Voltage[4] IOL = 8 mA IOL = 12 mA – 0.4 V VOH Output HIGH Voltage[4] IOH = –8 mA IOL = –12 mA 2.4 – V IDD Supply Current (Unloaded Outputs) 66.67MHz with unloaded outputs Commercial Temp. – 32 mA 66.67MHz with unloaded outputs Industrial Temp. – 45 mA Notes: 4. Parameter is guaranteed by design and c haracterization. Not 100% tested in produ ction .

Low Skew Zero Delay Buffer Micrel Inc. • 2180 Fortune Drive • San Jose, CA 95131 • USA • tel +1(408) 944 -0800 • fax +1(408) 474 -1000 • www.micrel.com Rev 4/22/13 Page 5 SWITCHING CHARACTERISTICS [5] Parameter Name Test Conditions Min. Typ. Max. Unit t1 Output Frequency 30-pF load 10 – 100 MHz 10-pF load 10 – 134 MHz Duty Cycle [4] = t2 ÷ t1 Measured at 1.4V, FOUT = 66.67MHz 40 50 60 % Duty Cycle [4] = t2 ÷ t1 Measured at 1.4V, FOUT <50MHz 45 50 55 % Rise Time [4] Measured between 0.8V and 2.0V – – 2.5 ns Rise Time [4] (High Drive) Measured between 0.8V and 2.0V – – 1.5 ns Fall Time [4] Measured between 0.8V and 2.0V – – 2.5 ns Fall Time [4] (High Drive) Measured between 0.8V and 2.0V – – 1.5 ns t5 Output to Output Skew All outputs equally loaded – – 250 ps t6A Delay, REF Rising Edge to CLKOUT Rising Edge [4] Measured at VDD/2 – 0 ±350 ps t6B Delay, REF Rising Edge to CLKOUT Rising Edge [4] Measured at VDD/2. Measured in PLL bypass mode, PL123-09 only. 1 5 8.5 ns t7 Device to Device Skew [4] Measured at VDD/2 on the CLKOUT pin – 0 700 ps t8 Output Slew Rate [4] Measured between 0.8V and 2.0V using Test Circuit #2 1 – – V/ns tJ Cycle to Cycle Jitter [4] Measured at 66.67 MHz, loaded outputs – 75 200 ps tLOCK PLL Lock Time [4] Stable power supply, valid clock presented on REF pin – – 1 ms Notes: 4. Parameter is guar anteed by design and cha racterization. Not 100% tested in production . 5. All parameters are specified with loaded ou tputs .

Low Skew Zero Delay Buffer Micrel Inc. • 2180 Fortune Drive • San Jose, CA 95131 • USA • tel +1(408) 944 -0800 • fax +1(408) 474 -1000 • www.micrel.com Rev 4/22/13 Page 6 SWITCHING WAVEFORMS 1.4V 1.4V VDD/2 INPUT OUTPUT VDD/2 1.4V OUTPUT OUTPUT 1.4V Duty Cycle Ti ming All Outputs Rise/Fall Time Output -Output Skew Input -Output Propagation D elay t3 t4 OUTPUT 0.8V 2.0V 3.3V V 0.8V 2.0V VDD/2 CLKOUT, D evice 1 CLKOUT, D evice 2 VDD/2 Device -Device Skew

Low Skew Zero Delay Buffer Micrel Inc. • 2180 Fortune Drive • San Jose, CA 95131 • USA • tel +1(408) 944 -0800 • fax +1(408) 474 -1000 • www.micrel.com Rev 4/22/13 Page 7 TEST CIRCUITS VDD VDD GND GND OUTPUTS CLOAD CLK 0.1 F 0.1 F Test Circuit #1 VDD VDD GND GND OUTPUTS 0.1 F 0.1 F Test Circuit # 2 10 pF 1KΩ 1KΩ

Low Skew Zero Delay Buffer Micrel Inc. • 2180 Fortune Drive • San Jose, CA 95131 • USA • tel +1(408) 944 -0800 • fax +1(408) 474 -1000 • www.micrel.com Rev 4/22/13 Page 8 PACKAGE DRAWINGS ( GREEN PACKAGE COMPL IANT) SOP 8L Symbol Dimension in MM Min. Max. A 1.35 1.75 A1 0.10 0.25 A2 1.25 1.50 B 0.33 0.53 C 0.19 0.27 D 4.80 5.00 E 3.80 4.00 H 5.80 6.20 L 0.40 0.89 e 1.27 BSC C L A SOP-16L and TSSOP-16L ( mm ) SOP TSSOP Symbol Min. Max. Min. Max. A 1.35 1.75 - 1.20 A1 0.10 0.25 0.05 0.15 B 0.33 0.51 0.19 0.30 C 0.19 0.25 0.09 0.20 D 9.80 10.00 4.90 5.10 E 3.80 4.00 4.30 4.50 H 5.80 6.20 6.40 BSC L 0.40 1.27 0.45 0.75 e 1.27 BSC 0.65 BSC E H D e B C L E H D e B A

Low Skew Zero Delay Buffer Micrel Inc. • 2180 Fortune Drive • San Jose, CA 95131 • USA • tel +1(408) 944 -0800 • fax +1(408) 474 -1000 • www.micrel.com Rev 4/22/13 Page 9

ORDERING INFORMATION

Micrel Inc., reserves the right to make changes in its products or specifications, or both at any time without notice. The information furnished by Mic rel is believed to be accurate and reliable. However, Micrel makes no guarantee or warranty concerning the accuracy of said info rm ation and shall not be responsible for any loss or damage of whatever nature resulting from the use of, or reliance upon this product. LIFE SUPPORT POLICY : Micrel’s products are not authorized for use as critical components in life support devices or syste ms without the express written approval of the President of Micrel Inc. For part ordering, please contact our Sales Department:

2180 Fortune Drive , San Jose, CA 95131 , USA

Tel: (408) 944 -0800 Fax: (408) 474 -1000 PART NUMBER The order number for this device is a combinati on of the following: Part number, Package type and Operating temperature range PL123-0x(H) X X - X Part Number H=High Drive None = Standard Drive Package Type O=TSSOP S=SOP None=Tubes R=Tape & Reel Temperature Range C=Commercial (0°C to 70°C) I=Industrial (-40°C to 85°C) Part/Order Nu mber (Commercial) Mar king* (Commercial) Part/Order Nu mber (Industrial) Mar king* (Industrial) Package O ption PL123 -05SC P12305 SC LLLLL PL123 -05SI P12305 SI LLLLL 8-Pin SOP Tube PL123 -05SC -R PL123 -05SI -R 8-Pin SOP (Tape and Reel) PL123 -05HSC P12305H SC LLLLL PL123 -05HSI P12305H SI LLLLL 8-Pin SOP Tube PL123 -05HSC -R PL123 -05HSI -R 8-Pin SOP (Tape and Reel) PL123 -09OC P12309 OC LLLLL PL123 -09OI P12309 OI LLLLL 16-Pin TSSOP Tube PL123 -09OC -R PL123 -09OI -R 16-Pin TSSOP (Tape and Reel) PL123 -09HOC P123 09H OC LLLLL PL123 -09HOI P123 09H OI LLLLL 16-Pin TSSOP Tube PL123 -09HOC -R PL123 -09HOI -R 16-Pin TSSOP (Tape and Reel) PL123 -09SC P123 09 SC LLLLL PL123 -09SI P123 09 SI LLLLL 16-Pin SOP Tube PL123 -09SC-R PL123 -09SI-R 16-Pin SOP (Tape and Reel) PL123 -09HSC P123 09H SC LLLLL PL123 -09HSI P123 09H SI LLLLL 16-Pin SOP Tube PL123 -09HSC -R PL123 -09HSI -R 16-Pin SOP (Tape and Reel) *Note : LLL LL designates lot number