PKS604P

PKS603P FERYSTER | Alldatasheet

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Technical content

D S AC IN DC OUT Optional Smart AC Sense PeakSwitch PI-3995-051006 D S EN/UV BP Figure 1. Typical Peak Power Application.

• Standby output power ≥0.6 W for 1 W input (high line)
• Sleep mode power ≥2.4 W at 3 W input (high line)
• No-load consumption <200 mW at 265 V AC input
• Surpasses California Energy Commission (CEC), ENERGY STAR, and EU requirements PeakSwitch Features Reduce System Cost
• Delivers peak power of up to three times maximum continuous output power
• 277 kHz operation during peak power significantly reduces transformer size
• Programmable smart AC line sensing provides latching shutdown during short circuit, overload and open loop faults, and prevents glitches during power down or brownout
• Two external components reset latch on AC removal
• Adaptive switching cycle on-time extension increases low line peak output power, minimizing bulk capacitor size
• Adaptive current limit reduces output overload power
• Frequency jittering reduces EMI filter cost
• Tight I 2f tolerances and negligible temperature variation of key parameters ease design and lower cost
• Accurate hysteretic thermal shutdown with automatic recovery provides complete system level overload protection and eliminates need for manual reset Better System Cost/Performance over RCC & Discrete
• Simple ON/OFF control – no loop compensation needed
• Very low component count – higher reliability and single side printed circuit board
• High bandwidth provides fast turn on with no overshoot and excellent transient load response
• Peak current limit operation rejects line frequency ripple
• Built-in current limit and hysteretic thermal protection

Applications

• Inkjet printer
• Data storage, audio amplifier, DC motor drives

Description

PeakSwitch is designed to address applications with high peak- to-continuous power ratio demands. The very high switching frequency during peak power loads and excellent load transient response reduce system cost as well as component count and size. PeakSwitch incorporates a 700 V power MOSFET, oscillator, high voltage switched current source for startup, current limit, February 2007 Table 1. Notes: 1. Typical continuous power in a non-ventilated enclosed adapter measured at +50 °C ambient. 2. Typical peak power for a period of 100 ms and a duty cycle of 10% in a non-ventilated enclosed adapter measured at +50 °C (see Key Applications section for details). 3. See Part Ordering Information. and thermal shutdown onto a monolithic device. In addition, these devices incorporate auto-restart, line under-voltage sense and frequency jittering. An innovative design minimizes audio frequency components in the simple ON/OFF control scheme to practically eliminate audible noise with standard varnished transformer construction. OUTPUT POWER TABLE PRODUCT3

230 VAC ±15% 85-265 VAC

Cont.1 Adapter Peak2 Adapter Cont.1 Adapter Peak2 PKS603 P 13 W 32 W 9 W 25 W PKS604 P 23 W 56 W 16 W 44 W PKS604 Y/F 35 W 56 W 23 W 44 W PKS605 P 31 W 60 W 21 W 44 W PKS605 Y/F 46 W 79 W 30 W 58 W PKS606 P 35 W 66 W 25 W 46 W PKS606 Y/F 68 W 117 W 45 W 86 W PKS607 Y/F 75 W 126 W 50 W 93 W PKS603-607 PeakSwitch Family Enhanced, Energy-Efficient, Off-Line Switcher IC With Super Peak Power Performance

Figure 2. Functional Block Diagram. Figure 3. Pin Configuration. operating current for both startup and steady-state operation. this pin must be externally supplied via a bias winding.

1.0 V + VT

3 EN/UV

2 GND

7 DBP

Figure 4. Frequency Jitter. simple ON/OFF control to regulate the output voltage.

5.8 V regulator, BYPASS pin under-voltage circuit, over-

switching cycle on-time extension, and frequency jitter. indicates the beginning of each cycle. adjusts the current limit level accordingly in discrete amounts. is usually connected to this pin.

6.3 V when current is provided through an external resistor

MOSFET when the BYPASS pin voltage drops below 4.8 V . back to 5.8 V to enable (turn on) the power MOSFET. The thermal shutdown circuitry senses the die temperature. The threshold is typically set at 142 °C with 75 °C hysteresis.

Figure 7. PeakSwitch Operation at Near Maximum Loading. Figure 6. PeakSwitch Auto-Restart Operation. low). After 30 ms of no feedback, MOSFET switching is disabled. switching remains disabled until normal line voltage is restored. latching shutdown function during such a condition. of the power MOSFET until the fault condition is removed.

300 VDRAIN

extension is disabled during the startup of the power supply. Figure 8. PeakSwitch Operation at Moderately Heavy Loading.

Zener reference and opto coupler feedback. limits the peak inrush current when AC is first applied. voltage lockout function during brown-out conditions. low voltage conditions and also on removal of the AC input.

30 V @

2.7 A Peak

250 VAC

Figure 15. PeakSwitch PKS606Y, 32 W Continuous, 81 W Peak, Universal Input Power Supply.

Rev. I 02/07 off the power supply. This protects the load and supply from a continuous fault condition. Removing the AC input resets this condition. The output voltage is determined by the Zener diode VR2, the voltage drop across R12 and the forward drop of D9 and the LED of optocoupler U2. Resistor R13 provides bias current through D9 and VR2, to ensure that VR2 is operating close to its knee voltage, while R12 sets the overall gain of the feedback loop. Capacitor C15 boosts high frequency loop gain to help distribute the enabled switching cycles and reduce pulse grouping. When the output voltage exceeds the feedback threshold voltage, current will flow in the optocoupler LED, causing current flow in the transistor of the optocoupler. When this exceeds the ENABLE pin threshold current the next switching cycle is inhibited, as the output voltage falls (below the feedback threshold) a conduction cycle is allowed to occur and by adjusting the number of enabled cycles output regulation is maintained. As the load reduces the number of enabled cycles decreases, lowering the effective switching frequency and scaling switching losses with load. This provides almost constant efficiency down to very light loads, ideal for meeting energy efficiency requirements. PeakSwitch device U1 is supplied from an auxillary winding on the transformer which is rectified and filtered by D7 and C6. Resistor R7 provides approximately 2 mA of supply current into the BYPASS pin capacitor C8. During startup or fault conditions when the bias voltage is low, the BYPASS pin is supplied from a high voltage current source within U1, eliminating the need for separate startup components. Components Q1-2, R9-11, R14, C13, C16, and VR3 form an overvoltage and overcurrent protection circuit. An output overvoltage or overcurrent condition fires SCR Q2, clamping the output voltage and forcing PeakSwitch U1 into latching shutdown after 30 ms. The low pass filter formed by R10 and C13 adds a delay to the over-current sense. The shutdown condition can be reset by briefly removing AC power for ~3 seconds (maximum). The latching function within PeakSwitch significantly reduces the size of the SCR and output rectifier, D8, as the short circuit current only flows for 50 ms before the supply latches off. This design meets EN55022 Class B conducted EMI with >10 dB margin even with the output RTN directly connected to earth ground. Key Application Considerations PeakSwitch Design Considerations Output Power Table The data sheet maximum output power table (Table 1) represents the maximum practical continuous output power level that can be obtained under the following assumed conditions: 1. The minimum DC input voltage is 100 V or higher for

85 V AC input, or 220 V or higher for 230 V AC input or

single 100/115 V AC with a voltage doubler. 2. Efficiency of 70% for Y/F packaged devices, 75% for P packaged devices at 85-265 V AC, 75% for 230 V AC input all packages 3. Minimum datasheet value of I2f 4. Transformer primary inductance tolerance of ±10% 5. Reflected output voltage (VOR) of 135 V 6. Voltage only output of 15 V with an ultra fast PN rectifier diode 7. Continuous conduction mode operation with transient KP* value of 0.25 8. Sufficient heatsinking is provided, either externally (Y/F packages) or through an area of PC board copper (P package) to keep the SOURCE pin or tab temperature at or below 110 °C. 9. Device ambient temperature of 50 °C for open frame designs and 40 °C for sealed adapters *Below a value of 1, KP is the ratio of ripple to peak primary current. To prevent reduced power capability due to premature termination of switching cycles, a transient KP limit of ≥0.25 is recommended. This avoids the initial current limit (IINIT) being exceeded at MOSFET turn on. Peak vs. Continuous Power PeakSwitch devices have current limit values that allow the specified peak power values in the power table. With sufficient heatsinking, these power levels could be provided continuously, however this may not be practical in many applications. PeakSwitch is optimized for use in applications that have short duration, high peak power demand, but a significantly lower continuous or average power. Typical ratios would be PPEAK ≥ 2 × PA VE. The high switching frequency of PeakSwitch allows a small core size to be selected to deliver the peak power, but the short duration prevents the transformer winding from overheating. As average power increases, it may be necessary to select a larger transformer to allow increased copper area for the windings based on the measured transformer temperature. The power table provides some guidance between peak power and continuous power in sealed adapters, however specific applications may differ. For example, if the peak power condition is very low duty cycle, say a 2 second peak occurring only at power up to accelerate a hard disk drive, then the transformer’s thermal rise is only a function of the continuous power. However, if the peak power occurs every 200 ms for 50 ms then it would need to be considered. In all cases, the acceptable temperature rise of the PeakSwitch and transformer should be verified under worst case ambient and load conditions.

requirements for a design with two different peak load conditions. one cycle of the pulse load condtion. can generate audio frequency components in the transformer. capacitance and increased losses that result. dielectric or construction, for example a film type capacitor.

3000 Gauss at the peak current limit of the selected device,

startup or output short circuit conditions. current into the BYPASS pin once the supply is operational. (IS2) for the specific device being used. pins on the PC board is not recommended. to the BYPASS and SOURCE pins. be kept as small as possible. Zener (~200 V) and diode clamp across the primary winding. Figure 16. Continuous (Average) Output Power Calculation

Figure 17. Recommended Layout for PeakSwitch in (a) P and (b) Y/F Packages.

Rev. I 02/07 Thermal Considerations For the P package, the four SOURCE pins are internally connected to the IC lead frame and provide the main path to remove heat from the device. Therefore, all the SOURCE pins should be connected to a copper area underneath the PeakSwitch to act not only as a single point ground, but also as a heatsink. As this area is connected to the quiet source node, it should be maximized for good heatsinking. Similarly, for axial output diodes, maximize the PCB area connected to the cathode. Y-Capacitor The placement of the Y-type cap should be directly from the primary input filter capacitor positive terminal to the common/ return terminal of the transformer secondary. If a second Y- type cap is required from primary to secondary return, connect the primary side directly to the negative terminal of the input capacitor. Such a placement will route high magnitude common mode surge currents away from the PeakSwitch device. Note – if an input π (C, L, C) EMI filter is used, then the inductor in the filter should be placed between the negative terminals on the input filter capacitors. Optocoupler Place the optocoupler physically close to the PeakSwitch to minimize the primary side trace lengths. Keep the high current high voltage drain and clamp traces away from the optocoupler to prevent noise pick up. Output Diode For best performance, the area of the loop connecting the secondary winding, the output diode and the output filter capacitor should be minimized. In addition, sufficient copper area should be provided at the anode and cathode terminal of the diode for heatsinking. A larger area is preferred at the quite cathode terminal. A large anode area can increase high frequency radiated EMI. Quick Design Checklist As with any power supply design, all PeakSwitch designs should be verified on the bench to make sure that component specifications are not exceeded under worst case conditions. The following minimum set of tests is strongly recommended: 1. Maximum drain voltage – Verify that the VDS does not exceed

650 V at highest input voltage and peak (overload) output

power. The 50 V margin to the 700 V BVDSS specification allows margin for design variation. 2. Maximum drain currents – Verify the simultaneous drain voltage and current levels are within the curve provided in Figure 29 under worst case conditions. Typically this occurs at start up (and during an output short circuit), highest input line voltage and maximum ambient temperature. When making this measurement using a current probe, to monitor the drain current, ensure the results are corrected for the 10-20 ns current probe delay. 3. Maximum drain current – At maximum ambient temperature, maximum input voltage and peak output (overload) power, verify drain current waveforms show no signs of transformer saturation. If the transformer shows signs of saturation, it should be redesigned with a lower flux density, or a higher quality core material should be used. To prevent false triggering of the current limit, verify the leading edge current spike event is below IINIT(MIN) at the end of the tLEB(MIN). Under all conditions, the maximum drain current should be below the absolute maximum limit specified in the Absolute Maximum Ratings section. 4. Thermal Check – At specified maximum output power, minimum input voltage and maximum ambient temperature, verify that the temperature specifications are not exceeded for PeakSwitch, transformer, output diode and output capacitors. Enough thermal margin should be allowed for part-to-part variation of the RDS(ON) of PeakSwitch as specified in the data sheet. Under low line, maximum power, a maximum PeakSwitch SOURCE pin or tab temperature of 110 °C is recommended to allow for these variations. Design Tools Up-to-date information on design tools can be found at the Power Integrations web site: www.powerint.com.

Rev. I 02/07 Parameter Symbol Conditions SOURCE = 0 V; TJ = -40 to 125 °C See Figure 18 (Unless Otherwise Specified) Min Typ Max Units CONTROL FUNCTIONS Output Frequency fOSC TJ = 25 °C See Figure 4 Average 250 277 304 kHzPeak-Peak Jitter 16 Maximum Duty Cycle DCMAX S1 Open 62 65 68 % EN/UV Pin Turn Off Threshold Current IDIS -350 -240 -200 µA EN/UV Pin Voltage VEN IEN/UV = -125 µA 0.4 1.0 1.5 VIEN/UV = 25 µA 1.3 2.0 2.7 DRAIN Supply Current IS1 VEN/UV = 0 V 350 475 600 µA IS2 EN/UV Open (MOSFET Switching) See Note A, B PKS603 460 570 690 PKS604 600 725 870 PKS605 700 875 1050 PKS606 950 1175 1400 PKS607 1160 1430 1700 BYPASS Pin Charge Current ICH1 VBP = 0 V, TJ = 25 °C See Note C mA ICH2 VBP = 4 V, TJ = 25 °C See Note C ABSOLUTE MAXIMUM RATINGS(1,) Notes: 1. All voltages referenced to SOURCE, TA = 25 °C. 2. Normally limited by internal circuitry. 3. 1/16 in. from case for 5 seconds. 4. Maximum ratings specified may be applied one at a time, without causing permanent damage to the product. Exposure to Absolute Maximum Rating conditions for extended periods of time may affect product reliability. 5. Peak DRAIN current is allowed while the DRAIN voltage is simultaneously less than 400 V . See also Figure 29. THERMAL IMPEDANCE Thermal Impedance: Y/F Package: P Package: Notes: 1. Free standing with no heatsink. 2. Measured at the back surface of tab. 5. Measured on the SOURCE pin close to plastic interface.

Rev. I 02/07 Parameter Symbol Conditions SOURCE = 0 V; TJ = -40 to 125 °C See Figure 18 (Unless Otherwise Specified) Min Typ Max Units CONTROL FUNCTIONS (cont.) BYPASS Pin Shunt Regulator Voltage VBP(SH) See Note D 6.0 6.3 6.7 V BYPASS Pin Voltage VBP 5.5 5.8 6.15 V BYPASS Pin Voltage Hysteresis VBPH 0.8 1.0 1.3 V EN/UV Pin Line Under-Voltage Threshold ILUV TJ = 25 °C 22.5 25 27.5 µA CIRCUIT PROTECTION Current Limit ILIMIT PKS603 P TJ = 25 °C di/dt = 200 mA/µs See Note E 0.75 0.81 0.87 A PKS604 P/Y/F TJ = 25 °C di/dt = 290 mA/µs See Note E 1.35 1.45 1.55 PKS605 P TJ = 25 °C di/dt = 290 mA/µs See Note E 1.35 1.45 1.55 PKS605 Y/F TJ = 25 °C di/dt = 325 mA/µs See Note E 1.76 1.89 2.02 PKS606 P TJ = 25 °C di/dt = 255 mA/µs See Note E 1.40 1.51 1.62 PKS606 Y/F TJ = 25 °C di/dt = 660 mA/µs See Note E 2.60 2.80 3.00 PKS607 Y/F TJ = 25 °C di/dt = 800 mA/µs 2.79 3.00 3.21 Power Coefficient I2f PKS603 P TJ = 25 °C di/dt = 200 mA/µs 164 182 204 A2kHz PKS604 P/Y/F TJ = 25 °C di/dt = 290 mA/µs 524 582 652 PKS605 P TJ = 25 °C di/dt = 290 mA/µs 524 582 652 PKS605 Y/F TJ = 25 °C di/dt = 325 mA/µs 890 989 1108 PKS606 P TJ = 25 °C di/dt = 255 mA/µs 569 632 708 PKS606 Y/F TJ = 25 °C di/dt = 660 mA/µs 1955 2172 2433 PKS607 Y/F TJ = 25 °C di/dt = 800 mA/µs 2242 2493 2793

Rev. I 02/07 Parameter Symbol Conditions SOURCE = 0 V; TJ = -40 to 125 °C See Figure 18 (Unless Otherwise Specified) Min Typ Max Units CIRCUIT PROTECTION (cont.) Initial Current Limit IINIT See Figure 21 See Note F 0.75 × ILIMIT(Min) mA Leading Edge Blanking Time tLEB TJ = 25 °C See Note F 170 215 ns Current Limit Delay tILD TJ = 25 °C See Notes F, G 150 ns Thermal Shutdown Temperature 135 142 150 °C Thermal Shutdown Hysteresis 75 °C OUTPUT ON-State Resistance RDS(ON) PKS603 ID = 81 mA TJ = 25 °C 7.8 9.0 W TJ = 100 °C 11.7 13.5 PKS604 ID = 150 mA TJ = 25 °C 5.2 6.0 TJ = 100 °C 7.8 9.0 PKS605 ID = 200 mA TJ = 25 °C 3.9 4.5 TJ = 100 °C 5.8 6.7 PKS606 ID = 300 mA TJ = 25 °C 2.6 3.0 TJ = 100 °C 3.9 4.5 PKS607 ID = 300 mA TJ = 25 °C 2.0 2.3 TJ = 100 °C 3.0 3.5 OFF-State Drain Leakage Current IDSS1 VBP = 6.2 V VEN/UV = 0 V VDS = 560 V TJ = 125 °C See Note H 200 µA IDSS2 VBP = 6.2 V VEN/UV = 0 V VDS = 375 V TJ = 50 °C See Note H Breakdown Voltage BVDSS VBP = 6.2 V, VEN/UV = 0 V, See Note I, TJ = 25 °C 700 V Drain Supply Voltage 50 V Output EN/UV Delay tEN/UV See Figure 20 5 µs Output Disable Setup Time tDST 0.5 µs

Rev. I 02/07 NOTES: A. Total current consumption is the sum of IS1 and IDSS when EN/UV pin is shorted to ground (MOSFET not switching) and the sum of IS2 and IDSS when EN/UV pin is open (MOSFET switching). B. Since the output MOSFET is switching, it is difficult to isolate the switching current from the supply current at the DRAIN. An alternative is to measure the BYPASS pin current at 6.1 V. C. See Typical Performance Characteristics section for BYPASS pin startup charging waveform. D. BYPASS pin is externally supplied (bias winding). E. For current limit at other di/dt values, refer to Figure 25. F. This parameter is derived from characterization. G. This parameter is derived from the change in current limit measured at 1X and 4X of the di/dt shown in the ILIMIT specification. H. IDSS1 is the worst case OFF state leakage specification at 80% of BVDSS and maximum operating junction temperature. IDSS2 is a typical specification under worst case application conditions (rectified 265 VAC) for no-load consumption calculations. I. Breakdown voltage may be checked against minimum BVDSS specification by ramping the DRAIN pin voltage up to but not exceeding minimum BVDSS. J. Auto-restart on time has the same temperature characteristics as the oscillator (inversely proportional to frequency). Auto-restart on time is extended during startup and certain fault conditions because the controller reduces its oscillator clock frequency to prevent excessive drain currents. If excessive drain currents are still occuring half way through the auto-restart on time, output MOSFET switching is disabled for the remainder of that auto-restart on time episode (if the line is not sensed) or the supply latches off (if the line is sensed and adequate line voltage is present). K. Only applicable if no UV resistor is present at the EN/UV pin. 5 s applies only if the preceding switching auto- restart event did not result in EN/UV pin going low. In that event, the first auto-restart off-time is 150 ms. Parameter Symbol Conditions SOURCE = 0 V; TJ = -40 to 125 °C See Figure 18 (Unless Otherwise Specified) Min Typ Max Units OUTPUT (cont.) Auto-Restart ON Time tAR TJ = 25 °C See Note J 30 ms Auto-Restart OFF Time tAROFF See Note K 5 s

Figure 19. Duty Cycle Measurement. Figure 20. Output Enable Timing. Figure 18. PeakSwitch General Test Circuit. Figure 21. Current Limit Envelope.

5 W S2

NOTE: This test circuit is not applicable for current limit or output characteristic measurements.

Rev. I 02/07 PART ORDERING INFORMATION PeakSwitch Product Family Series Number Package Identifier P Plastic DIP-8C Y Plastic TO-220-7C F Plastic TO-262-7C Lead Finish N Pure Matte Tin (Pb-Free) PI-2644-122004 Notes: 1. Controlling dimensions are inches. Millimeter dimensions are shown in parentheses. 2. Pin numbers start with Pin 1, and continue from left to right when viewed from the front. 3. Dimensions do not include mold flash or other protrusions. Mold flash or protrusions shall not exceed .006 (.15mm) on any side. 4. Minimum metal to metal spacing at the package body for omitted pin locations is .068 in. (1.73 mm). 5. Position of terminals to be measured at a location .25 (6.35) below the package body. 6. All terminals are solder plated. Y07C PIN 1 PIN 7 MOUNTING HOLE PATTERN .050 (1.27) .150 (3.81) .050 (1.27) .150 (3.81) .050 (1.27) .050 (1.27) .100 (2.54) PIN 1 .010 (.25) M .461 (11.71) .495 (12.57) .390 (9.91) .156 (3.96) .860 (21.84) .880 (22.35) .024 (.61) .034 (.86) .068 (1.73) MIN .050 (1.27) BSC .150 (3.81) BSC .108 (2.74) REF PIN 1 & 7 7° TYP. PIN 2 & 4 .040 (1.02) .060 (1.52) .190 (4.83) .210 (5.33) .012 (.30) .024 (.61) .080 (2.03) .120 (3.05) .234 (5.94) .261 (6.63) .165 (4.19) .185 (4.70) .040 (1.02) .060 (1.52) .045 (1.14) .055 (1.40) .670 (17.02) REF. .570 (14.48) REF. TO-220-7C PKS 60 P N

Rev. I 02/07 Notes: 1. Package dimensions conform to JEDEC specification MS-001-AB (Issue B 7/85) for standard dual-in-line (DIP) package with .300 inch row spacing. 2. Controlling dimensions are inches. Millimeter sizes are shown in parentheses. 3. Dimensions shown do not include mold flash or other protrusions. Mold flash or protrusions shall not exceed .006 (.15) on any side. 4. Pin locations start with Pin 1, and continue counter-clock- wise to Pin 8 when viewed from the top. The notch and/or dimple are aids in locating Pin 1. Pin 3 is omitted. 5. Minimum metal to metal spacing at the package body for the omitted lead location is .137 inch (3.48 mm). 6. Lead width measured at package body. 7. Lead spacing measured with the leads constrained to be perpendicular to plane T. .008 (.20) .015 (.38) .300 (7.62) BSC (NOTE 7) .300 (7.62) .390 (9.91) .367 (9.32) .387 (9.83) .240 (6.10) .260 (6.60) .125 (3.18) .145 (3.68) .057 (1.45) .068 (1.73) .120 (3.05) .140 (3.56) .015 (.38) MINIMUM .048 (1.22) .053 (1.35) .100 (2.54) BSC .014 (.36) .022 (.56) -E- Pin 1 SEATING PLANE -D- -T- P08C DIP-8C PI-3933-100504 D S .004 (.10)⊕ T E D S .010 (.25) M⊕ (NOTE 6) .137 (3.48) MINIMUM

Rev. I 02/07 PI-2757-122004 Notes: 1. Controlling dimensions are inches. Millimeter dimensions are shown in parentheses. 2. Pin numbers start with Pin 1, and continue from left to right when viewed from the front. 3. Dimensions do not include mold flash or other protrusions. Mold flash or protrusions shall not exceed .006 (.15mm) on any side. 4. Minimum metal to metal spacing at the pack- age body for omitted pin locations is .068 inch (1.73 mm). 5. Position of terminals to be measured at a location .25 (6.35) below the package body. 6. All terminals are solder plated.F07C PIN 1 PIN 7 MOUNTING HOLE PATTERN .050 (1.27) .150 (3.81) .050 (1.27) .150 (3.81) .050 (1.27) .050 (1.27) .100 (2.54) PIN 1 .010 (.25) M .326 (8.28) .336 (8.53) .390 (9.91) .420 (10.67) .795 (20.18) REF. .024 (.61) .034 (.86) .050 (1.27) BSC .150 (3.81) BSC .055 (1.40) .066 (1.68) PIN 1 & 7 7° TYP. PIN 2 & 4 .040 (1.06) .060 (1.52) .190 (4.83) .210 (5.33) .012 (.30) .024 (.61) .080 (2.03) .120 (3.05) .165 (4.17) .185 (4.70) .040 (1.02) .060 (1.52) .045 (1.14) .055 (1.40) .595 (15.10) REF. .495 (12.56) REF. TO-262-7C .068 (1.73) MIN

Rev. I 02/07

Rev. I 02/07 Revision Notes Date F 1) Final Release Data Sheet. 3/06 G Revised device symbol in Figures 1 and 15 to be consistent with other PI documentation (added second ground connection). Revised layout of Figure 17 (PI-4326). H Revised grounding in Figure 1 to match actual implementation. 6/06 I Added PKS607. 2/07 For the latest updates, visit our website: www.powerint.com Power Integrations reserves the right to make changes to its products at any time to improve reliability or manufacturability. Power Integrations does not assume any liability arising from the use of any device or circuit described herein. POWER INTEGRATIONS MAKES NO WARRANTY HEREIN AND SPECIFICALLY DISCLAIMS ALL WARRANTIES INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF MERCHANTABILITY , FITNESS FOR A PARTICULAR PURPOSE, AND NON-INFRINGEMENT OF THIRD PARTY RIGHTS. PATENT INFORMATION The products and applications illustrated herein (including transformer construction and circuits external to the products) may be covered by one or more U.S. and foreign patents, or potentially by pending U.S. and foreign patent applications assigned to Power Integrations. A complete list of Power Integrations’ patents LIFE SUPPORT POLICY POWER INTEGRATIONS’ PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROV AL OF THE PRESIDENT OF POWER INTEGRATIONS. As used herein: 1. A Life support device or system is one which, (i) is intended for surgical implant into the body, or (ii) supports or sustains life, and (iii) whose failure to perform, when properly used in accordance with instructions for use, can be reasonably expected to result in significant injury or death to the user. 2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. The PI logo, TOPSwitch, TinySwitch, LinkSwitch, DPA-Switch, PeakSwitch, Clampless, EcoSmart, E-Shield, Filterfuse, StackFET, PI Expert and PI FACTS are trademarks of Power Integrations, Inc. Other trademarks are property of their respective companies. ©Copyright 2007, Power Integrations, Inc. Power Integrations Worldwide Sales Support Locations WORLD HEADQUARTERS

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