PKD01

REV.A

Document overview

• PDF pages: 18

Technical content

REV.A Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. a PKD01 Tel: 781/329-4700 World Wide Web Site: http://www.analog.com Fax: 781/326-8703 © Analog Devices, Inc., 2001 Monolithic Peak Detector with Reset-and-Hold Mode FUNCTIONAL BLOCK DIAGRAM PKD01 OUTPUT BUFFER OUTPUT LOGIC GND CH DET –IN +IN –IN +IN RST –IN+IN OUTPUT V+ V– CMP A B C GA TED "gm" AMP GA TED "gm" AMP RST DET OPERA TIONAL MODE PEAK DETECT PEAK HOLD RESET INDETERMINA TE SWITCHES SHOWN FOR: RST = “0,” DET = “0”

FEATURES

Monolithic Design for Reliability and Low Cost High Slew Rate: 0.5 V/ /H9262s Low Droop Rate TA = 25/H11543C: 0.1 mV/ms TA = 125/H11543C: 10 mV/ms Low Zero-Scale Error: 4 mV Digitally Selected Hold and Reset Modes Reset to Positive or Negative Voltage Levels Logic Signals TTL and CMOS Compatible Uncommitted Comparator On-Chip Available in Die Form GENERAL DESCRIPTION The PKD01 tracks an analog input signal until a maximum amplitude is reached. The maximum value is then retained as a peak voltage on a hold capacitor. Being a monolithic circuit, the PKD01 offers significant performance and package density advantages over hybrid modules and discrete designs without sacrificing system versatility. The matching characteristics attained in a monolithic circuit provide inherent advantages when charge injection and droop rate error reduction are primary goals. Innovative design techniques maximize the advantages of mono- lithic technology. Transconductance (g m) amplifiers were chosen over conventional voltage amplifier circuit building blocks. The g m amplifiers simplify internal frequency compensation, minimize acquisition time and maximize circuit accuracy. Their outputs are easily switched by low glitch current steering circu its. The steered outputs are clamped to reduce cha rge injection errors upon entering the hold mode or exiting the reset mode. The inher- ently low zero-scale error is further reduced by active Zener-Zap trimming to optimize overall accuracy. The output buffer amplifier features an FET input stage to reduce droop rate error during lengthy peak hold periods. A bias current cancellation circuit minimizes droop error at high ambi- ent temperatures. Through the DET control pin, new peaks may eit her be detected or ignored. Detected peaks are presented as positive output levels. Positive or negative peaks may be detected without additional active circuits, since Amplifier A can operate as an inverting or noninverting gain stage. An uncommitted comparator provides many application o ptions. Status indication and logic shaping/shifting are typical examples.

REV. A–2– PKD01–SPECIFICATIONS

ELECTRICAL CHARACTERISTICS

Parameter Symbol Conditions Min Typ Max Min Typ Max Unit gm AMPLIFIERS A, B Zero-Scale Error V ZS 24 37m V Input Offset Voltage V OS 23 36m V Input Bias Current I B 80 150 80 250 nA Input Offset Current I OS 20 40 20 75 nA Voltage Gain A V RL = 10 kΩ, VO = ± 10 V 18 25 10 25 V/mV Open-Loop Bandwidth BW A V = 1 0.4 0.4 MHz Common-Mode Rejection Ratio CMRR –10 V ≤ VCM ≤ + 1 0 V 8 09 0 7 49 0 d B Power Supply Rejection Ratio PSRR ± 9 V ≤ VS ≤ ±1 8 V 8 69 6 7 69 6 d B Input Voltage Range1 VCM ± 10 ± 11 ± 10 ± 11 V Slew Rate SR 0.5 0.5 V/ µs Feedthrough Error1 ∆VIN = 20 V, DET = 1, RST = 0 66 80 66 80 dB Acquisition Time to 0.1% Accuracy1 tAQ 20 V Step, AVCL = +1 41 70 41 70 µs Acquisition Time to t AQ 20 V Step, AVCL = +1 45 45 µs 0.01% Accuracy 1 COMPARATOR Input Offset Voltage V OS 0.5 1.5 1 3 mV Input Bias Current I B 700 1000 700 1000 nA Input Offset Current I OS 75 300 75 300 nA Voltage Gain A V 2k Ω Pull-Up Resistor to 5 V 5 7.5 3.5 7.5 V/mV Common-Mode Rejection Ratio CMRR –10 V ≤ VCM ≤ +10 V 82 106 82 106 dB Power Supply Rejection Ratio PSRR ± 9 V ≤ VS ≤ ±1 8 V 7 69 0 7 69 0 d B Input Voltage Range1 VCM ± 11.5 ± 12.5 ± 11.5 ± 12.5 V “OFF” Output Leakage Current I L VOUT = 5 V 2 58 0 2 58 0 µA Output Short-Circuit Current I SC VOUT = 5 V 7 12 45 7 12 45 mA Response Time2 tS 5 mV Overdrive, 2 kΩ Pull-Up 150 150 ns Resistor to 5 V DIGITAL INPUTS – RST, DET2 Logic “1” Input Voltage V H 22 V Logic “0” Input Voltage V L 0.8 0.8 V Logic “1” Input Current I INH VH = 3.5 V 0.02 1 0.02 1 µA Logic “0” Input Current I INL VL = 0.4 V 1.6 10 1.6 10 µA MISCELLANEOUS Droop Rate3 VDR TJ = 25°C 0.01 0.07 0.01 0.1 mV/ms TA = 25°C 0.02 0.15 0.03 0.20 mV/ms Output Voltage Swing: V OP DET = 1 Amplifier C R L = 2.5 kΩ± 11.5 ± 12.5 ± 11 ± 12 V Short-Circuit Current: Amplifier C I SC 7 15 40 7 15 40 mA Switch Aperture Time t AP 75 75 ns Switch Switching Time ts 50 50 ns Slew Rate: Amplifier C SR R L = 2.5 kΩ 2.5 2.5 V/ µs Power Supply Current I SY N o L o a d 57 69m A NOTES 1Guaranteed by design. 2DET = 1, RST = 0. 3Due to limited production test times, the droop current corresponds to junction temperature (T J). The droop current vs. time (after power-on) curve clarified this point. Since most devices (in use) are on for more than 1 second, ADI specifies droop rate for ambient temperature (T A) also. The warmed-up (T A) droop current specification is correlated to the junction temperature (T J) value. ADI has a droop current cancellation circuit that minimizes droop current at high temperature. Ambient (T A) temperature specifications are not subject to production testing. Specifications subject to change without notice. (@ VS = /H1155015 V, CH = 1000 pF, TA = 25/H11543C, unless otherwise noted.)

REV. A –3– PKD01 Parameter Symbol Conditions Min Typ Max Min Typ Max Unit “gm” AMPLIFIERS A, B Zero-Scale Error V ZS 47 61 2m V Input Offset Voltage V OS 36 51 0m V Average Input Offset Drift 1 TCVOS –9 –24 –9 –24 µV/°C Input Bias Current I B 160 250 160 500 nA Input Offset Current I OS 30 100 30 150 nA Voltage Gain A V RL = 10 kΩ, VO = ± 10 V 7.5 9 5 9 V/mV Common-Mode Rejection Ratio CMRR –10 V ≤ VCM ≤ +10 V 74 82 72 80 dB Power Supply Rejection Ratio PSRR ± 9 V ≤ VS ≤ ± 18 V 80 90 70 90 dB Input Voltage Range 1 VCM ± 10 ± 11 ± 10 ± 11 V Slew Rate SR 0.4 0.4 V/ µs Acquisition Time to 0.1% Accuracy1 tAQ 20 V Step, AVCL = +1 60 60 µs COMPARATOR Input Offset Voltage V OS 2 2.5 2 5 mV Average Input Offset Drift 1 TCVOS –4 –6 –4 –6 µV/°C Input Bias Current I B 1000 2000 1100 2000 nA Input Offset Current I OS 100 600 100 600 nA Voltage Gain A V 2 kΩ Pull-Up Resistor to 5 V 4 6.5 2.5 6.5 V/mV Common-Mode Rejection Ratio CMRR –10 V ≤ VCM ≤ +10 V 80 100 80 92 dB Power Supply Rejection Ratio PSRR ± 9 V ≤ VS ≤ ± 18 V 72 82 72 86 dB Input Voltage Range 1 VCM ± 11 ± 11 V OFF Output Leakage Current I L VOUT = 5 V 25 100 100 180 µA Output Short-Circuit Current I SC VOUT = 5 V 6 10 45 6 10 45 mA Response Time t S 5 mV Overdrive, 2 k Ω Pull-Up Resistor to 5 V 200 200 ns DIGITAL INPUTS – RST, DET2 Logic “1” Input Voltage V H 22 V Logic “0” Input Voltage V L 0.8 0.8 V Logic “1” Input Current I INH VH = 3.5 V 0.02 1 0.02 1 µA Logic “0” Input Current I INL VL = 0.4 V 2.5 15 2.5 15 µA MISCELLANEOUS Droop Rate3 VDR TJ = Max Operating Temp. 1.2 10 3 15 mV/ms TA = Max Operating Temp. DET = 1 2.4 20 6 20 mV/ms Output Voltage Swing Amplifier C V OP RL = 2.5 kΩ± 11 ± 12 ± 10.5 ± 12 V Short-Circuit Current Amplifier C I SC 6 1 24 06 1 24 0 m A Switch Aperture Time t AP 75 75 ns Slew Rate: Amplifier C SR R L = 2.5 kΩ 22 V / µs Power Supply Current I SY No Load 5.5 8 6.5 10 mA NOTES 1Guaranteed by design. 2DET = 1, RST = 0. 3Due to limited production test times, the droop current corresponds to junction temperature (T J). The droop current vs. time (after power-on) curve clarifies this point. Since most devices (in use) are on for more than 1 second, ADI specifies droop rate for ambient temperature (T A) also. The warmed-up (T A) droop current specification is correlated to the junction temperature (T J) value. ADI has a droop current cancellation circuit that minimizes droop current at high temperature. Ambient (T A) temperature specifications are not subject to production testing. Specifications subject to change without notice. (@ VS = /H1155015 V, CH = 1000 pF, –55 /H11543C ≤ TA ≤ +125/H11543C for PKD01AY, –25 /H11543C ≤ TA ≤ +85/H11543C for PKD01EY, PKD01FY and 0/H11543C ≤ TA ≤ +70/H11543C for PKD01EP, PKD01FP, unless otherwise noted.)

REV. A PKD01 –4– CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the PKD01 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. WARNING! ESD SENSITIVE DEVICE ABSOLUTE MAXIMUM RATINGS 1, 2 Logic and Logic Ground Comparator Output Voltage Storage Temperature Range Operating Temperature Range NOTES 1Absolute maximum ratings apply to both DICE and packaged parts, unless otherwise noted. 2Stresses above those listed under Absolute Maximum Ratings may cause perma- nent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. THERMAL CHARACTERISTICS Package Type /H9258JA* /H9258JC Unit 14-Lead Hermetic DIP (Y) 99 12 °C/W 14-Lead Plastic DIP (P) 76 33 °C/W *θJA is specified for worst-case mounting conditions, i.e., θJA is specified for device in socket for cerdip and PDIP packages. ORDERING GUIDE 1 Temperature Package Package Model2 Range Description Option PKD01AY –55 °C to +85°C Cerdip Q-14 PKD01EY –25 °C to +85°C Cerdip Q-14 PKD01FY –25 °C to +85°C Cerdip Q-14 PKD01EP 0 °C to 70°C Plastic DIP N-14 PKD01FP 0 °C to 70°C Plastic DIP N-14 NOTES 1Burn-in is available on commercial and industrial temperature range parts in cerdip, plastic DIP, and TO-can packages. 2For devices processed in total compliance to MIL-STD-883, add /883 after part number. Consult factory for 883 data sheet. PIN CONFIGURATION DET LOGIC GND COMP OUT –IN C +IN C –IN B +IN B RST OUTPUT C H –IN A +IN A PKD01 DICE CHARACTERISTICS

REV. A PKD01 –5– WAFER TEST LIMITS PKD01N Parameter Symbol Conditions Limit Unit “gm” AMPLIFIERS A, B Zero-Scale Error V ZS 7m V m a x Input Offset Voltage V OS 6m V m a x Input Bias Current I B 250 nA max Input Offset Current I OS 75 nA max Voltage Gain A V RL = 10 kΩ, VO = ±10 V 10 V/mV min Common-Mode Rejection Ratio CMRR –10 V ≤ VCM ≤ +10 V 74 dB min Power Supply Rejection Ratio PSRR ± 9 V ≤ VS ≤ ±18 V 76 dB min Input Voltage Range 1 VCM ± 11.5 V min Feedthrough Error ∆VIN = 20 V, DET = 1, RST = 0 66 dB min COMPARATOR Input Offset Voltage V OS 3m V m a x Input Bias Current I B 1000 nA max Input Offset Current I OS 300 nA max Voltage Gain1 AV 2 kΩ Pull-Up Resistor to 5 V 3.5 V/mV min Common-Mode Rejection Ratio CMRR –10 V ≤ VCM ≤ +10 V 82 dB min Power Supply Rejection Ratio PSRR ± 9 V ≤ VS ≤ ±18 V 76 dB min Input Voltage Range 1 VCM ± 11.5 V min Low Output Voltage V OL ISINK ≤ 5 mA, Logic GND = 5 V 0.4 V max –0.2 V min “OFF” Output Leakage Current I L VOUT = 5 V 80 µA max Output Short-Circuit Current I SC VOUT = 5 V 45 mA min 7 mA min DIGITAL INPUTS–RST, DET2 Logic “1” Input Voltage V H 2V m i n Logic “0” Input Voltage V L 0.8 V max Logic “1” Input Current I INH VH = 3.5 V 1 µA max Logic “0” Input Current I INL VL = 0.4 V 10 µA max MISCELLANEOUS Droop Rate3 VDR TJ = 25°C, 0.1 mV/ms max TA = 25°C 0.20 mV/ms max Output Voltage Swing Amplifier C V OP RL = 2.5 kΩ± 11 V min Short-Circuit Current Amplifier C I SC 40 mA max 7 mA min Power Supply Current I SY No Load 9 mA max gm AMPLIFIERS A, B Slew Rate SR 0.5 V/ µs Acquisition Time1 tA 0.1% Accuracy, 20 V Step, A VCL = 1 41 µs tA 0.01% Accuracy, 20 V Step, A VCL = 1 45 µs COMPARATOR Response Time 5 mV Overdrive, 2 kΩ Pull-Up Resistor to 5 V 150 ns MISCELLANEOUS Switch Aperture Time t AP 75 ns Switching Time t S 50 ns Buffer Slew Rate SR R L = 2.5 kΩ 2.5 V/ µs NOTES 1Guaranteed by design. 2DET = 1, RST = 0. 3Due to limited production test times, the droop current corresponds to junction temperature (T J). The droop current vs. time (after power-on) curve clarifies this point. Since most devices (in use) are on for more than 1 second, ADI specifies droop rate for ambient temperature (T A) also. The warmed-up (T A) droop current specification is correlated to the junction temperature (T J) value. ADI has a droop current cancellation circuit that minimizes droop current at high temperature. Ambient (TA) temperature specifications are not subject to production testing. (@ VS = /H1155015 V, CH = 1000 pF, TA = 25/H11543C, unless otherwise noted.)

REV. A PKD01 –6– –Typical Performance Characteristics –18 46 1 8 91 21 5 –10 –14 INPUT + RANGE = V+ –55/H11543C TA +125/H11543C V– SUPPL Y –55/H11543C +25/H11543C +125/H11543C INPUT RANGE OF AMPLIFIER – V SUPPL Y VOL T AGE +V AND –V –V TPC 1. A and B Input Range vs. Supply Voltage FREQUENCY – Hz INPUT NOISE VOL T AGE – nV/ Hz 1000 100 11 0 1 k 100 RS = 10k/H9024 RS = 0 TPC 4. Input Spot Noise vs. Frequency –1.0 1.0 +125/H11543C +25/H11543C –55/H11543C 0.5 –0.5 VIN – V ERROR – mV –10 –50 5 1 0 POLARITY OF ERROR MA Y BE POSITIVE OR NEGA TIVE CH = 1000pF TA = 25/H11543C TPC 7. Amplifier A Charge Injec- tion Error vs. Input Voltage and Temperature TEMPERA TURE – /H11543C –75 –50 125–25 0 25 50 75 100 OFFSET VOL T AGE – mV TPC 2. A and B Amplifiers Offset Voltage vs. Temperature BANDWIDTH – kHz RMS NOISE – /H9262V 100 0.1 1 100 10 1000 VS = 15V TA = 25/H11543C AV = +1 TPC 5. Wideband Noise vs. Bandwidth SUPPL Y VOL T AGE +V AND –V – V OUTPUT SWING – V –18 46 1 8 91 2 1 5 –10 –14 V– SUPPL Y –55/H11543C +25/H11543C +125/H11543C V+ SUPPL Y –55/H11543C +25/H11543C +125/H11543C RL = 10k/H9024 TPC 8. Output Voltage Swing vs. Supply Voltage (Dual Supply Operation) TEMPERA TURE – /H11543C A,B IOS – nA –75 –50 150–25 0 25 75 100 12550 TPC 3. A, B IOS vs. Temperature –1.0 1.0 +125/H11543C +25/H11543C –55/H11543C0.5 –0.5 VIN – V ERROR – mV –10 –50 5 1 0 TPC 6. Amplifier B Charge Injec- tion Error vs. Input Voltage and Temperature LOAD RESISTOR TO GROUND – k/H9024 OUTPUT SWING – V olts 12.5 –15 1.0 10.0 0.1 2.5 –2.5 –5.0 10.0 5.0 7.5 –12.5 –10.0 –7.5 +25/H11543C –55/H11543C +125/H11543C –55/H11543C +25/H11543C +125/H11543C TPC 9. Output Voltage vs. Load Resistance

REV. A PKD01 –7– FREQUENCY – Hz PK OF SINEWAVE – V 100 1k 1M 10k 100k 2mV ERROR 200mV ERROR 20mV ERROR TPC 10. Output Error vs. Frequency and Input Voltage 100 TA = 25/H11543C TIME – 20/H9262s/DIV OUTPUT VOL T AGE – 5V/DIV TPC 13. Large-Signal Inverting Response TA = 25/H11543C TIME – 20/H9262s/DIV OUTPUT VOL T AGE – 5mV/DIV 100 TA = 25/H11543C TPC 16. Settling Time for +10 V to

0 V Step Input

CH = 1000pF PEAK OUTPUT TPC 11. Settling Response 100 TA = 25/H11543C TIME – 20/H9262s/DIV OUTPUT VOL T AGE – 5V/DIV TPC 14. Large-Signal Noninverting Response FREQUENCY – Hz GAIN – dB –30 1 10 10M 100 1k 10k 100k 1M PHASE LAG – Degrees 180 135 TA = 25/H11543C RL = 10k/H9024 CL = 30pF CH = 1000pF GAIN PHASE CH = 1000pF CH = 1000pF TPC 17. Small-Signal Open-Loop Gain/Phase vs. Frequency 100 2/H9262s CH = 1000pF 10mV DETECTED PEAK 3kHz SINEWAVE INPUT 10mV 10V TPC 12. Settling Response 100 TIME – 20/H9262s/DIV OUTPUT VOL T AGE – 5mV/DIV TA = 25/H11543C TPC 15. Settling Time for –10 V to FREQUENCY – Hz CHANNEL-TO-CHANNEL ISOLA TION – dB 120 0 1 10 10M 100 1k 10k 100k 1M 100 TA = 25/H11543C AMPLIFIER A(B) OFF , INPUT = 20V p-p AMPLIFIER B(B) ON, INPUT = 0V TEST CONDITION: CH = 1000pF AMPLIFIER A AND B CONNECTED IN +1 GAIN TPC 18. Channel-to-Channel Isolation vs. Frequency

REV. A PKD01 –8– TPC 26. Comparator Output Response Time (2 kΩ Pull-Up Resistor, TA = 25°C) TPC 27. Comparator Output Response Time (2 kΩ Pull-Up Resistor, TA = 25°C) TPC 24. Acquisition of Step Input 100 50/H9262s5V 10V 10V PEAK DETECT PEAK OUTPUT RESET INPUT RESET +10V –10V +10V –10V TPC 21. Acquisition Time vs. External Hold Capacitor and Acquisition Step TPC 23. Droop Rate vs. Temperature TPC 20. Droop Rate vs. Time after Power On TPC 25. Acquisition of Sine Wave Peak 100 50/H9262s DETECTED PEAK RESET +10V –10V CH = 1000pF 3kHz SINEWAVE INPUT TPC 22. Acquisition Time vs. Input Voltage Step Size TPC 19. Off Isolation vs. Frequency FREQUENCY – Hz OFF ISOLA TION – dB 100 0 1 10 10M 100 1k 10k 100k 1M A, AV = +1 B, AV = /H115501 A, AV = –1 1V 5mV 50ns COMP ARA TOR OUTPUT TIME – 50ns/DIV OUTPUT VOL T AGE – V INPUT VOL T AGE – mV 100 50ns1V 5mV COMP ARA TOR OUTPUT 1V 5mV 50ns COMP ARA TOR OUTPUT TIME – 50ns/DIV OUTPUT VOL T AGE – V INPUT VOL T AGE – mV 100 50ns1V 5mV COMP ARA TOR OUTPUT TEMPERA TURE – /H11543C DROOP RA TE (mV/sec), CH = 1000pF 10000 1000 –100 –50 50 0 100 100 500 AMBIENT TEMPERA TURE JUNCTION TEMPERA TURE INPUT STEP – V SETTLING TIME – /H9262s 51 0 1 5 2 00 TA = 25/H11543C CH = 1000pF TO 2mV TO 20mV TO 200mV HOLD CAP ACIT ANCE – pF ACQUISITION TIME TO 0.1% ACCURACY – /H9262s 500 200 400 300 2000 4000 6000 8000 100000 100 20V STEP TO 20mV (0.1%) 10V STEP TO 10mV (0.1%) 5V STEP TO 5mV (0.1%) 1V STEP TO 1mV (0.1%) TIME AFTER POWER APPLIED – Minutes DROOP RA TE – mV/ms 0 1 TA = 125/H11543C CH = 1000pF 23456789 1 00

REV. A PKD01 –9– SUPPL Y VOL T AGE +V AND –V – V INPUT LOGIC RANGE – V –18 46 91 2 1 51 8 –10 –14 +VIN V+ FOR –55/H11543C TA +125/H11543C –55/H11543C +125/H11543C +25/H11543C TPC 28. Input Logic Range vs. Supply Voltage SUPPL Y +V AND –V – V SUPPL Y CURRENT – mA 31 2 1 5 1 804 96 –55/H11543C +25/H11543C +125/H11543C TPC 31. Supply Current vs. Supply Voltage TEMPERA TURE – /H11543C OFFSET VOL T AGE – mV –75 –50 125–25 0 25 50 75 100 TPC 34. Comparator Offset Voltage vs. Temperature SUPPL Y VOL T AGE +V AND –V – V INPUT RANGE OF LOGIC GROUND – V –14 46 9 1 2 1 8 15 –10 –18 –55/H11543C +125/H11543C ACCEPT ABLE GROUND PIN POTENTIAL IS BETWEEN SLIDE LINES. +25/H11543C +25/H11543C +125/H11543C TPC 29. Input Range of Logic Ground vs. Supply Voltage FREQUENCY – Hz REJECTION RA TIO – dB 100 010 100 1M 1k 10k 100k TA = 25/H11543C VIN = 0V CH = 1000pF CHANNEL A = 1 CHANNEL B = 0 POSITIVE SUPPL Y (+15V +1V SIN /H9275T) NEGA TIVE SUPPL Y (–15V +1V SIN /H9275) TPC 32. Hold Mode Power Supply Rejection vs. Frequency TEMPERA TURE – /H11543C 110 –75 –50 150–25 0 25 75 100 12550 100 90COMP ARA TOR IOS – nA TPC 35. Comparator IOS vs. Temperature LOGIC INPUT VOL T AGE – V LOGIC CURRENT – /H9262A –3–2 –15 01 2 34 LOGIC GROUND = 0V LOGIC 0 LOGIC 1 –55/H11543C +125/H11543C +25/H11543C TPC 30. Logic Input Current vs. Logic Input Voltage INPUT VOL T AGE – V INPUT BIAS CURRENT (EITHER INPUT) – /H9262A 3 –15 –10 15 –50 51 0 VS = /H1155015V TA = 25/H11543C OTHER INPUT A T +10V OTHER INPUT AT –10V OTHER INPUT A T 0V INPUT CURRENT MUST BE LIMITED TO LESS THAN 1mA TPC 33. Comparator Input Bias Current vs. Differential Input Voltage TEMPERA TURE – /H11543C COMP ARA TOR IB – nA 1200 200 –75 –50 150–25 0 25 75 100 12550 1000 800 600 400 TPC 36. Comparator IB vs. Temperature

REV. A PKD01 –10– SUPPL Y VOL T AGE +V AND –V – V OUTPUT RANGE OF COMP ARA TOR – V –18 46 91 2 1 51 8 –10 –14 –55/H11543C +25/H11543C +125/H11543C +25/H11543C +125/H11543C TPC 37. Output Swing of Com- parator vs. Supply Voltage IO – OUTPUT SINK CURRENT – mA 0.8 01 4 42 6 10 12 8 0.6 0.2 –0.2 0.4 1.0 VO – VOL T AGE OUTPUT – VDC –55/H11543C +125/H11543C +25/H11543C TPC 40. Comparator Output Voltage vs. Output Current and Temperature TIME – ns INPUT VOL T AGE – mV –50 300 500 100 200 250 150 OUTPUT VOL T AGE – V PULL-UP RESISTOR = 2k/H9024 TA = +25/H11543C TA = –55/H11543C TA = +125/H11543C TPC 38. Comparator Response Time vs. Temperature TIME – ns INPUT VOL T AGE – mV –50 300 500 100 200 250 150 OUTPUT VOL T AGE – V PULL-UP RESISTOR = 2k/H9024 TA = –55/H11543C TA = +125/H11543C TA = +25/H11543C TPC 41. Comparator Response Time vs. Temperature INPUT VOL T AGE – mV OUTPUT VOL T AGE – V VS = /H1155015V TA = 25/H11543C INVERTING INPUT = VIN NONINVERTING INPUT = 0V RL = 2k/H9024 TO 5V RL = 1k/H9024 TO 5V TPC 39. Comparator Transfer Characteristic

REV. A PKD01 –18– OUTLINE DIMENSIONS Dimensions shown in inches and (mm). 14-Lead Plastic DIP (PDIP) (N-14) PIN 1 0.795 (20.19) 0.725 (18.42) 0.280 (7.11) 0.240 (6.10) 0.100 (2.54) BSC SEATING PLANE 0.060 (1.52) MAX 0.022 (0.558) 0.014 (0.356) 0.160 (4.06) 0.115 (2.93) 0.070 (1.77) 0.045 (1.15) 0.130 (3.30) MIN 0.195 (4.95) 0.115 (2.93) 0.015 (0.381) 0.008 (0.204) 0.325 (8.25) 0.300 (7.62) 14-Lead Cerdip (Q-14) 0.310 (7.87) 0.220 (5.59) PIN 1 0.005 (0.13) MIN 0.098 (2.49) MAX 0.100 (2.54) BSC 15° 0.320 (8.13) 0.290 (7.37) 0.015 (0.38) 0.008 (0.20) SEATING PLANE 0.200 (5.08) MAX 0.785 (19.94) MAX 0.150 (3.81) MIN 0.200 (5.08) 0.125 (3.18) 0.023 (0.58) 0.014 (0.36) 0.070 (1.78) 0.030 (0.76) 0.060 (1.52) 0.015 (0.38) PRINTED IN U.S.A.