IR3477 IRF | Alldatasheet

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March 27, 2013 | V2.5 | PD976042 IR3477 15A Highly Integrated SupIRBuckTM

ORDERING INFORMATION

Package Tape & Reel Qty Part Number M 750 IR3477MTR1PBF M 4000 IR3477MTRPBF PIN DIAGRAM WC WC o PCBJ o JA /30 - = θ θ PBF – Lead Free TR – Tape and Reel M – Package Type 3477 ?YWW? xxxxx Site/Date/Marking Code Lot Code Pin 1 Identifier

March 27, 2013 | V2.5 | PD976043 IR3477 15A Highly Integrated SupIRBuckTM FUNCTIONAL BLOCK DIAGRAM Figure 3: IR3477 Functional Block Diagram

March 27, 2013 | V2.5 | PD976044 IR3477 15A Highly Integrated SupIRBuckTM TYPICAL APPLICATION VOUT TP7 TP10 EN VCC TP23 +Vsws TP24 +Vsws +Vins R12 open C26 open TP8 VOUTS TP21 -Vsws TP25 -Vin1s C27 open TP12 VSWS TP22 +Vsws VIN open open 330uF C10 47uF -Vout1s C11 open -Vdd2s -Vdd1s 1uF 1.33K 1.21K C12 0.1uFPGOOD C24 open ISET -Vout1s +Vdd2s Vout +Vdd1s +3.3V +Vin1s TP6 PGNDS TP14 +3.3V IR3477 3VCBP FCCM SS PGOOD FF GND1 FB GND NC1 ISET BOOT VIN VCC NC2 PGND PHASE EN 1uF VCC TP4 EN SW1 EN / FCCM TP17 PGND C20 0.1uF TP26 AGND open VSW C21 1uF TP11 PGOOD 1.0uH open C22 open TP1 VINS 7.50K 200K C13 open 22uF C16 open + C3 68uF TP2 VIN TP5 PGND C14 open C17 open C18 open TP16 VCC FB 10K C15 open open TP18 VOLTAGE SENSE +Vins +Vdd1s +Vdd2s +Vout1s +Vout2s -Vout2s -Vdd2s -Vout1s -Vins -Vdd1s -Vout1s TP9 +Vout1s 10K FCCM +Vin1s TP20 +Vin1s +3.3V C25 1uF +Vdd1s -Vdd1s R13 open +3.3V TP15 -Vout1s R14 open TP19 FB R11 open TP13 SS VSW +Vdd2s TP3 FCCM SS -Vdd2s 10K IR3477 C19 open -Vins PGND VOUT C23 open Figure 4: Demoboard Schematic for VOUT = 1.05V, FS = 300kHz DEMOBOARD BILL OF MATERIALS QTY REFERENCE DESIGNATOR VALUE DESCRIPTION MANUFACTURER PART NUMBER 4 C1, C21, C25, C4 1.00uF capacitor, X7R, 1.00uF, 25V, 0.1, 0603 Murata GRM188R71E105KA12D 1 C10 47uF capacitor, 47uF, 6.3V, 805 TDK C2012X5R0J476M 2 C12, C20 0.100uF capacitor, X7R, 0.100uF, 50V, 0.1, 603 TDK C1608X7R1H104K 1 C2 22.0uF capacitor, X5R, 22.0uF, 25V, 20%, 1206 TDK C3216X5R1E226M 1 C3 68uF capacitor, electrolytic, 86uF, 25V, 0.2, SMD Panasonic EEV‐FK1E680P 1 C9 330uF capacitor, 330uF, 2.5V, SMD Sanyo 2R5TPE330M9 1 L1 1.0uH inductor, ferrite, 1.0uH, 20A, 2.7mOhm, SMT Cyntec PIMB103E‐1R0MS‐39 3 R1, R2, R5 10.0K resistor, thick film, 10.0K, 1/10W, 0.01, 603 KOA RK73H1J1002F 1 R3 200K resistor, thick film, 200K, 1/10W, 0.01, 603 KOA RK73H1JLTD2003F 1 R4 7.50K resistor, thick film, 7.50K, 1/10W, 0.01, 603 KOA RK73H1JLTD7501F 1 R7 1.33K resistor, thick film, 1.33K, 1/10W, 0.01, 603 KOA RK73H1J1331F 1 R8 1.21K resistor, thick film, 1.21K, 1/10W, 0.01, 603 KOA RK73H1JLTD1211F

1 SW1 SPST switch, DIP, SPST, 2 position, SMT C&K Components SD02H0SK

1 U1 IR3477 5mm x 6mm QFN IRF IR3477MTRPBF

March 27, 2013 | V2.5 | PD976045 IR3477 15A Highly Integrated SupIRBuckTM PIN DESCRIPTIONS PIN # PIN NAME I/O LEVEL PIN DESCRIPTION 1 FCCM 3.3V Forced Continuous Conduction Mode (CCM). Ground this pin to enable diode emulation mode or discontinuous conduction mode (DCM). Pull this pin to 3.3V to operate in CCM under all load conditions. 2 ISET Connecting resistor to PHASE pin sets over current trip point. 3 PGOOD 5V Power good open drain output – pull up with a resistor to 3.3V 4, 17 GND Reference Bias return and signal reference. 5 FB 3.3V Inverting input to PWM comparator, OVP / PGOOD sense. 6 SS 3.3V Soft start/shutdown. This pin provides user programmable soft‐start function. Connect an external capacitor from this pin to GND to set the startup time of the output voltage. The converter can be shutdown by pulling this pin below 0.3V.

7 NC ‐ ‐

8 3VCBP 3.3V For internal LDO. Bypass with a 1.0µF capacitor to GND.

9 NC ‐ ‐

10 VCC 5V VCC input. Gate drive supply. A minimum of 1.0µF ceramic capacitor is required. 11 PGND Reference Power return. 12 PHASE VIN Phase node (or switching node) of MOSFET half bridge. 13 VIN VIN Input voltage for the system. 14 BOOT VIN + VCC Bootstrapped gate drive supply – connect a capacitor to PHASE. 15 FF VIN Input voltage feed forward – sets on‐time with a resistor to VIN. 16 EN 5V Enable pin to turn on and off the device. Use two external resistors to set the turn on threshold (see Electrical Specifications) for input voltage monitoring.

March 27, 2013 | V2.5 | PD976046 IR3477 15A Highly Integrated SupIRBuckTM ABSOLUTE MAXIMUM RATINGS Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications are not implied. VIN, FF ‐0.3V to 30V VCC, PGOOD, EN ‐ 0.3V to 8V BOOT ‐0.3V to 38V PHASE ‐ 0.3V to 30V (DC), ‐5V (100ns) BOOT to PHASE ‐0.3V to 8V ISET ‐ 0.3V to 30V, 30mA PGND to GND ‐0.3V to +0.3V All other pins ‐ 0.3V to 3.9V Storage Temperature Range ‐65°C to 150°C Junction Temperature Range ‐ 40°C to 150°C ESD Classification JEDEC Class 1C Moisture Sensitivity Level JEDEC Level 2 @ 260°C (Note 2)

March 27, 2013 | V2.5 | PD976047 IR3477 15A Highly Integrated SupIRBuckTM ELECTRICAL SPECIFICATIONS RECOMMENDED OPERATING CONDITIONS FOR RELIABLE OPERATION WITH MARGIN SYMBOL MIN MAX UNITS Recommended VIN Range VIN 3 27* V Recommended VCC Range VCC 4.5 5.5 Recommended Output Voltage Range VOUT 0.5 12 Recommended Output Current Range IOUT 0 15 A Recommended Switching Frequency FS N/A 750 kHz Recommended Operating Junction Temperature TJ ‐ 40 125 °C * PHASE pin must not exceed 30V.

ELECTRICAL CHARACTERISTICS

Unless otherwise specified, these specifications apply over VIN = 12V, 4.5V < VCC < 5.5V, 0°C ≤ TJ ≤ 125°C. PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNIT Control Loop Reference Accuracy VREF VFB = 0.5V 0.495 0.5 0.505 V On‐Time Accuracy RFF = 180K, TJ = 65°C 280 300 320 ns Min. Off Time 500 580 ns Soft‐Start Current EN = High 8 10 12 µA DCM Comparator Offset Measure at VPHASE ‐ 4.5 ‐ 2.5 0 mV Feedback Input Current VFB = 0.5V, TA = 25°C, Note 1 0.01 0.2 µA Supply Current VCC Supply Current (standby) EN = Low, No Switching 23 µA VCC Supply Current (dynamic) EN = High, FS = 300kHz 9.7 mA FF Shutdown Current EN = Low, RFF = 180K 2 µA Forced Continuous Conduction Mode (FCCM) FCCM Start Threshold 2 V FCCM Stop Threshold 0.6 V Gate Drive Deadtime Monitor body diode conduction on PHASE pin, Note 1 5 30 ns Bootstrap PFET Forward Voltage I(BOOT) = 10mA 300 mV Upper MOSFET Static Drain‐to‐Source On‐Resistance VCC = 5V, ID = 12A, TJ = 25°C 14.5 20 mΩ Lower MOSFET Static Drain‐to‐Source On‐Resistance VCC = 5V, ID = 12A, TJ = 25°C 6 7.5 mΩ

March 27, 2013 | V2.5 | PD976048 IR3477 15A Highly Integrated SupIRBuckTM PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNIT Fault Protection ISET Pin Output Current On the basis of 25°C 17 19 21 µA ISET Pin Output Current Temperature Coefficient On the basis of 25°C, Note 1 4400 ppm/ Under Voltage Threshold Falling VFB & Monitor PGOOD 0.37 0.4 0.43 V Under Voltage Hysteresis Rising VFB, Note 1 7.5 mV Over Voltage Threshold Rising VFB & Monitor PGOOD 0.586 0.625 0.655 V Over Voltage Hysteresis Falling VFB, Note 1 7.5 mV VCC Turn‐on Threshold ‐40°C to 125°C 3.9 4.2 4.5 V VCC Turn‐off Threshold 3.6 3.9 4.2 V VCC Threshold Hysteresis 300 mV EN Rising Threshold ‐ 40°C to 125°C 1.1 1.25 1.45 V EN Hysteresis 400 mV EN Input Current EN = 3.3V 15 µA PGOOD Pull Down Resistance 25 50 Ω PGOOD Delay Threshold VSS 1 V Thermal Shutdown Threshold Note 1 125 140 °C Thermal Shutdown Threshold Hysteresis Note 1 20 °C Note: 1. Guaranteed by design but not tested in production 2. Upgrade to industrial/MSL2 level applies from date codes 1227 (marking explained on application note AN1132 page 2). Products with prior date code of 1227 are qualified with MSL3 for Consumer Market.

March 27, 2013 | V2.5 | PD9760412 IR3477 15A Highly Integrated SupIRBuckTM THEORY OF OPERATION PWM COMPARATOR The PWM comparator initiates a SET signal (PWM pulse) when the FB pin falls below the reference (VREF) or the soft start (SS) voltage. ON‐TIME GENERATOR The PWM on‐time duration is programmed with an external resistor (RFF) from the input supply (VIN) to the FF pin. The simplified equation for RFF is shown in equation 1. The FF pin is held to an internal reference after EN goes HIGH. A copy of the current in RFF charges a timing capacitor, which sets the on‐time duration, as shown in equation 2. CONTROL LOGIC The control logic monitors input power sources, sequences the converter through the soft‐start and protective modes, and initiates an internal RUN signal when all conditions are met. VCC and 3VCBP pins are continuously monitored, and the IR3477 will be disabled if the voltage of either pin drops below the falling thresholds. EN_DELAY will become HIGH when VCC and 3VCBP are in the normal operating range and the EN pin = HIGH. SOFT START With EN = HIGH, an internal 10µA current source charges the external capacitor (CSS) on the SS pin to set the output voltage slew rate during the soft start interval. The soft start time (tSS) can be calculated from equation 3. The feedback voltage tracks the SS pin until SS reaches the 0.5V reference voltage (Vref), then feedback is regulated to Vref. C SS will continue to be charged, and when SS pin reaches VSS (see Electrical Specification), SS_DELAY goes HIGH. With EN_DELAY = LOW, the capacitor voltage and SS pin is held to the FB pin voltage. A normal startup sequence is shown in Figure 23. PGOOD The PGOOD pin is open drain and it needs to be externally pulled high. High state indicates that output is in regulation. The PGOOD logic monitors EN_DELAY, SS_DELAY, and under/over voltage fault signals. PGOOD is released only when EN_DELAY and SS_DELAY = HIGH and output voltage is within the OV and UV thresholds. PRE‐BIAS STARTUP IR3477 is able to start up into pre‐charged output, which prevents oscillation and disturbances of the output voltage. With constant on‐time control, the output voltage is compared with the soft start voltage (SS) or Vref, depending on which one is lower, and will not start switching unless the output voltage drops below the reference. This scheme prevents discharge of a pre‐biased output voltage. SHUTDOWN The IR3477 will shutdown if VCC is below its UVLO limit. The IR3477 can be shutdown by pulling the EN pin below its lower threshold. Alternatively, the output can be shutdown by pulling the soft start pin below 0.3V. Figure 23: Normal Startup (1) F201 VR SW OUT FF ⋅⋅= pFV (2) V 201RT IN FF ON pFV ⋅⋅= (3) A10 5.0 μ VCt SS SS

March 27, 2013 | V2.5 | PD9760414 IR3477 15A Highly Integrated SupIRBuckTM GATE DRIVE LOGIC The gate drive logic features adaptive dead time, diode emulation, and a minimum lower gate interval. An adaptive dead time prevents the simultaneous conduction of the upper and lower MOSFETs. The lower gate voltage must be below approximately 1V after PWM goes HIGH before the upper MOSFET can be gated on. Also, the differential voltage between the upper gate and PHASE must be below approximately 1V after PWM goes LOW before the lower MOSFET can be gated on. The upper MOSFET is gated on after the adaptive delay for PWM = HIGH and the lower MOSFET is gated on after the adaptive delay for PWM = LOW. When FCCM = LOW, the lower MOSFET is driven ‘off’ when the ZCROSS signal indicates that the inductor current is about to reverse direction. The ZCROSS comparator monitors the PHASE voltage to determine when to turn off the lower MOSFET. The lower MOSFET stays ‘off’ until the next PWM falling edge. When the lower peak of the inductor current is above zero, IR3477 operates in continuous conduction mode. The continuous conduction mode can also be selected for all load current levels by pulling FCCM to HIGH. Whenever the upper MOSFET is turned ‘off’, it stays ‘off’ for the Min Off Time denoted in the Electrical Specifications. This minimum duration allows time to recharge the bootstrap capacitor and allows the over current monitor to sample the PHASE voltage. COMPONENT SELECTION Selection of components for the converter is an iterative process which involves meeting the specifications and tradeoffs between performance and cost. The following sections will guide one through the process. Inductor Selection Inductor selection involves meeting the steady state output ripple requirement, minimizing the switching loss of the upper MOSFET, meeting transient response specifications and minimizing the output capacitance. The output voltage includes a DC voltage and a small AC ripple component due to the low pass filter which has incomplete attenuation of the switching harmonics. Neglecting the inductance in series with the output capacitor, the magnitude of the AC voltage ripple is determined by the total inductor ripple current flowing through the total equivalent series resistance (ESR) of the output capacitor bank. One can use equation 5 to find the required inductance. ΔI is defined as shown in Figure 27. The main advantage of small inductance is increased inductor current slew rate during a load transient, which leads to a smaller output capacitance requirement as discussed in the Output Capacitor Selection section. The drawback of using smaller inductances is increased switching power loss in the upper MOSFET, which reduces the system efficiency and increases the thermal dissipation. Figure 27: Typical Input Current Waveform Input Capacitor Selection The main function of the input capacitor bank is to provide the input ripple current and fast slew rate current during the load current step up. The input capacitor bank must have adequate ripple current carrying capability to handle the total RMS current. Figure 27 shows a typical input current. Equation 6 shows the RMS input current. The RMS input current contains the DC load current and the inductor ripple current. As shown in equation 5, the inductor ripple current is unrelated to the load current. The maximum RMS input current occurs at the maximum output current. The maximum power dissipation in the input capacitor equals the square of the maximum RMS input current times the input capacitor’s total ESR. The voltage rating of the input capacitor needs to be greater than the maximum input voltage because of high frequency ringing at the phase node. The typical percentage is 25%. (6) I ΔI 11FsTI dttfTs OUT ONOUT Ts 2IN_RMS ⋅⋅= ∫ ( ) (5) L2 VVTΔI OUTINON

March 27, 2013 | V2.5 | PD9760416 IR3477 15A Highly Integrated SupIRBuckTM DESIGN EXAMPLE DESIGN CRITERIA

  • Input Voltage, VIN = 6V to 21V
  • Output Voltage, VOUT = 1.25V
  • Switching Frequency, Fs = 400kHz
  • Inductor Ripple Current, 2ΔI = 3A
  • Maximum Output Current, IOUT = 12A
  • Over Current Trip, IOC = 18A
  • Current Transient Step Size = 5A
  • Overshoot Allowance, VOS = VOUT + 50mV
  • Undershoot Allowance, VDROP = 50mV Find RFF: Pick a standard value 158 kΩ, 1% resistor. Find RISET: Pick a 7.15kΩ, 1% standard resistor. Find a resistive voltage divider for VOUT = 1.25V: R2 = 1.33kΩ, R1 = 1.96 kΩ, both 1% standard resistors. Choose the soft start capacitor: Once the soft start time has chosen, such as 1000us to reach to the reference voltage, a 22nF for CSS is used to meet 1000us. Choose an inductor to meet the design specification: Choose the inductor with the lowest DCR and AC power loss as possible to increase the overall system efficiency. For instance, choose a PIMB103E‐1R0MS‐39 manufactured by CYNTEC. The inductance of this part is 1µH and has 2.7mΩ DCR. Ripple current needs to be recalculated using the chosen inductor. Choose an input capacitor: A Panasonic 10µF (ECJ3YB1E106M) accommodates 6 Arms of ripple current at 300kHz. Due to the chemistry of multilayer ceramic capacitors, the capacitance varies over temperature and operating voltage, both AC and DC. One 10µF capacitor is recommended. In a practical solution, one 1µF capacitor is required along with 10µF. The purpose of the 1µF capacitor is to suppress the switching noise and deliver high frequency current. Choose an output capacitor: To meet the undershoot and overshoot specification, equations 7b and 8 will be used to calculate the minimum output capacitance. As a result, 200μF will be needed for 5A load removal. To meet the stability requirement, choose an output capacitor with ESR larger than 6mΩ. Combine those two requirements, one can choose a set of output capacitors from manufactures such as SP‐Cap (Specialty Polymer Capacitor) from Panasonic or POSCAP from Sanyo. A 220μF (EEFSL0D221R) from Panasonic with 9mΩ ESR will meet both requirements. If an all ceramic output capacitor solution is desired, the external slope injection circuit composed of R6, C13, and C14 is required as explained in the Stability Considerations section. In this design example, we can choose C14 = 1nF and C13 = 100nF. To calculate the value of R6 with PIMB103E‐1R0MS‐39 as our inductor: Pick a standard value for R6 = 3.74kΩ. k 156 400k201 1.25RFF Ω=⋅⋅= HzpFV V Ω=Ω= 7.1k 91 18 7.5mR ISET A A μ V0.5 V RR RV OUT FB =⋅+= H HzAV VVV μ1.0 400k321 1.25-211.25 FΔI2V VVVL sIN OUTINOUT ( ) AHzHV VVVI 3 400k121 1.25-211.252Δ =⋅⋅ ⋅= μ AA A V VA 9.221 5.1 1121 1.2521I IN_RMS =⎟ ⎛⋅+⋅⋅= ⋅Ω= k nFm H CDCR LR 7.3 1007.2 μ

March 27, 2013 | V2.5 | PD9760418 IR3477 15A Highly Integrated SupIRBuckTM PCB METAL AND COMPONENT PLACEMENT

  • Lead lands (the 13 IC pins) width should be equal to nominal part lead width. The minimum lead to lead spacing should be ≥ 0.2mm to minimize shorting.
  • Lead land length should be equal to maximum part lead length + 0.3 mm outboard extension. The outboard extension ensures a large toe fillet that can be easily inspected.
  • Pad lands (the 4 big pads) length and width should be equal to maximum part pad length and width. However, the minimum metal to metal spacing should be no less than; 0.17mm for 2 oz. Copper or no less than 0.1mm for 1 oz. Copper or no less than 0.23mm for 3 oz. Copper. Figure 31: Metal and Component Placement * Contact International Rectifier to receive an electronic PCB Library file in your preferred format

March 27, 2013 | V2.5 | PD9760419 IR3477 15A Highly Integrated SupIRBuckTM SOLDER RESIST

  • It is recommended that the lead lands are Non Solder Mask Defined (NSMD). The solder resist should be pulled away from the metal lead lands by a minimum of 0.025mm to ensure NSMD pads.
  • The land pad should be Solder Mask Defined (SMD), with a minimum overlap of the solder resist onto the copper of 0.05mm to accommodate solder resist misalignment.
  • Ensure that the solder resist in between the lead lands and the pad land is ≥ 0.15mm due to the high aspect ratio of the solder resist strip separating the lead lands from the pad land. Figure 32: Solder Resist * Contact International Rectifier to receive an electronic PCB Library file in your preferred format

March 27, 2013 | V2.5 | PD9760420 IR3477 15A Highly Integrated SupIRBuckTM STENCIL DESIGN

  • The Stencil apertures for the lead lands should be approximately 80% of the area of the lead lads. Reducing the amount of solder deposited will minimize the occurrences of lead shorts. If too much solder is deposited on the center pad the part will float and the lead lands will open.
  • The maximum length and width of the land pad stencil aperture should be equal to the solder resist opening minus an annular 0.2mm pull back in order to decrease the risk of shorting the center land to the lead lands when the part is pushed into the solder paste. Figure 33: Stencil Design * Contact International Rectifier to receive an electronic PCB Library file in your preferred format

March 27, 2013 | V2.5 | PD9760421 IR3477 15A Highly Integrated SupIRBuckTM

PACKAGE INFORMATION

Figure 34: Package Dimensions Data and specifications subject to change without notice. This product has been designed and qualified for the Industrial Market (Note2). Qualification Standards can be found on IR’s Web site. IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105 TAC Fax: (310) 252-7903 Visit us at www.irf.com for sales contact information www.irf.com