PI6ULS5V9511A

PI6ULS5V9511A

Document overview

• Manufacturer or author: Diodes Incorporated
• PDF pages: 17

Technical content

PI6ULS5V9511A www.diodes.com December 2018 Document Number 40558 Rev 3 - 2 2 © Diodes Incorporated PI6ULS5V9511A Block Diagram Figure 3: Block Diagram PI6ULS5V9511A

PI6ULS5V9511A www.diodes.com December 2018 Document Number 40558 Rev 3 - 2 3 © Diodes Incorporated PI6ULS5V9511A Maximum Ratings Recommended Operating Conditions VCC = 2.7V to 5.5V; GND = 0V; Tamb=-40°C to +85°C; unless otherwise specified Symbol Parameter CONDITIONS Min. TYP Max. Unit VCC [1] Supply Voltage Port B — 2.7 — 5.5 V ICC Supply Current VCC = 5.5V; VSDAIN = VSCLIN = 0V — 2.8 6 mA ICC(sd) Shut-Down Mode Supply Current VENABLE = 0V; All Other pins at VCC or GND — 0.1 — µA Note: 1. This specification applies over the full operating temperature range.

Electrical Characteristics

VCC = 2.7 V to 5.5 V; GND = 0 V; Tamb=-40°C to +85°C; unless otherwise specified Parameter Description Test Conditions Min Typ. Max Unit Startup Circuitry Vpch [1] Pre-Charge Voltage SDA, SCL Floating 0.8 1.1 1.2 V VIH(ENABLE) HIGH-Level Input Voltage on pin ENABLE — — 0.5 × VCC 0.7 × VCC V VIL(ENABLE) LOW-Level Input Voltage on pin ENABLE — 0.3 × VCC 0.5 × VCC — V II(ENABLE) Input Current on pin ENABLE VENABLE = 0V to VCC — ±0.1 ±1 µA ten [2] Enable Time — — 110 — µs tidle(READY) [1] Bus Idle Time to READY Active — 50 105 200 µs tdis(EN-RDY) Disable Time (ENABLE to READY) — — 30 — ns tstp(READY) [3] SDAIN to READY Delay After STOP — — 1.2 — µs tREADY [3] SCLOUT/SDAOUT to READY delay — — 0.8 — µs ILZ(READY) Off-State Leakage Current on pin READY VENABLE = VCC — ±0.3 — µA Ci(ENABLE) [4] Input Capacitance on pin ENABLE VI = VCC or GND — 1.9 4.0 pF Co(READY) [4] LOW-Level Output Voltage VI = VCC or GND — 2.5 4.0 pF VOL(READY) [1] LOW-Level Output Voltage on pin READY Ipu = 3mA; VENABLE = VCC — — 0.4 V Note: 1. This specification applies over the full operating temperature range. 2. The enable time can slow considerably for some parts when temperature is < −20 °C. 3. Delays that can occur after ENABLE and/or idle times have passed. 4. Guaranteed by design, not production tested. 5. Itrt(pu) varies with temperature and VCC voltage. 6. Input pullup voltage must not exceed power supply voltage in operating mode because the rise time accelerat or will clamp the voltage to the positive supply rail. 7. The connection circuitry always regulates its output to a higher voltage than its input. 8. Force VSDAIN = VSCLIN = 0.1V, tie SDAOUT and SCLOUT through 10kΩ resistor to VCC and measure the SDAOUT and SCLOUT output. Note: Stresses greater than those listed under MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for exte nded periods may affect reliability.

PI6ULS5V9511A www.diodes.com December 2018 Document Number 40558 Rev 3 - 2 4 © Diodes Incorporated PI6ULS5V9511A Electrical Characteristics (continued) VCC = 2.7 V to 5.5 V; GND = 0 V; Tamb=-40°C to +85°C; unless otherwise specified Parameter Description Test Conditions Min Typ. Max Unit Rise Time Accelerators Itrt(pu) [5][6] Transient Boosted Pullup Current Positive Transition on SDA, SCL; VCC = 2.7V; Slew Rate = 1.25V/µs 1 2 — V Input-Output Connection Voffset [1][7][8] Offset Voltage 10kΩ to VCC on SDA, SCL; VCC = 3.3V — 110 175 mV tPLH LOW to HIGH Propagation Delay SCL to SCL and SDA to SDA; 10kΩ to VCC; CL = 100pF Each Side — 0 — ns tPHL HIGH to LOW Propagation Delay SCL to SCL and SDA to SDA; 10kΩ to VCC; CL = 100pF Each Side — 70 — ns Ci(SCL/SDA) [4] SCL and SDA Input Capacitance — — 5 7 pF VOL [1] LOW-Level Output Voltage VI = 0V; SDAn, SCLn pins; Isink = 3mA; VCC = 2.7V 0 — 0.4 V ILI Input Leakage Current SDAn, SCLn pins; VCC = 5.5V -1 — +1 µA Note: 1. This specification applies over the full operating temperature range. 2. The enable time can slow considerably for some parts when temperature is < −20 °C. 3. Delays can occur after ENABLE and/or idle times have passed. 4. Guaranteed by design, not production tested. 5. Itrt(pu) varies with temperature and VCC voltage. 6. Input pullup voltage must not exceed power supply voltage in operating mode because the rise time accelerator will clamp the voltage to the positive supply rail. 7. The connection circuitry always regulates its output to a higher voltage than its input. 8. Force VSDAIN = VSCLIN = 0.1V, tie SDAOUT and SCLOUT through 10kΩ resistor to VCC and measure the SDAOUT and SCLOUT output.

1. Data taken using a 1kΩ pullup resistor and 50pF load notes

Figure 4. Timing for ten, tidle(READY) and tdis

PI6ULS5V9511A www.diodes.com December 2018 Document Number 40558 Rev 3 - 2 7 © Diodes Incorporated PI6ULS5V9511A Function Description Startup An undervoltage/initialization circuit holds the parts in a disconnected state , which presents high- impedance to all SDA and SCL pins during power -up. A LOW on the ENABLE pin also forces the parts into the low -current disconnected state when the ICC is essentially zero. When the power supply is brought up, and the ENABLE is HIGH, or when the part is powered and the ENABLE is taken from LOW to HIGH , the device enters an initialization state where the internal references are stabilized , and the pre-charge circuit is enabled. At the end of the initialization state , the Stop Bit And Bus Idle detect circuit is enabled. SDAIN is connected to SDAOUT , and SCLIN is connected to SCLOUT when the ENABLE pin is HIGH long enough to complete the initialization state (ten) and remains HIGH while all of the SDA and SCL pins are HIGH for the bus idle time or when all pins are HIGH , and a STOP condition is on the SDAIN and SCLIN pins. The 1V pre-charge circuitry is activated during the initializatio n and is deactivated when the connection is made. The pre -charge circuitry pulls up the SDA and SCL pins to 1 V through individual 100 kΩ nominal resistors. This pre -charges the pins to 1 V to minimize the worst-case disturbances that result from inserting a card into the backplane where the backplane and the card are at opposite logic levels. Connect Circuitry Once the connection circuitry is activated, the behavior of SDAIN and SDAOUT as well as SCLIN and SCLOUT become identical with each pin acting as a bidirectional buffer that isolates the input capacitance from the output bus capacitance while communicating the logic levels. A LOW forced on either SDAIN or SDAOUT cause s the other pin to be driven to a LOW by the part. The same is also true for the SCL pins. Noise between 0.7VCC and VCC is generally ignored because a falling edge is only recognized when it falls below 0.7VCC with a slew rate of at least 1.25 V/µs. When a falling edge is on one pin, the other pin in the pair turns on a pull down driver that is referenced to a small voltage above the falling pin. The driver pull s the pin down at a slew rate initially determined by the driver and the load because the driver does not start until the first falling pin is below 0.7VCC. The first falling pin can have a fast or slow slew rate . If the falling pin is faster than the pull down slew rate , the initial pull down rate continue s. If the first falling pin has a slow slew rate , the second pin is pulled down at its initial slew rate until it is just above the first pin ’s voltage then both pins continue down at the slew rate of the first pin. When both sides are LOW, they remain LOW until all of the external drivers stop driving LOWs. If both sides are driven LOW to the same value —for instance, 10 mV —by external drivers, which is the case for clock stretching and is typically the case for acknowledge, one side external driver stops driving that pin and rises until the internal driver pulls it down to the offset voltage. When the last external driver stops driving a LOW, th e pin rises up and settle s out just above the other pin as both rise together with a slew rate determined by the internal slew rate control and the RC time constant. As long as the slew rate is at least 1.25V/µs when the pin voltage exceeds 0.6 V for the PI6ULS5V9511A, the rise -time accelerator’s circuits turn on, and the pull down driver turns off.

PI6ULS5V9511A www.diodes.com December 2018 Document Number 40558 Rev 3 - 2 8 © Diodes Incorporated PI6ULS5V9511A Maximum Number of Devices in Series Each buffer adds about 0.1 V dynamic level offset at 25 °C with the offset larger at higher temperatures. Maximum offset (V offset) is 0.150V with a 10kΩ pullup resistor. The LOW level at the signal origination end (master) is dependent upon the load , and the only specification point is that the I2C -bus specification of 3mA produces VOL < 0.4V; although if lightly loaded, the VOL may be ~0.1V. Assuming VOL = 0.1V and V offset = 0.1V, the level after four buffers is 0.5 V, which is only about 0.1 V below the threshold of the rising edge accelerator (about 0.6 V). With great care a system with four buffers can work, but as the V OL moves up from 0.1 V, noise or bounces on the line result s in firing the rising edge accelerator thus introducing false clock edges. Generally it is recommended to limit the number of buffers in series to two and to keep the load light to minimize the offset. Figure 8: System with Three Buffers Connected to Common Node Consider a system with three buffers connected to a common node and where communication between the Master and Slave B are connected at either end of buffer A and buffer B in series as shown in Figure 8. Consider if the VOL at the input of buffer A is 0.3 V, and the VOL of Slave B (when acknowledging) is 0.4 V with the direction changing from Master to Slave B and then from Slave B to Master. Before the direction change, VIL at the input of buffer A is 0.3V, and its output, the common node, is ~0.4V. The output When the Master pull down turns off, the input of buffer A rises and so does its output, the common node, because it is the only part driving the node. The common node rise s to 0.5 V before buffer B’s output turns on ; if the pull up is strong , the node can bounce. If the bounce goes above the threshold for the rising edge accelerator ~0.6 V, the accelerators on both buffer A and buffer C fire contending with the output of buffer B. The node on the input of buffer A will go HIGH a s will the input node of buffer C. After the common node voltage is stable for a while , the rising edge accelerators turn off, and the common node return s to ~0.5V because the buffer B is still on. The voltage at both the Master and Slave C node s fall to ~0.6V until Slave B turns off. This does not cause a failure on the data line as long as the return to 0.5 V on the common node (~0.6 V at the Master and Slave C) occu rs before the data setup time. If this were the SCL line, the parts on buffer A and buffer C can detect a false clock rather than a stretched clock, which causes a system error. Propagation Delays The delay for a rising edge is determined by the combined pull up current from the bus resistors and the rise time accelerator current source and the effective capacitance on the lines. If the pull up currents are the same, any difference in rise time is directly proportional to the difference in cap acitance between the two sides. The t PLH can be negative if the output capacitance is less than the input capacitance and is positive if the output capacitance is larger than the input capacitance when the currents are the same. The tPHL is never negative because the output does not start to fall until the input is below 0.7VCC, the output turn on has a non - zero delay, and the output has a limited maximum slew rate . Even if the input slew rate is slow enough that the outp ut catches up, it still lags the falling voltage of the input by the offset voltage. The maximum t PHL occurs when the input is driven LOW with zero delay, and the output is still limited by its turn -on delay and the falling edge slew rate. The output falling edge slew rate is a function of the internal maximum slew rate , which is a function of temperature, VCC , and process as well as the load current and the load capacitance.

PI6ULS5V9511A www.diodes.com December 2018 Document Number 40558 Rev 3 - 2 9 © Diodes Incorporated PI6ULS5V9511A Rise Time Accelerators During positive bus transitions , a 2mA current source switches on to quickly slew the SDA and SCL lines HIGH once the input level of 0.6 V for the PI6ULS5V9511A is exceeded. The rising edge rate must be at least 1.25 V/µs to guarantee turnon of the accelerators. The built-in ΔV/Δt rise-time accelerators on all SDA and SCL lines require the bus pullup voltage and supply voltage (VCC) to be the same. READY Digital Output This pin provides a digital flag , which is LOW when either ENABLE is LOW , or the start- up sequence described earlier in this section is not complete. READY goes HIGH when ENABLE is HIGH , and startup is complete. The pin is driven by an open- drain pulldown capable of sinking 3mA while holding 0.4V on the pin. Connect a resistor of 10kΩ to VCC to provide the pullup. ENABLE Low-Current Disable Grounding the ENABLE pin disconnects the backplane side from the card side, disables the rise -time accelerators, drives READY LOW, disables the bus pre- charge circuitry, and puts the part in a low -current state. When the pin voltage drives all the way to VCC, the part waits for data transactions on both the backplane and card sides to be complete before reconnecting the two sides. Resistor Pullup Value Selection In order to activate the boost pullup currents during rising edges , the system pull up resistors must be strong enough to provide a positive slew rate of 1.25V/µs on the SDA and SCL pins.. Choose a maximum resistor value using the following equation. 𝑅𝑅 ≤ 800 × 103(𝑉𝑉𝑉𝑉𝑉𝑉(min) −0.6 C ) Where:

• R is the pullup resistor value in Ω
• VCC(min) is the minimum VCC voltage in V
• C is the equivalent bus capacitance in pF) In addition regardless of the bus capacitance, always choose R ≤ 65.7 kΩ for VCC = 5.5V maximum and R ≤ 45kΩ for VCC = 3.6V maximum. The start up circuitry requires logic HIGH voltages on SDAOUT and SCLOUT to connect the backplane to the card . These pullup values are required to overcome the pre-charge voltage.

Figure 15. Typical A

PI6ULS5V9511A www.diodes.com December 2018 Document Number 40558 Rev 3 - 2 14 © Diodes Incorporated PI6ULS5V9511A Packaging Mechanical MSOP-8 (U)

PI6ULS5V9511A www.diodes.com December 2018 Document Number 40558 Rev 3 - 2 15 © Diodes Incorporated PI6ULS5V9511A SOIC-8 (W)

PI6ULS5V9511A www.diodes.com December 2018 Document Number 40558 Rev 3 - 2 16 © Diodes Incorporated PI6ULS5V9511A UDFN-8 (ZW) For latest package information: Please see http://www.diodes.com/design/support/packaging/pericom-packaging/packaging-mechanicals-and-thermal-characteristics/.

Ordering Information

Part Numbers Package Code Package PI6ULS5V9511AUEX U 8-Pin, Mini Small Outline Package (MSOP) PI6ULS5V9511AWEX W 8-Pin, 150mil-Wide (SOIC) PI6ULS5V9511AZWEX ZW 8-Pin, 2x3 (UDFN) Notes: 1. No purposely added lead. Fully EU Directive 2002/95/EC (RoHS), 2011/65/EU (RoHS 2) & 2015/863/EU (RoHS 3) compliant. 2. See https://www.diodes.com/quality/lead-free/ for more information about Diodes Incorporated’s definitions of Halogen- and Antimony-free, "Green" and Lead-free. 3. Halogen- and Antimony-free "Green” products are defined as those which contain <900ppm bromine, <900ppm chlorine (<1500ppm total Br + Cl) and <1000ppm antimony compounds. 4. E = Pb-free and Green 5. X suffix = Tape/Reel

PI6ULS5V9511A www.diodes.com December 2018 Document Number 40558 Rev 3 - 2 17 © Diodes Incorporated PI6ULS5V9511A IMPORTANT NOTICE DIODES INCORPORATED MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARDS TO THIS DOCUMENT, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE (AND THEIR EQUIVALENTS UNDER THE LAWS OF ANY JURISDICTION). Diodes Incorporated and its subsidiaries reserve the right to make modifications, enhancements, improvements, corrections or other c hanges without further notice to this document and any product described herein. Diodes Incorporated does not assume any liability arising out of the application or use of this document or any product described herein; neither does Diodes Incorporated convey any license under its patent or trademark rights, nor the rights of others. Any Customer or user of this document or products described herein in such applications shall assume all risks of such use and will agree to hold Diodes Incorporated and all the companies whose products are repres ented on Diodes Incorporated website, harmless against all damages. Diodes Incorporated does not warrant or accept any liability whatsoever in respect of any products purchased through unauthorized sales channel. Should Customers purchase or use Diodes Incorporated products for any unintended or unauthorized application, Customers shall indemnify and hold Diodes Incorporated and its representatives harmless against all claims, damages, expenses, and attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized application. Products described herein may be covered by one or more United States, international or foreign patents pending. Product names and markings noted herein may also be covered by one or more United States, international or foreign trademarks. This document is written in English but may be translated into multiple languages for reference. Only the English version of t his document is the final and determinative format released by Diodes Incorporated. LIFE SUPPORT Diodes Incorporated products are specifically not authorized for use as critical components in life support devices or systems without the express written app roval of the Chief Executive Officer of Diodes Incorporated. As used herein: A. Life support devices or systems are devices or s ystems which: 1. are intended to implant into the body, or 2. support or sustain life and whose failure to perform when properly used in accordance with instructions for use provided i n the labeling can be reasonably expected to result in significant injury to the user. B. A critical component is any component in a life support device or system whose failure to perform can be reasonably expe cted to cause the failure of the life support device or to affect its safety or effectiveness. Customers represent that they have all necessary expertise in the safety and regulatory ramifications of their life support devices or s ystems, and acknowledge and agree that they are solely responsible for all legal, regulatory and safety-related requirements concerning their products and any use of Diodes Incorporated products in such safety- critical, life support devices or systems, notwithstanding any devices- or systems-related information or support that may be provided by Diodes Incorporated. Further, Customers must fully indemnify Diodes Incorporated and its representatives against any damages arising out of the use of Diodes Incorporated products in suc h safety-critical, life support devices or systems. Copyright © 2016, Diodes Incorporated www.diodes.com