PI6C184 ANALOGICTECH | Alldatasheet

Document overview

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Technical content

Features

  • High-speed, low-noise, non-inverting, 1-13 buffer
  • Supports up to four SDRAM DIMMs
  • Low skew (< 250ps) between any two output clocks
  • I2C Serial Configuration interface
  • Multiple VDD, VSS pins for noise reduction
  • 3.3V power supply voltage
  • Separate Hi-Z pin for testing
  • Packaging (Pb-free & Green available): - 28-pin SSOP (H) 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 Precision 1-13 Clock Buffer PI6C184

Precision 1-13 Clock Buffer PS8320D 10/14/04 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 Pin Description I2C Address Assignment Serial Configuration Map Byte0: SDRAM Active/Inactive Register (1 = enable, 0 = disable) Note: Inactive means outputs are held LOW and are disabled from switching n i P l o b m y S e p y T -tit n a u Q y n o it p ir c s e D M A R D S tu p tu o k c olc ety B M A R D S M A R D S tu p tu o k c olc ety B M A R D S M A R D S tu p tu o k c olc ety B M A R D S N I F U B r eff u b r o f tu p n I A T A D S O I r o f ni p ata D a s a H rtiu c ric C r o tsis e r p u -llu p la n r etn I k K L C S O I r o f ni p k c ol C p u -llu p la n r etn I k a s a H rtiu c ric C r o tsis e r V D D r e w o P r eff u b M A R D S r o f yl p p u s r e w o p V V S S d n u o r G sr eff u B M A R D S r o f d n u o r G ti B n i P n oit p ir c s e D ti B vitc a n I/e vitc A M A R D S ti B vitc a n I/e vitc A M A R D S ti B vitc a n I/e vitc A M A R D S ti B vitc a n I/e vitc A M A R D S ti B vitc a n I/e vitc A M A R D S ti B vitc a n I/e vitc A M A R D S ti B vitc a n I/e vitc A M A R D S ti B vitc a n I/e vitc A M A R D S A A A A A A A W R

Precision 1-13 Clock Buffer PS8320D 10/14/04 123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123 123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123 Byte1: SDRAM Active/Inactive Register (1 = enable, 0 = disable) Byte2: Optional Register for Possible Future Requirements (1 = enable, 0 = disable) 2-Wire I2C Control The I2C interface permits individual enable/disable of each clock output and test mode enable. The PI6C184 is a slave receiver device. It can not be read back. Sub addressing is not supported. All preceding bytes must be sent in order to change one of the control bytes. Every bite put on the SDATA line must be 8-bits long (MSB first), followed by an acknowledge bit generated by the receiving device. During normal data transfers SDATA changes only when SCLK is LOW. Exceptions: A HIGH-to-LOW transition on SDATA while SCLK is HIGH indicates a “start” condition. A LOW-to-HIGH transition on SDATA while SCLK is HIGH is a “stop” condition and indicates the end of a data transfer cycle. Each data transfer is initiated with a start condition and ended with a stop condition. The first byte after a start condition is always a 7-bit address byte followed by a read/write bit. (HIGH = read from addressed device, LOW= write to addressed device). If the device’s own address is detected, PI6C184 generates an acknowledge by pulling SDATA line LOW during ninth clock pulse, then accepts the following data bytes until another start or stop condition is detected. Following acknowledgement of the address byte (D2), two more bytes must be sent: 1. “Command Code” byte, and 2. “Byte Count” byte. Although the data bits on these two bytes are “don’t care,” they must be sent and acknowledged. Note: Stresses greater than those listed under MAXIMUM RAT- INGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. Supply Current (VDD = +3.465V, CLOAD = Max.) ti B n i P n oit p ir c s e D ti B ot e zilaitin C N ti B ot e zilaitin C N ti B ot e zilaitin C N ti B ot e zilaitin C N ti B ot e zilaitin C N ti B vitc a n I/e vitc A M A R D S ti B vitc a n I/e vitc A M A R D S ti B vitc a n I/e vitc A M A R D S ti B n i P n oit p ir c s e D ti B vitc a n I/e vitc A M A R D S ti B vitc a n I/e vitc A M A R D S ti B d e v re s e R ti B d e v re s e R ti B d e v re s e R ti B d e v re s e R ti B d e v re s e R ti B d e v re s e R l o b m y S r et e m a r a P n oiti d n o C t s e T i M y T a M sti n U I D D tn err u C yl p p u S z H M N I F U B A m I D D tn err u C yl p p u S z H M 6.6 N I F U B I D D tn err u C yl p p u S z H M 0.0 N I F U B Maximum Ratings (Above which the useful life may be impaired. For user guidelines, not tested.)

Precision 1-13 Clock Buffer PS8320D 10/14/04 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 SDRAM Clock Buffer Operating Specification DC Operating Specifications (VDD = +3.3V ±5%, TA = 0°C - 70°C) lo b m y S r et e m a r a P n oitid n o C ts e T i M a M stin U e g atlo V tu p n I V H I e g atlo v h gih tu p n I V D D 0.2 V D D 3.0 V V L I e g atlo v w ol tu p n I V S S 3.0 8.0 I L I tn erru c e g a k a el tu p n I V N I V D D A m V D D V 3.3 V H O e g atlo v h gih tu ptu O I H O A m 4.2 V V L O e g atlo v w ol tu ptu O I L O A m 4.0 C T U O e c n atic a p a c nip tu ptu O F p C N I e c n atic a p a c nip tu p n I L N I P e c n atc u d n I ni P H n TA erutare p m e T tn eib m A w olfri A o N C lo b m y S r et e m a r a P s n oitid n o C ts e T i M y T a M stin U I N I M H O tn erru c p u -llu P V T U O V 0.2 A m I X A M H O tn erru c p u -llu P V T U O V 1.3 I N I M L O tn erru c n w o d -llu P V T U O V 0.1 I X A M L O tn erru c n w o d -llu P V T U O V 4.0 t H R M A R D S yln o M A R D S etar e g d e e sir tu ptu O V 4.2 V V 3.3 5.1 s V t H T M A R D S yln o M A R D S etar e g d e llaf tu ptu O V 4.0 V 4.2 V 3.3 5.1 AC Timing Symbol Parameter

66 MHz

100 MHz

Min. Max. Min. Max. TDSKP SDRAM CLK period 15.0 15.5 10.0 10.5 ns TSDKH SDRAM CLK high time 5.6 3.3 ns TSDKL SDRAM CLK low time 5.3 3.1 ns TSDRISE SDRAM CLK rise time 1.5 4.0 1.5 4.0 V/ns TSDFALL SDRAM CLK fall time 1.5 4.0 1.5 4.0 V/ns tPLH SDRAM Buffer LH prop delay 1.0 5.5 1.0 5.0 ns tPHL SDRAM Buffer HL prop delay 1.0 5.5 1.0 5.0 ns DutyCycle Measured at 1.5V tSDSKW SDRAM Output to Output Skew 250 250 ps

Figure 1. Clock Waveforms

  1. Maximum rise/fall times are guaranteed at maximum specified load.
  2. Minimum rise/fall times are guaranteed at minimum specified load.
  3. Rise/fall times are specified with pure capacitive load as shown.

Testing is done with an additional 500Ω resistor in parallel.

  1. Place series resistors and CI capacitors as close as possible to the respective clock pins. Typical value

are still within the specified values.

  1. Minimize the number of “vias” of the clock traces.
  2. Route clock traces over a continuous ground plane or over a continuous power plane. Avoid routing

clock traces from plane to plane (refer to rule #2).

  1. Position clock signals away from signals that go to any cables or any external connectors.

depending on actual PCB design and layout. Figure 2. Design Guidelines

Precision 1-13 Clock Buffer PS8320D 10/14/04 123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123 123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123 Pericom Semiconductor Corporation • 1-800-435-2336 • www.pericom.com Packaging Mechanical: 28-pin SSOP (H) Notes: Thermal characteristics can be found on the company web site at www.pericom.com/packaging/

Ordering Information

H 28-pin SSOP PI6C184HE H Pb-free & Green, 28-pin SSOP