Features
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Technical content
Features
Î Converts low-swing AC coupled differential input to HDMI™ rev 1.3 compliant open-drain current steering Rx terminated differential output Î HDMI Level shifting operation up to 2.5Gbps per lane (250MHz pixel clock) Î Integrated 50-ohm termination resistors for AC-coupled differential inputs. Î Enable/Disable feature to turn off TMDS outputs to enter low-power state. Î Output slew rate control on TMDS outputs to minimize EMI Î Integrated Passive DDC level shifters (3.3V source to 5V sink) Î Transparent operation: no re-timing or configuration required Î Level shifter for HPD signal from HDMI/DVI connector Î Integrated pull-down on HPD_sink input guarantees "input low" when no display is plugged in Î 3.3V Power supply required Î TMDS output enable control Î ESD protection on all I/O pins à 4kV HBM à ±8kV con tact ESD protection on the following pins → OUT_Dx → SDA_SI NK, SCL_SINK → HPD_SI NK Î Packaging (Pb-free & Green available): à 48 TQFN, 7 mm × 7mm (ZBE) Dual Mode DisplayPort™ to DVI/HDMI™ Electrical Bridge (Level Shifter) PART OBSOLETE - USE PI3HDX511F www.diodes.comPI3VDP411LSR Document Number DS45872 Rev 1-4
Dual Mode DisplayPort™ to DVI/HDMI™ Electrical Bridge (Level Shifter) Block Diagram OE# INx_D4+ INx_D4- OUTx_D4+ OUTx_D4- 50Ω 50Ω Rx INx_D3+ INx_D3- OUTx_D3+ OUTx_D3- 50Ω 50Ω Rx INx_D2+ INx_D2- OUTx_D2+ OUTx_D2- 50Ω 50Ω Rx INx_D1+ INx_D1- OUTx_D1+ OUTx_D1- 50Ω 50Ω Rx HPD_SOURCE 100KΩ HPD_SINK HPD SR0 SR1 DDC_EN (0V to 3.3V) SDA_Sink SCL_Sink SDA_Source SCL_Source PI3VDP411LSR Document Number DS45872 Rev 1-4
Dual Mode DisplayPort™ to DVI/HDMI™ Electrical Bridge (Level Shifter) Pin Name I/O Type Descriptions 31, 36, 37, 43 GND POWER GROUND 40, 46 V DD POWER POWER, 3.3V ±10% 3 SR0 I Slew Rate Control. Acceptable connections to SR0 pin are: resistor to 3.3V or short to GND. (internal 200KΩ pull-LOW) 4 SR1 I Slew Rate Control. Acceptable connections to SR1 pin are: resistor to 3.3V or short to GND. (internal 200KΩ pull-LOW) 6, 10, 34, 35 NC O No Connect
7 HPD_SOURCE O
HPD_SOURCE: 0V to 3.3V (nominal) output signal. HPD_Sink input can be as high as 5V and then HPD_Source will output no higher than 3.3V.
8 SDA_SOURCE I/O
3.3V DDC Data I/O. Pulled up by external termination to 3.3V. Connected to SDA_SINK through voltage limiting integrated NMOS passgate.
9 SCL_SOURCE I/O
3.3V DDC Data I/O. Pulled up by external termination to 3.3V. Connected to SCL_SINK through voltage-limiting integrated NMOS passgate 13 OUT_D4+ O HDMI 1.3 compliant TMDS output. OUT_D4+ makes a differential output signal with OUT_D4-. 14 OUT_D4- O HDMI 1.3 compliant TMDS output. OUT_D4- makes a differential output signal with OUT_D4+ 16 OUT_D3+ O HDMI 1.3 compliant TMDS output. OUT_D3+ makes a differential output signal with OUT_D3-. 17 OUT_D3- O HDMI 1.3 compliant TMDS output. OUT_D3- makes a differential output signal with OUT_D3+ 19 OUT_D2+ O HDMI 1.3 compliant TMDS output. OUT_D2+ makes a differential output signal with OUT_D2-. 20 OUT_D2- O HDMI 1.3 compliant TMDS output. OUT_D2- makes a differential output signal with OUT_D2+ 22 OUT_D1+ O HDMI 1.3 compliant TMDS output. OUT_D1+ makes a differential output signal with OUT_D1-. 23 OUT_D1- O HDMI 1.3 compliant TMDS output. OUT_D1- makes a differential output signal with OUT_D1+
25 OE# I
Enable for IN_Dx to OUT_Dx level shifter path. OE# IN_D Termination OUT_D Outputs 1 > 100KΩ High-Z 0 50Ω Active
28 SCL_SINK I/O
5V DDC Clock I/O. Pulled up by external termination to 5V. Connected to SCL_SOURCE through voltage limiting integrated NMOS passgate. PI3VDP411LSR Document Number DS45872 Rev 1-4
Dual Mode DisplayPort™ to DVI/HDMI™ Electrical Bridge (Level Shifter) Pin Name I/O Type Descriptions
29 SDA_SINK I/O
5V DDC Data I/O. Pulled up by external termination to 5V. Con- nected to SDA_SOURCE through voltage limiting integrated NMOS passgate.
30 HPD_SINK I
Low Frequency, 0V to 5V (nominal) input signal. This signal comes from the TMDS connector. Voltage High indicates “plugged” state; voltage low indicated “unplugged”. HPD_SINK is pulled down by an integrated 100K ohm pull-down resistor.
32 DDC_EN I
Enables bias voltage to the DDC passgate level shifter gates. (May be implemented as a bias voltage connection to the DDC pass gates themselves.) DDC_EN Passgate 0V Disable 3.3V Enable 38 IN_D1- I Low-swing diff input from DP Tx outputs. IN_D1- makes a differ- ential pair with IN_D1+. 39 IN_D1+ I Low-swing diff input from DP Tx outputs. IN_D1+ makes a dif- ferential pair with IN_D1-. 41 IN_D2- I Low-swing diff input from DP Tx outputs. IN_D2- makes a differ- ential pair with IN_D2+. 42 IN_D2+ I Low-swing diff input from DP Tx outputs. IN_D2+ makes a dif- ferential pair with IN_D2-. 44 IN_D3- I Low-swing diff input from DP Tx outputs. IN_D3- makes a differ- ential pair with IN_D3+. 45 IN_D3+ I Low-swing diff input from DP Tx outputs. IN_D3+ makes a dif- ferential pair with IN_D3-. 47 IN_D4- I Low-swing diff input from DP Tx outputs. IN_D4- makes a differ- ential pair with IN_D4+. 48 IN_D4+ I Low-swing diff input from DP Tx outputs. IN_D4+ makes a dif- ferential pair with IN_D4-. PI3VDP411LSR Document Number DS45872 Rev 1-4
Dual Mode DisplayPort™ to DVI/HDMI™ Electrical Bridge (Level Shifter) Absolute Maximum Ratings (Over operating free-air temperature range) Item Rating Supply Voltage to Ground Potential 5.5V All Inputs and Outputs -0.5V to VDD+0.5V Ambient Operating Temperature -40 to +85°C Storage Temperature -65 to +150°C Junction Temperature 150°C Soldering Temperature 260°C Stress beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. Parameter Min. Typ. Max. Unit Ambient Operating Temperature -40 +85 °C Power Supply Voltage (measured in respect to GND) +3.0 +3.6 V PI3VDP411LSR Document Number DS45872 Rev 1-4
Dual Mode DisplayPort™ to DVI/HDMI™ Electrical Bridge (Level Shifter) Table: Power Supplies and Temperature Range Symbol Parameter Min Typ Max Units Comments VDD 3.3V Power supply 3.0 3.3 3.6 V ICC Max Current 100 mA ICCQ Standby Current 2 mA OE# = HIGH TCASE Case temperature range for operation with spec. -40 85 Celsius (°) Table: Differential Input Characteristics for IN_Dx signals Symbol Parameter Min Typ Max Units Comments Tbit Unit Interval 360 ps Tbit is determined by the display mode. Nominal bit rate ranges from 250Mbps to 2.5Gbps per lane. Nomi- nal Tbit at 2.5 Gbps = 400 ps. 360ps = 400ps-10% V RX_DIFF Input Differential Volt- age level 0.175 1.200 V See note 1 below T RX_EYE Minimum Eye Width at IN_D input pair 0.8 T bit The level shifter may add a maximum of 0.02UI jitter (400 * 0.02) = 8ps V CM-ACp-p AC Peak Common Mode Input Voltage 100 mV See note 2 below Z RX_DC 40 50 60 Ω Required IN_D+ as well as IN_D- DC impedance (50 ±20% tolerance). Z RX-Bias 0 2.0 V Intended to limit power-up stress on chipset's PCIE output buffers. Z RX_HIGH-Z 100 k Ω Differential inputs must be in a high impedance state when OE# is HIGH. 1. VRX-DIFF = 2x|VRX-D- -VRX-D-| Applies to IN_Dx signals 2. VCM-AC-p-p = |VRX-D- - VRX-D-|/2 - VRX-CM-DC VRX-CM-DC = DC(avg) of |VRX-D+ + VRX-D-|/2 VCM-AC-p-p includes all frequencies above 30 kHz. TMDS Outputs The level shifter's TMDS outputs are required to meet HDMI 1.3 specifications. The HDMI 1.3 Specification is assumed to be the correct reference in instances where this document conflicts with the HDMI 1.3 specification. PI3VDP411LSR Document Number DS45872 Rev 1-4
Dual Mode DisplayPort™ to DVI/HDMI™ Electrical Bridge (Level Shifter) Truth Table (Slew Rate control function) SR1 SR0 Rise/Fall Time (Typ) 1 1 140ps 1 0 130ps 0 1 120ps 0 0 110ps Test Setup Condition VDD = 3.3V, Ambient temperture 25°C Rise /Fall time is from 20% to 80% on Rising/Falling edge Date r ate: 620 Mbps Inpu t: 1V differential peak-to-peak clock pattern Equa lization : 3dB Table 1: OE Pin Description OE# Device State Comments Asserted (low voltage) Differential input buffers and output buffers enabled. Input impedance = 50Ω Normal functioning state for IN_D to OUT_D level shifting function. Unasserted (high voltage) Low-power state. à Differen tial input buffers and termination are disabled. à Differen tial inputs are in a high impedance state. à OUT_ D level-shifting outputs are disabled. à OUT_ D level-shifting outputs are in high impedance state. à Inter nal bias currents are turned off. Intended for lowest power condition when: à No dis play is plugged in or à The lev el shifted data path is disabled HPD_SINK input and HPD_SOURCE output are not affected by OE# SCL_ SOURCE, SCL_SINK, SDA_SOURCE and SDA_SINK signals and functions are not affected by OE# PI3VDP411LSR Document Number DS45872 Rev 1-4
Dual Mode DisplayPort™ to DVI/HDMI™ Electrical Bridge (Level Shifter) Table 2: Differential Output Characteristics for TMDS_OUT signals Symbol Parameter Min Typ Max Units Comments VH Single-ended high level output voltage VDD-10mV V DD VDD+10mV V VDD is the DC termination volt- age in the HDMI or DVI Sink. V DD is nominally 3.3V VL Single-ended low level output voltage V DD-600mV V DD-500mV V DD-400mV V The open-drain output pulls down from V DD. VSWING Single ended output swing voltage 425 500 600 mV Swing down from TMDS termi- nation voltage (3.3V ±10%) I OFF Single-ended current in high-Z state 50 µA Measured with TMDS outputs pulled up to V DD Max _(3.6V) through 50Ω resistors. TSKEW-INTRA Intra-pair differential skew 30 ps This differential skew budget is in addition to the skew present- ed between D+ and D- paired input pins. HDMI revision 1.3 source allowable intrapair skew is 0.15 T bit. TSKEW-INTER Inter-pair lane-to-lane output skew 100 ps This lane-to-lane skew budget is in addition to skew between differential input pairs T JIT Jitter added to TMDS signals 25 ps Jitter budget for TMDS signals as they pass through the level shifter. 25ps = 0.056 T bit at 2.25 Gb/s TMDS output oscillation elimination The inputs do not incorporate a squelch circuit. Therefore, we recommend the input to be externally biased to prevent output oscilla- tion. Pericom recommends to add a 1.5Kohm pull-up to the CLK- input. TMDS Input Fail-Safe Recommendation 1.5Kohm RINT VBIAS RINT DMDP Receiver TMDS Driver SS SS RT RT AVDD 3.3V PI3VDP411LSR Document Number DS45872 Rev 1-4
Dual Mode DisplayPort™ to DVI/HDMI™ Electrical Bridge (Level Shifter) Table 3: HPD Characteristics Symbol Parameter Min Typ Max Units Comments VIH-HPD Input High Level 2.0 5.0 5.3 V Low-speed input changes state on cable plug/ unplug VIL-HPD HPD_sink Input Low Level 0 0.8 V I IN-HPD HPD_sink Input Leakage Current 70 µA Measured with HPD_sink at V IH-HPD max and VIL-HPD min VOH-HPD HPD_source Output High-Level 2.5 V DD V VDD = 3.3V ±10% IOH = -4mA(MIN) / -8mA(MAX) VOL-HPD HPD_source Output Low- Level 0 0.4 V I OL = 4mA(MIN) / 8mA(MAX) THPD HPD_sink to HPD_source propagation delay 200 ns Time from HPD_sink changing state to HPD_source changing state. Includes HPD_ source rise/fall time T RF-HPDB HPD_source rise/ fall time 1 20 ns Time required to transition from VOH- HPDB to VOL-HPDB or from VOL-HPDB to VOH-HPDB Table 4: OE# Input, DDC_EN Symbol Parameter Min Typ Max Units Comments VIH Input High Level 2.0 VDD V TMDS enable input changes state on cable plug/unplug V IL Input Low Level 0 0.8 V IIN Input Leakage Current 10 µA Measured with input at VIH-EN max and VIL-EN min Table 5: Termination Resistor Symbol Parameter Min Typ Max Units Comments RHPD HPD_sink input pull- down resistor. 100K Ω Guarantees HPD_sink is LOW when no display is plugged in. PI3VDP411LSR Document Number DS45872 Rev 1-4
Dual Mode DisplayPort™ to DVI/HDMI™ Electrical Bridge (Level Shifter) Pericom Semiconductor Corporation • 1-800-435-2336 DESCRIPTION: 48-Pin, Thin Fine Pitch Quad Flat No-Lead (TQFN) PACKAGE CODE: ZB48 DOCUMENT CONTROL #: PD-2080 REVISION: A DATE: 02/11/09 UNIT: mm Notes: 1. All dimensions are in millimeters, angles are in degrees. 2. Coplanarity applies to the exposed thermal pad as well as the terminals. 3. Refer JEDEC MO-220 4. Recommended land pattern is for reference only. 5. Thermal pad soldering area 09-0091
Ordering Information
Ordering Code Package Code Package Type PI3VDP411LSRZBE ZB Pb-free & Green, 48-pin TQFN 1. Thermal characteristics can be found on the company web site at www.pericom.com/packaging/ 2. E = Pb- free and Green 3. Add ing an X suffix = Tape/Reel Note:
- Fo r latest package info, please check: http://www.pericom.com/products/packaging/mechanicals.php PI3VDP411LSR Document Number DS45872 Rev 1-4