PI3HDX621

Features

Document overview

• PDF pages: 15

Technical content

Features

yy HDMI 1.4b compliant for sink side application yy Operation up to 3.4 Gbps per lane yy Support up to 48-bit per pixel Deep Color yy Fast switching between two TMDS input ports yy Programmable equalizer, emphasis and amplitude settings to achieve optimized TMDS signal integrity yy Each input can be AC coupled or DC coupled, while the output will maintain TMDS compliance DC coupled, current steering signals yy Idle clock detection function for output squelch and auto standby yy Integrated ARC(Audio Return Channel) and DDC Mux yy Integrated ESD protection on I/O pins to connector yy 3.3V single power supply yy 8 KV contact per IEC61000-4-2, level 4, 8 KV HBM yy Industrial temperature coverage yy Packaging (Pb-free & Green): 48-contact LQFP (FB48) Application yy Notebook Computers, Set Top Box yy A/V Home Entertainment Systems yy Dongle and Switches

Description

PI3HDX621 is the active-type 2:1 switch compliant to HDMI 1.4b specification, featuring equalized TMDS input and pre- emphasized TMDS outputs, with 3.4 Gbps high speed and long cable application. Two TMDS input ports switch fast in the built-in high speed Mux through port selection pins. Redriver boost the input signal quality, adjust known channel losses at the transmit ter and restore signal integrity at the receiver. It offers doube termination or open drain output mode by output selection pin. TMDS output can shut down to reduce power dissipation by sink side HPD detection status. DDC 2:1 Mux and ARC drivers are integrated. PI3HDX621 is specified to operate over -40 to 85 °C temperature range with 8kV ESD protec tion pins. CLKP CLKN D0N VDD VDD_REG D1N D1P D2N D2P SPDIF_IN 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 D0P ARC_OUT EQ_S0 ROUT_S0 SCL1 SDA1 HPD1 GND D2P1 D2N1 D1P1 D1N1 OC_S0 SCL_SINK SDA_SINK SEL1 OEB HPD2 SDA2 SCL2 CLKN2 CLNP2 D0N2 HPD_SINK PI3HDX621 LQFP- 48 D1N2 VDD D0P2 D1P2 D2P2 CLKN1 CLKP1 D0N1 D0P1 GND GND GND VDD D2N2 Pin Configuration Typical Application Block Diagram PI3HDX621 Source Device:A Signal Device:B Sink Device EQ EQ Driver 14-0144

3.4Gbps HDMI1.4b Active 2:1 Switch with ARC and Fast Switching 2 www.pericom.com 10/28/14 All trademarks are property of their respective owners. Functional Block Diagram HPD_SINK (1) 2:1 Active Mux CLKP1/N1 D[0:2]P1/N1 CLKP2/N2 D[0:2]P2/N2 CLKP/N D[0:2]P/N ARC_OUT SPDIF_IN VDD ROUT ROUT 120KΩ HPD Detector LDO VDD RT RT VDD RT RT Control Logic SDA_SINK SCL_SINK SCL1 SDA1 SCL2 SDA2 2:1 Mux VDD_REG OEB SEL1 HPD[1:2] ROUT_S0 OC_S0 EQ_S0 Note: (1) If HPD_SINK input voltage is higher than 5V, serial resister is recommended. The resister value is about 20 -25kΩ. 14-0144

3.4Gbps HDMI1.4b Active 2:1 Switch with ARC and Fast Switching 3 www.pericom.com 10/28/14 All trademarks are property of their respective owners. Pin Description Pin # Pin Name I/O(1) Description 39 HPD_SINK I Sink side hot plug detector input; internal pull-down at 120Kohm.

18 HPD1 O Port 1 HPD output

O Port 2 HPD output CLKN1 CLKP1 D0N1 D0P1 D1N1 D1P1 D2N1 D2P1 I Port 1 TMDS inputs. Rt = 50 Ohm CLKN2 CLKP2 D0N2 D0P2 D1N2 D1P2 D2N2 D2P2 I Port 2 TMDS inputs. Rt = 50 Ohm CLKN CLKP D0N D0P D1N D1P D2N D2P O TMDS outputs. Rout = 50 Ohm when Rout_S0 = "1"

20 SCL1 IO Port 1 DDC Clock

44 SCL2 IO Port 2 DDC Clock

37 SCL_SINK IO Sink side DDC Clock

38 SDA_SINK IO Sink side DDC Data

ROUT_S0 I TMDS output termination selection. Internal 100 Kohm pull-up. See ROUT_S0 truth table for functionality. "1" or "NC": Double termination "0": Open drain output 14-0144

3.4Gbps HDMI1.4b Active 2:1 Switch with ARC and Fast Switching 4 www.pericom.com 10/28/14 All trademarks are property of their respective owners. Pin # Pin Name I/O(1) Description

41 OEB I

Output Enable control. Active low. Internal 100 Kohm pull-down. See truth table for functionality. "1": TMDS Port1 and Port2 Output disable "0": TMDS Port1 and Port2 Output enable OC_S0 I TMDS output pre-emphasis selection. This pin has internal 100 Kohm pull-up. See OC_S0 truth table for functionality. "0": Pre-emphasis 0 dB "1": Pre-emphasis 2.5 dB EQ_S0 I TMDS Data Input Equalization selection. This pin has an internal 100 KOhm pull- low. See EQ_S0 truth table for functionality. "0" or "NC": 9 dB "1": 15 dB TMDS Clock inputs is always set as 3 dB EQ SEL1 I PORT1 or PORT2 selection. This pin has an internal 100 KOhm pull-up "1": Port 1 select "0": Port 2 select Please see Port Selection truth table.

25 SPDIF_IN I Single mode ARC signal input

24 ARC_OUT O Single mode ARC signal output

1, 12, 31 VDD P 3.3V power supply VDD_REG P LDO output for internal core power supplier. External capacitor 2.2 to 4.7 μF should be added to GND. 4, 9, 17, GND G Ground Note: (1) I = Input, O = Output, IO = Bidirectional, P = Power, G = Ground. Pin Description 14-0144

3.4Gbps HDMI1.4b Active 2:1 Switch with ARC and Fast Switching 5 www.pericom.com 10/28/14 All trademarks are property of their respective owners. Functional Description Squelch Automatic output squelch function disables TMDS output when no Input signal presents. Output Disable (Squelch) Mode uses TMDS Clock channel signal detection. When low voltage levels on the TMDS input clock signals are detected, Squelch state enables and TMDS output port signals shall disable; when the TMDS clock input signal levels are above a pre-deter mined threshold voltage, output ports shall return to the normal voltage swing levels. Hot Plug Detect Sink HPD_SINK Shut Down When HPD_SINK pin is floating or tie to GND, TMDS outputs shall shut down to sleep mode; HPD_SINK does not control DDC channel. Pre-emphasis OC_S0 Truth Table Configuration Pins Functional Description Output Types ROUT_S0 OC_S0 Single-end Vswing Pre-emphasis(1) 500 mV 0 dB Open Drain 500 mV 2.5 dB 500 mV 0 dB Double termination 500 mV 2.5 dB Note: (1) TMDS Clock Pre-emphasis is fixed 0 dB. Port Selection SEL1 Truth Table Configuration Pins Functional Description OEB SEL1 TMDS Port DDC port HPD port CLKN/P1, D0N/P1, D1N/P1,D2N/P1 SCL1/SDA1 HPD1 CLKN/P2, D0N/P2, D1N/P2,D2N/P2 SCL2/SDA2 HPD2 X OFF Follow SEL1 Follow SEL1 14-0144

3.4Gbps HDMI1.4b Active 2:1 Switch with ARC and Fast Switching 6 www.pericom.com 10/28/14 All trademarks are property of their respective owners. Rest HEAC+ HEAC+ or NO ARC_OUT SPDIF_IN 12kohm 9kohm From Scalar HDMI SinkHDMI Source To HDMI Source Rest Audio Return Channel(ARC) There are two ARC input modes, common mode and single mode input. This device can supports "single mode input" only. ARC single mode input and output ARC single mode signal output waveform Typical DDC, HPD application block diagram V eh = 0~5V, +V eh-swing = 250mV, -Veh-swing = 250mV -Veh-swing +V eh-swing +V eh-swing +V eh-swing V eh 3.3V SCL_SINK HPD_SINKHPD_5V PWR5V VDD HPD1/2 SCL1/2 SDA1/2 SDA_SINKSDA_SRC SCL_SRC Sink Device (Rx) Source Device (Tx) PI3HDX621 Sink-side Application Board 3.3V 3.3V 3.3V5V 1.5kΩ 1.5kΩ 47kΩ 47kΩ 3.3V TraceCable Note(1) Note(2) Note: (1) When source device provides 5V power supply, two external BJTs is recommended with 1kΩ pull-up with PWR5V(5V), another pull-up resistor with VDD(3.3V) . HPD1/HPD2 outputs are open-drain type with external pull-up resistor requirement. (2) Also source device DDCs are recommends to use external FETs as a voltage level-shifter for the highly reliable system design. 14-0144

3.4Gbps HDMI1.4b Active 2:1 Switch with ARC and Fast Switching 7 www.pericom.com 10/28/14 All trademarks are property of their respective owners. Absolute Maximum Ratings Item Rating Supply Voltage to Ground Potential 4.5V All Inputs and Outputs -0.5V to 4.5V Storage Temperature -65 to +150°C Junction Temperature 150°C Soldering Temperature 260°C Note: Stress beyond those lists under “Absolute Maximum Ratings” may cause permanent damage to the device Recommended Operation Conditions Parameter Min. Ty p. Max. Unit Ambient Operating Temperature -40 25 85 °C Power Supply Voltage (measured in respect to GND) 3.0 3.3 3.6 V Electrical Specification Parameter Parameter Conditions Min. Ty p. Max. Unit VDD Operating Voltage 3.0 3.3 3.6 V IDD VDD Supply Current Output Enable (open drain 500 mV single-ended, 0 dB pre- emphasis) 120 150 mA Output Enable ( double termina tion, 500 mV single-ended, 0 dB pre-emphasis) 190 230 mA IDD_SQLH Supply Current in squelch mode VDD=3.6V HPD_SINK=3.6V mA ISTB Standby mode VDD = 3.6V, HPD_x = 0V, ARC_OUT = 0, OEB = High mA VOL_HPD Open Drain Output Low Volt age IOL = 4 mA 0 0.4 V IOFF_HPD Off leakage current VDD = 0V, VIN = 3.6V 20 µ A IOZ_HPD Output leakage current VDD = 3.6V, VIN = 3.6V 20 14-0144

3.4Gbps HDMI1.4b Active 2:1 Switch with ARC and Fast Switching 8 www.pericom.com 10/28/14 All trademarks are property of their respective owners. DDC Channel Block Symbol Parameter Conditions Min. Ty p. Max. Units ILK Input leakage current DDC switch is OFF -10 40 µ A CIO Input/Output capacitance VIpeak-peak = 1V, 100 KHz pF RON On resistance IO = 3mA, VO = 0.4V 25 50 Ω Control Pin (OEB) Symbol Parameter Conditions Min. Ty p. Max. Units IIH High level digital input current VIH =VDD -30 µ A IIL Low level digital input current VIL = GND -10 10 µA VIH High level digital input voltage 2.0 V VIL Low level digital input voltage 0 0.8 V HPD_SINK Symbol Parameter Conditions Min. Ty p. Max. Units IIH High level digital input current VIH = VDD -25 40 µA IIL Low level digital input current VIL = GND -10 10 µ A VIH High level digital input voltage VDD = 3.3V 2.0 V VIL Low level digital input voltage 0 0.8 V 14-0144

3.4Gbps HDMI1.4b Active 2:1 Switch with ARC and Fast Switching 9 www.pericom.com 10/28/14 All trademarks are property of their respective owners. TMDS Differential Pins Symbol Parameter Conditions Min. Ty p. Max. Units VOH Single-ended high level output voltage V DD =3. 3V, ROUT=50 Ω VDD-10 VDD+10 mV VOL Single-ended low level output voltage VDD- 600 VDD- 400 mV VSWING Single-ended output swing voltage 400 600 mV VOD(O) Overshoot of output differential voltage (1) 180*1 mV VOD(U) Undershoot of output differential voltage (2) 200*2 mV VOC(SS) Change in steady-state common-mode out - put voltage between logic 5 mV IOS Short Circuit output current -12 12 mA Short Circuit output current at double termi- nation mode -24 24 mA VI(open) Single-ended input voltage under high im - pedance input or open II=10uA VDD-10 VDD+10 mV RT Input termination resistance VIN=2.9V 45 50 55 Ω IOZ Leakage current with Hi-Z I/O VDD=3.6V 10 µA Note: (1) Overshoot of output differential voltage VOD(O) = (VSWING(MAX) * 2) * 15% (2) Undershoot of output differential voltage VOD(O) = (VSWING(MIN) * 2) * 25% SPDIF & ARC Pins Symbol Parameter Conditions Min. Ty p. Max. Units IIH_SPDIF High level input current VDD=3.6V, VIH=3.6V 500 µ A IIL_SPDIF Low level input current VDD=3.6V, VIL= GND -350 µ A VEL Single mode input/output Vel DC voltage level 0 5.0 V VEL_SWING_SPDIF Single mode input swing 0.2 0.6 V VEL_SWING_ARC_ OUT Single mode ARC output swing 0.4 0.5 0.6 V RO Output resistance of ARC output stage Ω tR ARC output rise time (10% to 90%) < 0.4UI (fclock = 6.144MHz) 25 ns tF ARC output fall time (10% to 90%) < 0.4UI (fclock = 6.144MHz) 25 ns tJPP ARC signal peak to peak jitter < 0.4UI (fclock = 6.144MHz) 3 ns 14-0144

3.4Gbps HDMI1.4b Active 2:1 Switch with ARC and Fast Switching 10 www.pericom.com 10/28/14 All trademarks are property of their respective owners. TMDS Differential Pins Symbol Parameter Conditions Min. Ty p. Max. Units tPD Propagation delay VDD = 3.3V, Rout = 50 Ohm 2000 ps tR Differential output signal rise time (20% - 80%) 190 tF Differential output signal fall time (20% - 80%) 190 tSK(p) Pulse skew 10 50 tSK(D) Intra-pair differential skew 23 50 tSK(O) Inter-pair differential skew 100 tJIT(pp) Peak-to-peak output jitter CLK residual jitter CLK Input = 300MHz clock 15 30 tJIT(pp) Peak-to-peak output jitter DATA Residual Jitter 18 50 tSX Select to switch output 10 tEN Enable time 1 us tDIS Disable time 10 ns Control and Status Pins (HPD_SINK, HPD) Symbol Parameter Conditions Min. Ty p. Max. Units tPD(HPD) Propagation Delay CL = 10pF, Pull-up resistor=1 Kohm Open drain output 10 ns tSX(HPD) Select to switch output 10 ns DDC I/O Pins (SCL, SCL_SINK, SDA, SDA_SINK) Symbol Parameter Conditions Min. Ty p. Max. Units tPD(DDC) Propagation Delay CL = 10pF 0.4 2.5 ns 14-0144

3.4Gbps HDMI1.4b Active 2:1 Switch with ARC and Fast Switching 11 www.pericom.com 10/28/14 All trademarks are property of their respective owners. Test Setup of DC-coupled TMDS Input Measurement 100% 20% 20% 80% 80% OUT_Dx+ VSWING VSWING(Max) VSWING(Min) OUT_Dx- tR tF Rise/Fall Time and Single-ended Swing Voltage Intra-pair Skew Definition 50% OUT_Dx+ OUT_Dx- tskt(D) HDMI Source Oscilloscope VDD Test Probe 3.3VVDD IN_DX+ IN_DX- OUT_DX+ OUT_DX- TP1 measurement point 50Ω 50Ω 50Ω 50Ω 50Ω 50Ω Output Enable Pre-emphasis Input Equalzation Output termination Selection 14-0144

3.4Gbps HDMI1.4b Active 2:1 Switch with ARC and Fast Switching 12 www.pericom.com 10/28/14 All trademarks are property of their respective owners. Power Supply Decoupling Circuit It is recommended to put 0.1 µF decoupling capacitors on each VDD pins of our part, there are four 0.1 µF decoupling capacitors are put in Figure 1 with an assumption of only four VDD pins on our part, if there is more or less VDD pins on our Pericom parts, the number of 0.1 µF decoupling capacitors should be adjusted according to the actual number of VDD pins. On top of 0.1 µF decoupling capacitors on each VDD pins, it is recommended to put a 10 µF decoupling capacitor near our part’s VDD, it is for stabilizing the power supply for our part. Ferrite bead is also recommended for isolating the power supply for our part and other power supplies in other parts of the circuit. But, it is optional and de pends on the power supply conditions of other circuits. Requirements on the De-coupling Capacitors There is no special requirement on the material of the capacitors. Ceramic capacitors are generally being used with typi - cally materials of X5R or X7R. Recommended Power Supply Decoupling Capacitor Diagram 14-0144

3.4Gbps HDMI1.4b Active 2:1 Switch with ARC and Fast Switching 13 www.pericom.com 10/28/14 All trademarks are property of their respective owners. Layout and Decoupling Capacitor Placement Consideration yy Each 0.1 µF decoupling capacitor should be placed as close as possible to each VDD pin. yy VDD and GND planes should be used to provide a low impedance path for power and ground. yy Via holes should be placed to connect to VDD and GND planes directly. yy Trace should be as wide as possible yy Trace should be as short as possible. yy The placement of decoupling capacitor and the way of routing trace should consider the power flowing criteria. yy 10 µF Capacitor should also be placed closed to our part and should be placed in the middle location of 0.1 µF capacitors. yy Avoid the large current circuit placed close to our part; especially when it is shared the same VDD and GND planes. Since large current flowing on our VDD or GND planes will generate a potential variation on the VDD or GND of our part. Decoupling Capacitor Placement Diagram 14-0144

3.4Gbps HDMI1.4b Active 2:1 Switch with ARC and Fast Switching 14 www.pericom.com 10/28/14 All trademarks are property of their respective owners. Packaging Mechanical: 48-Contact LQFP (FB)1 DESCRIPTION: 48-Contact, Low Profi le Quad Flat Package (LQFP) PACKAGE CODE: FB (FB48) DOCUMENT CONTROL #: PD-2027 REVISION: C DATE: 09/17/09 09-0012Please check for the latest package information on the Pericom web site at www.pericom.com/support/packaging/

Ordering Information

Ordering Number Package Code Package Description PI3HDX621FBE FB Pb-free & Green 48-Contact LQFP

• Thermal characteristics can be found on the company web site at www.pericom.com/packaging/
• E = Pb-free and Green
• X suffix = Tape/Reel 14-0144

3.4Gbps HDMI1.4b Active 2:1 Switch with ARC and Fast Switching 15 www.pericom.com 10/28/14 All trademarks are property of their respective owners.

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