PI3HDX511F

Online Datasheet

Read PI3HDX511F online.

Document overview

Manufacturer or author: Diodes Incorporated
PDF pages: 35

Technical content

2.1 Revision History

P10 - Add Eye opening measurement with different test set-up in the functional description. Expand I-temp grade support in the ordering information. July 2016 Add more contents to assist the system design-in in Application page 20 eg. PCB layout, HDMI compliance report. September 2016 Add clarity for the total power dissipation in the Open-drain and the Double termination modes in p1, p12 and p13. February 2017 Add Via in the package mechanical drawing June 2017 I-temp ordering part number added . Diodes Datasheet style updated. November 2017 Package outline drawing updated. August 2018 2 Remove HDMI active cable/dongle application. November 2020 3 Updated Package from ZL Package to ZLC Package November 2022 4 Updated Package Drawing Updated to Offical Format August 2025 5 Updated Format Updated Absolute Maximum Ratings Updated Mechanical Data Added Part Marking

2.2 Products Comparison

PI3HDX511F PI3HDX511D PI3VDP1431 PI3HDX511E Package 40-pin contact 30-pin contact 32-pin contact 32-pin contact Body Size(mm) 3x9 2,5x4.5 3x9 3x9 Power Supply 1.5V Core, 3.3V IO power 3.3V 3.3V 3.3V Data/Clock Pin Swap Ye s No No No Low Power LDO Bypass Ye s No No No Power Dissipation 70mA@1.5V , 3mA@3.3V 120mA @ 3.3V 120mA @ 3.3V 120mA @ 3.3V DDC channels Passive Switch or Buffers Passive Switch only Passive Switch or Buffers Passive Switch or Buffers

Applications

level shifter DP++ level shifter TMDS ReDriver DP++ level shifter Sink and Source devices. Space-limited ultra mobile system Source Devices like NoteBook PC system Source Devices requires P2P with PI3HDMI511 earlier part.

2.3 Related Products

Part Numbers Products Description PI3DPX1203B 8.1Gbps Displayport 1.4 Linear Redriver. Low-jitter, Latency Free. PI3HDX1204B1 6Gbps HDMI 2.0 Redriver and Displayport Level Shifter, Low-jitter, High EQ. PI3HDX414 1:4 Active 3.4Gbps HDMI 1.4b Splitter/DeMux with Signal Conditioning PI3HDX412BD 1:2 Active 3.4Gbps HDMI 1.4b Splitter/DeMux with Signal Conditioning PI3HDX621 2:1 Active 3.4Gbps HDMI 1.4b Switch PI3HDMI336 3:1 Active 2.5Gbps HDMI Switch with I2C control and ARC Transmitter PI3DPX1202 5.4Gbps Displayport 1.2 Redriver with built-in auto test mode PI3WVR12612 Wide Voltage Range DisplayPort™ & HDMI Video 1:2 Mux/DeMux

2.4 Reference Document

HDMI 1.4 High-Definition Multimedia Interface Specification Version 1.4, HDMI Licensing, LLC

2.5 Product Status Definition

Advanced Formative / In Design Datasheet contains the design specifications for product development. Specifications may change in any manner without notice. Preliminary First Production Datasheet contains preliminary data; supplementary data will be published at a later date. Diodes Incorporated reserves the right to make product specification changes at any time without notice to improve design. No Identification Needed Full Production Datasheet contains final specifications. Diodes Incorporated reserves the right to make changes at any time without notice to improve datasheet informative or reference contents. Obsolete Not In Production Datasheet contains specifications on a product that is discontinued by Diodes Incorporated. The datasheet is for reference information only.

3.1 Package Pinout

VDD SCL_SINK IN_D0- CEXT/VDD15 VDD IN_CLK- IN_CLK+ HPD_SRC TMDS_ORDER HPDO_S0 SCL_SRC GND SDA_SRC GND TQFN 40 IN_D2- IN_D2+ IN_D1- IN_D1+ VDD IN_D0+ ROUT_S0 20OC_S0 OUT_CLK+ OUT_CLK- OUT_D2- OUT_D2+ OUT_D1- OUT_D1+ OUT_D0- OUT_D0+ DDC_SEL VBIAS EQ_S0 EQ_STEP HPD_SINK

35 SDA_SINK

LDO_EN GND Figure 3-1 Pinout Configuration

3.2 Pin Description

Pin Number Pin Name Type Description 1, 7, 29 VDD PWR 3.3V power supply. Add external 0.1uF decoupling capacitor to GND.

2 CEXT/VDD15 PWR

LDO output for internal core power supplier. VDD15: When LDO_EN is low "0", this shared pin be a VDD15 in dual power supply operation. Apply 1.5V power CEXT: When LDO_EN is high "1", this pin be a CEXT in 3.3V single power supply operation. Add external capacitor (2.2uF-4.7uF) to GND. 3 IN_D2- I TMDS inputs. RT = 50Ω and RPD = 200kΩ. 4 IN_D2+ I TMDS inputs. RT = 50Ω and RPD = 200kΩ. 5 IN_D1- I TMDS inputs. RT = 50Ω and RPD = 200kΩ. 6 IN_D1+ I TMDS inputs. RT = 50Ω and RPD = 200kΩ. 8 IN_D0- I TMDS inputs. RT = 50Ω and RPD = 200kΩ. 9 IN_D0+ I TMDS inputs. RT = 50Ω and RPD = 200kΩ. 10 IN_CLK- I TMDS inputs. RT = 50Ω and RPD = 200kΩ. 11 IN_CLK+ I TMDS inputs. RT = 50Ω and RPD = 200kΩ.

12 HPD_SRC O HPD output to source side

13 TMDS_ORDER I TMDS pin order swap control with internal pull high. Default is D2/D1/D0/CLK input sequence. 14 HPDO_S0 I HPD_SRC output control with internal pull high. Default is Open drain output 15, 18, 37, 39, Center Pad GND GND Ground

16 SDA_SRC IO Source side DDC Data

17 SCL_SRC IO Source side DDC Clock

19 ROUT_S0 I

TMDS output enable with double termination or open-drain selection. Default is Ac- tive high, double termination output. Active low is open-drain output. Internal pull high to VDD. 20 OC_S0 I TMDS output pre-emphasis value selection. Default is 1.5dB pre-emphasis setting. Internally tied with 50% of VDD (or VDD/2). 21 DDC_SEL I DDC buffer or Passive switch control. Default is Passive switch mode. Internal pull high. 22 VBIAS I TMDS input termination voltage control. Default is HDMI input mode. Internally pull high. Pull-down is for Displayport input mode. 23 EQ_STEP I EQ_step selection control. Default is low-side setting of 2.5/5/7.5dB. Internally pull high. High-side EQ values are 5/10/15dB with external pull-down. 24 EQ_S0 I TMDS input three-level equalization selection. Default is middle EQ value setting. Internally 50% of VDD (VDD/2).

25 OUT_CLK+ O TMDS outputs with ROUT = 50Ω, when ROUT_S0 = "1"

26 OUT_CLK- O TMDS outputs with ROUT = 50Ω, when ROUT_S0 = "1"

27 OUT_D0+ O TMDS outputs with ROUT = 50Ω, when ROUT_S0 = "1"

28 OUT_D0- O TMDS outputs with ROUT = 50Ω, when ROUT_S0 = "1"

30 OUT_D1+ O TMDS outputs with ROUT = 50Ω, when ROUT_S0 = "1"

31 OUT_D1- O TMDS outputs with ROUT = 50Ω, when ROUT_S0 = "1"

32 OUT_D2+ O TMDS outputs with ROUT = 50Ω, when ROUT_S0 = "1"

33 OUT_D2- O TMDS outputs with ROUT = 50Ω, when ROUT_S0 = "1"

34 SCL_SINK IO Sink side DDC Clock for connector

35 SDA_SINK IO Sink side DDC Data for connector

36 HPD_SINK I Sink side HPD (Hot Plug Detect) input. Active high pin. Default is inactive for power saving. Internally pull-down at 120kΩ. 38 OEB I Output Enable control. Active low for normal operation. Active high for disable out- put HDMI signals. Internally pull-down with 100kΩ.

40 LDO_EN I

Power supply mode control pin for 1.5/3.3V or 3.3V active low.

4.1 Block Diagram

HPD_SINK HPDO_S0 HPD_SRC VDD GND 50/uni03A9 VBIAS RT IN_Dx/CLK+ IN_Dx/CLK- HPD Detect Equalizer Channel Swap 200k/uni03A9 RPD Tx Output Control ROUT OUT_Dx/CLK+ OUT_Dx/CLK- Control Logic DDC Switch LDO EQ 5-step control (2.5dB up to 15dB) Pre-emp: 0/1.5/2.5dB Swing OEB OC_S0 EQ_S0 SCL_SRC SDA_SRC LDO_EN VDD CEXT/VDD15 ROUT_S0 TMDS_ORDER EQ_STEP DDC_SEL SCL_SINK SDA_SINK 1.5V internal 3.3V 1.5V

4.2 Function Description

Automatic output squelch function disables TMDS output when no Input signal presents. Output Disable (Squelch) Mode uses TMDS Clock signal detection. When low voltage levels on the TMDS input clock are detected, Squelch state enables and TMDS outputs shall be disabled. When the TMDS clock inputs are above the pre-determined threshold voltage, TMDS outputs shall return to the normal swing voltage levels. TMDS Output Shut Down When HPD_SINK pin floats or ties to GND, TMDS outputs shall shut down to sleep mode; HPD_SINK does not control DDC channel. Table 4-1. TMDS Pin Order Configuration TMDS_ORDER Functional Description Note "0" CLK/D0/D1/D2 pin order "1" or "NC" D2/D1/D0/CLK pin order Default Table 4-2. DDC Mode Selection DDC_SEL Configuration DDC_SEL Functional Description Note "0" Active DDC Buffer "1" or "NC" Passive Switch Default Table 4-3. LDO Enable Configuration LDO_EN Pin 1 Pin 2 Functional Description "0" 3.3V 1.5V Dual power supply mode 3.3/1.5V Table 4-4. Pre-emphasis Truth Table ROUT_S0 OC_S0 Single-end Vswing Pre-emphasis Functional Description "0" "0" 500mV 0dB Open drain output. "NC" or VDD/2 500mV 1.5dB Open drain output(Default) "1" 500mV 2.5dB Open drain output "1" "0" 500mV 0dB Double termination "NC" or VDD/2 500mV 1.5dB Double termination(Default) "1" 500mV 2.5dB Double termination Table 4-5. TMDS Input Termination Voltage Control VBIAS VBIAS Functional Description "1", "NC" HDMI input. VBIAS ties to VDD. "0" DisplayPort input. VBIAS ties to GND. Table 4-6. EQ Step Selection Control EQ_STEP EQ_STEP Functional Description "1", "NC" 2.5dB, 5dB, 7.5dB EQ setting with EQ_S0 control pin "0" 5dB, 10dB, 15dB EQ setting with EQ_S0 control pin

© 2025 Copyright Diodes Incorporated. All Rights Reserved. PI3HDX511F Document Number DS40011 Rev 5-2 www.diodes.com Table 4-7. Output Data Signals EQ_S0 Configuration EQ_S0 Functional Description Note "0" 2.5dB 5dB TMDS Clock(CLK) channel EQ is always fixed as 3dB without pre-emphasis."NC" , "VDD/2" 5dB 10dB "1" 7.5dB 15dB Table 4-8. Sink Side Hot Plug Detect HPD_SINK EQ_STEP Functional Description "1" Normal mode "0" Disable output signal for power saving mode Table 4-9. Source Side Hot Plug Detect Output Control HPDO_S0 EQ_STEP Functional Description "1" or "NC" Open drain output (Default) "0" Inverted Buffer output of HPD_SINK signal Table 4-10. Output Enable Control Truth Table EQ_STEP Functional Description "0" Active Low. Normal mode "1" Disable output signal for power saving mode HPD Output Buffer From HPD_sink

300 Kohm pull-down

Figure 4-1 Source-side Output Block Diagram Note: 1) Open drain buffer is recommended with external pull-up resistor to < 4.5V power supply.

5.1 Absolute Maximum Ratings

5V Tolerance I/O Pins (SDA_SINK, SCL_SINK, HPD_SINK) .. –0.5V to 5.5V

5.2 Recommended Operation Conditions

Symbol Parameter(1) Min. Typ. Max. Unit VDD Power Supply Voltage 2.89 3.3 3.6 V 1.42 1.5 1.57 V TA Ambient Operating Temperature 0 70 oC Industrial Operating Temperature –40 85 oC Note (1) Industrial temperature -40 to +85 oC can be guaranteed by design. Commercial temperature 0 to +70 oC is supported by the production-tested.

5.3 Electrical Characteristics

5.3.1 DC Electrical Characteristics

Symbol Parameter Conditions Min. Typ. Max. Unit Single Power Supply IDD33 3.3V Power @ 0dB Pre-Emp Outputs Enable (open drain 500mV, 0 dB pre-emphasis). terminated OUT_D [0:2] and CLK with 50 ohms to VDD. Exclude 40mA current pass-through from source devices 110 mA IDD33 3.3V Power@ 0dB Pre-Emp Outputs Enable (Double termination 500mV, 0 dB pre-emphasis). termi- nated OUT_D [0:2] and CLK with 50 ohms to VDD. Exclude 40mA current pass-through from source devices 180 mA IDD33 3.3V Power @ 2.5dB Pre-Emp Outputs Enable (Open Drain 500mV, 2.5 dB pre-emphasis). terminated OUT_D [0:2] and CLK with 50 ohms to VDD. Exclude 40mA current pass- through from source devices 133 mA IDD33 3.3V Power @ 2.5dB Pre-Emp Outputs Enable (Double termination 500mV, 2.5 dB pre-emphasis). termi- nated OUT_D [0:2] and CLK with 50 ohms to VDD. Exclude 40mA current pass-through from source devices 211 mA Note: Stresses greater than those listed under MAXIMUM RAT - INGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the op - erational sections of this specification is not implied. Expo - sure to beyond the absolute maximum rating conditions for extended periods may affect inoperability and degradation of device reliability and performance.

© 2025 Copyright Diodes Incorporated. All Rights Reserved. PI3HDX511F Document Number DS40011 Rev 5-2 www.diodes.com Symbol Parameter Conditions Min. Typ. Max. Unit Dual Power Supply IDD15 1.5V @ open drain 500mV, 0dB Outputs Enable (open drain 500mV, 0dB pre-emphasis), terminated OUT_D [0:2] and CLK with 50 ohms to Vdd 58 70 mA 1.5V @ double termination 500mV, 0dB Outputs Enable (open drain 500mV, 0dB pre-emphasis), terminated OUT_D [0:2] and CLK with 50 ohms to Vdd 78.2 mA 1.5V @ double termination 500mV, 2.5dB Outputs Enable (open drain 500mV, 0dB pre-emphasis), terminated OUT_D [0:2] and CLK with 50 ohms to Vdd 93.2 mA IDD33 3.3V IO current 2 3 mA Stand-by Current ISTB Standby mode Current; VDD = 3.6V DDC passive switch ( open drain & double termination); OEB = 1, HPD_ SINK = 0 40 µA DDC active buffer ( open drain & double termination); OEB = 1, HPD_ SINK = 0 1.5 mA DDC Passive Switch ( open drain & double termination); OEB= 1 and HPD_SINK = 0 0 mA DDC active buffer ( open drain & double termination); OEB= 0 and HPD_SINK = 0 1.44 mA Squelch Current ISQLH Squelch mode current; VDD = 3.6V DDC passive switch; No input clock VDD = 3.6V, HPD_SINK = 3.6V 2.68 3.0 mA DDC active buffer; No input clock VDD = 3.6V, HPD_SINK = 3.6V 3.52 4.1 mA Note: 1. Current is due to internal 100kΩ pull-down of OE pin drawing extra current (~36uA). If forced by a separate power supply with all other control pins open, lower current is seen (~4uA). HPD Pins Symbol Parameter Conditions Min. Typ. Max. Unit HPD_SRC VOL Buffer output low voltage IOL = 4mA 0.4 V Open drain output low voltage IOL = 4mA 0 0.4 V VOH Buffer output high voltage IOH = 0.1mA VDD- 1.55 V

© 2025 Copyright Diodes Incorporated. All Rights Reserved. PI3HDX511F Document Number DS40011 Rev 5-2 www.diodes.com Symbol Parameter Conditions Min. Typ. Max. Unit IOFF Off leakage current VDD = 0, VIN = 3.6V 25 uA IOZ Open drain output leakage current VDD = 3.6V, VIN = 3.6V 25 uA HPD_SINK IIH High level digital input current VIH = 5.5V -10 80 µA IIL Low level digital input current VIL = GND -10 10 µA VIH High level digital input voltage VDD = 3.3V 2.0 V VIL Low level digital input voltage 0 0.8 V Control Pins Symbol Parameter Conditions Min. Typ. Max. Unit OEB with 100k Pull to GND IIH High level digital input current VIH = 3.3V, VDD = 3.3V -10 80 µA IIL Low level digital input current VIL = GND -10 10 µA VIH High level digital input voltage 2.0 V VIL Low level digital input voltage 0 0.8 V EQ_S0, OC_S0 with 100k Pull High and 100k Pull Low when TMDS is Active IIH High level digital input current VIH = 3.3V, VDD = 3.3V -10 40 µA IIL Low level digital input current VIL = GND, VDD = 3.3V -40 10 µA ROUT_S0, TMDS_ORDER, EQ_STEP, VBIAS, LDO_EN, DDC_SEL, HPDO_S0 IIH High level digital input current VIH = VDD -10 10 µA IIL Low level digital input current VIL = GND -20 10 µA VIH High level digital input voltage 2.0 V VIL Low level digital input voltage 0 0.8 V DDC Channel Switch Symbol Parameter Conditions Min. Typ. Max. Unit ILK Input leakage current DDC switch is off, Vin = 5.5V -10 30 µA CIO Input/Output capacitance when pas- sive switch on VIpp(peak-peak) = 1V, 100 kHz 10 pF RON Passive Switch resistance IO = 3mA, VO = 0.4V 30 50 Ω DDC Channel Buffers Symbol Parameter Conditions Min. Typ. Max. Unit VIH_SRC Source Side DDC Buffer Input High Voltage 0.6 V VIL_SRC Source Side DDC Buffer Input Low Voltage 0.4 V

© 2025 Copyright Diodes Incorporated. All Rights Reserved. PI3HDX511F Document Number DS40011 Rev 5-2 www.diodes.com Symbol Parameter Conditions Min. Typ. Max. Unit VOL_SRC Source Side DDC Buffer Output Low Voltage External pull-up to VDD from 1.5kΩ to 10kΩ 0.47 0.52 0.6 V VOL_SINK Sink Side DDC Buffer Output Low Voltage 0.2 V VIH_SINK Sink Side DDC Buffer Input High Voltage 2.0 V VIL_SINK Sink Side DDC Buffer Input Low Voltage 0.8 V CI_SRC Source side DDC capacitance when active switch is on, or passive switch off VIpp(peak-peak) = 1V, 100 KHz 5 pF CI_SINK Sink side DDC capacitance when ac- tive switch is on, or passive switch off 5 pF TMDS Differential Pins Symbol Parameter Conditions Min. Typ. Max. Unit VOH Single-ended high level output voltage VDD = 3.3V, ROUT = 50Ω VDD-10 VDD+10 mV VOL Single-ended low level output voltage VDD-600 VDD-400 mV VSWING Single-ended output swing voltage 400 600 mV VOD(O)(1) Overshoot of output differential volt- age 180(1) mV VOD(U)(2) Undershoot of output differential voltage 200(2) mV VOC(SS) Change in steady-state common- mode output voltage between logic states 5 mV IOS Short Circuit output current at open drain mode Short to VDD -12 12 mA Short Circuit output current at double termination mode Short to VDD -24 24 mA VI(open) Single-ended input voltage under high impedance or open case II = 10uA VDD-10 VDD+10 mA RT Input termination resistance VIN = 2.9V 45 50 55 Ω IOZ Leakage current with Hi-Z I/O VDD = 3.6V 30 μA Note (1) Overshoot of output differential voltage VOD(O) = (VSWING(MAX) * 2) * 15% (2) Undershoot of output differential voltage VOD(O) = (VSWING(MIN) * 2) * 25%

5.3.2 AC Electrical Characteristics

Symbol Parameter Conditions Min. Typ. Max. Unit tpd Propagation delay VDD = 3.3V, ROUT = 50Ω 2000 ps tr/tf Differential output signal rise/fall time (20% - 80%), open drain, 0dB pre-emphasis 120 Differential output signal rise/fall time (20% - 80%), open drain, 2.5dB pre-emphasis 100 tsk(p) Pulse skew 10 50 tsk(D) Intra-pair differential skew 23 50 tsk(o) Inter-pair differential skew 100 tjit(pp) Peak-to-peak output jitter CLK re- sidual jitter Data Input = 3.4 Gbps 30 60 tjit(pp) Peak-to-peak output jitter DATA residual Jitter 40 70 ten Enable time 50 μs tdis Disable time 0.01 DDC I/O Pins (Passive Switch Mode) Symbol Parameter Conditions Min. Typ. Max. Unit tpd(DDC) Propagation delay from SCL_SINK/ SDA_SINK to SCL/SDA, or SCL/ SDA to SCL_SINK/SDA_SINK in passive switch. CL = 10pF in passive switch 5 ns DDC I/O Pins (Active Buffer Mode) Symbol Parameter Conditions Min. Typ. Max. Unit tPLH LOW-to-HIGH propagation delay SCL/SDA to SCL/SDA_SINK 169 255 ns tPHL HIGH-to-LOW propagation delay SCL/SDA to SCL/SDA_SINK 10 103 300 ns tPLH LOW-to-HIGH propagation delay SCL/SDA_SINK to SCL/SDA 25 67 110 ns tPHL HIGH-to-LOW propagation delay SCL/SDA_SINK to SCL/SDA 118 230 ns Control and Status Pins (HPD_SINK, HPD) Symbol Parameter Conditions Min. Typ. Max. Unit tpd(HPD) Propagation delay from HPD_SINK to the active port of HPD, high to low CL = 10pF, pull high resistor = 1kΩ 10 ns

5.4 Output Eye: EQ Settings and Input Trace Length (Informative)

5.4.1 Test Setup

5.4.2 Output Waveforms

0" Input Trace 18" Trace (-3.87dB) 36" Trace (-7.54dB loss) 48" Trace (-10.21dB) EQ=2.5dB, Double termination, 500mV Swing, VBIAS = Low, HPD_SINK = High EQ=5dB, Double termination, 500mV Swing, VBIAS = Low, HPD_SINK = High EQ=7.5dB, Double termination, 500mV Swing, VBIAS = Low, HPD_SINK = High EQ=10dB, Double termination, 500mV Swing, VBIAS = Low, HPD_SINK = HighPI3HDX511FA

© 2025 Copyright Diodes Incorporated. All Rights Reserved. PI3HDX511F Document Number DS40011 Rev 5-2 www.diodes.com EQ=15dB, Double termination 500mV Swing, VBIAS = Low, HPD_SINK = High Note: For system designers reference, characterization trace board insertion Loss Informations and picture image are shown below. Frequency @3.4Gbps 4-in 6-in 12-in 18-in 24-in 30-in 36-in 48-in Unit

6.2 Application Block Diagram

6.3 Output Eye Measurement Data

Sink Apps test set-up: Output Eye Diagram with different EQ settings of 1.5dB, 10dB and 15dB. Trace Cards used with 24” , 48” and 84” with 2 meter HDMI Cable with proper pre-emphasis setting. Note: For system designers reference, AE-trace board information are shown below. Insertion loss is measured in the 3GHz (6.0Gbps) speed. FR4 Trace Length 0-in 6-in 12-in 18-in 24-in 30-in 36-in Unit 24” Input (-15.46dB loss) , EQ = 2.5dB, 500mV Swing, Pre- emp = 1.5dB, Rout_S0 = 1 48” Input, EQ = 10dB, 500mV Swing, Pre-emp = 0dB, Rout_ S0 = 1 84” Input, EQ = 15dB, 500mV Swing, Pre-emp = 0dB, Rout_ S0 = 1

6.4 Layout Guidelines

As transmission data rate increases rapidly, any flaws and/or mis-matches on PCB layout are amplified in terms of signal integrity. Layout guideline for high-speed transmission is highlighted in this application note.

6.4.1 Power and Ground

To provide a clean power supply for Diodes high-speed device, few recommendations are listed below:

Power (VDD) and ground (GND) pins should be connected to corresponding power planes of the printed circuit board directly without passing through any resistor.
The thickness of the PCB dielectric layer should be minimized such that the VDD and GND planes create low inductance paths.
One low-ESR 0.1uF decoupling capacitor should be mounted at each VDD pin or should supply bypassing for at most two VDD pins. Capacitors of smaller body size, i.e. 0402 package, is more preferable as the insertion loss is lower. The capacitor should be placed next to the VDD pin.
One capacitor with capacitance in the range of 4.7uF to 10uF should be incorporated in the power supply decoupling design as well. It can be either tantalum or an ultra-low ESR ceramic.
A ferrite bead for isolating the power supply for Pericom high-speed device from the power supplies for other parts on the printed circuit board should be implemented.
Several thermal ground vias must be required on the thermal pad. 25-mil or less pad size and 14-mil or less finished hole are rec- ommended. G N D P la ne VIN V DD P la ne 10uF 1uF 0.1uF 0.1uF 0.1uF Bypass noise Power Flow VIN VIN Center Pad GND Plane Several Thermal GND Vias must be required on the Thermal Pad area Figure 6-1 Decoupling Capacitor Placement Diagram

6.4.2 High-speed signal Routing

Well-designed layout is essential to prevent signal reflection:

For 90Ω differential impedance, width-spacing-width micro-strip of 6-7-6 mils is recommended; for 100Ω differential impedance, width-spacing-width micro-strip of 5-7-5 mils is recommended.
Differential impedance tolerance is targeted at ±15%. Figure 6-2 Trace Width and Clearance of Micro-strip and Strip-line
For micro-strip, using 1/2oz Cu is fine. For strip-line in 6+ PCB layers, 1oz Cu is more preferable.

6.5.2 HDMI Compliance Test Report: Pass

Test Setup : Pericom SMA-to-HDMI Test Fixture, 12” and 36” SMA Cables, Pericom 36” FR4 Trace Cards, 2m 28AWG HDMI Cable.

© 2024 Copyright Diodes Incorporated. All Rights Reserved. PI3HDX511F Document Number DS40011 Rev 5-2 www.diodes.com PI3HDX511F A Product Line of Diodes Incorporated 7. Packaging Mechanical, Ordering Information

7.1 Packaging Mechanical Outline

DATE: 07/02/21 DESCRIPTION: 40-Pin, TQFN 3X6mm (W-QFN3060-40) PACKAGE CODE: ZLC (ZLC40) DOCUMENT CONTROL #: PD-2233 REVISION: A 1. ALL DIMENSIONS ARE IN mm. ANGLES IN DEGREES 2. COPLANARITY APPLIES TO THE EXPOSED THERMAL PAD AS WELL AS THE TERMINALS 3. REFER JEDEC MO-220 4. RECOMMENDED LAND PATTERN IS FOR REFERENCE ONLY 5. THERMAL PAD SOLDERING AREA (MESH STENCIL DESIGN IS RECOMMENDED) NOTE : 21-1406

7.2 Mechanical Data

y Moisture Sensitivity: Level 1 per J-STD-020 y Terminals: Finish - Matte Tin Plated Leads. Solderable per MIL-STD-202, Method 208 y Weight: 0.046 grams (Approximate)

7.3 Part Marking Information

Our standard product mark follows our standard part number ordering information, except for those products with a speed letter code. The speed letter code mark is placed after the package code letter, rather than after the device number as it is ordered. After electrical test screening and speed binning has been completed, we then perform an “add mark” operation which places the speed code letter at the end of the complete part number. PI X1 X2X3X4 X5X6X7X8X9 Product IO Configuration i.e) X5X6= Data Speed, X7=Total IO ports, X8= Port in, X9= Port out Device Family Code i.e) DPX = DisplayPort Redriver, HDX = HDMI Redriver IO Voltage Code PI = Pericom Packaging Type i.e) Blank = Tube; X = Tape & Reel Product Skew & Version Package Code Pb-Free i.e) Blank = Standard; E = Pb-free & Green Temperature Range i.e) Blank=Commerial temp, I=Industrial temp X10X11 X12X13 I E X Figure 7-1 Part Naming Information PI3HDX 511FZLCE ZYYWWXX Z: Die Rev YY: Year WW: Workweek 1st X: Assembly Code 2nd X: Fab Code PI3HDX 511FZLCIE ZYYWWXX Z: Die Rev YY: Year WW: Workweek 1st X: Assembly Code 2nd X: Fab Code Figure 7-2 Package Marking Information

7.4 Tape & Reel Materials and Design

The Pocketed Carrier Tape is made of Conductive Polystyrene plus Carbon material (or equivalent). The surface resistivity is 106Ohm/ sq. maximum. Pocket tapes are designed so that the component remains in position for automatic handling after cover tape is removed. Each pocket has a hole in the center for automated sensing if the pocket is occupied or not, thus facilitating device removal. Sprocket holes along the edge of the center tape enable direct feeding into automated board assembly equipment. See Figures 7-5 and 7-6 for carrier tape dimensions. Cover Tape Cover tape is made of Anti-static Transparent Polyester film.The surface resistivity is 107Ohm/Sq. Minimum to 1011Ohm sq. maximum. The cover tape is heat-sealed to the edges of the carrier tape to encase the devices in the pockets. The force to peel back the cover tape from the carrier tape shall be a MEAN value of 20 to 80gm (2N to 0.8N). Reel The device loading orientation is in compliance with EIA-481, current version (Figure 7-4). The loaded carrier tape is wound onto ei- ther a 13-inch reel, (Figure 7-6) or 7-inch reel. The reel is made of Antistatic High-Impact Polystyrene. The surface resistivity 107Ohm/ sq. minimum to 1011Ohm/sq. max. NOTE: LABELS TO BE PLACED ON THE REEL OPPOSITE PIN 1 TOP COVER TAPE SPROCKET HOLE (ROUND) CARRIER TAPE EMBOSSED CAVITY BARCODE LABEL Figure 7-3 Tape & Reel Label Information END CARRIER TAPE TRAILER COVER TAPE COMPONENTS COVER TAPE START LEADER Top Left PIN 1 ORIENTATION Top Right PIN 1 ORIENTATION Bottom Left PIN 1 ORIENTATION Figure 7-4 Tape Leader and Trailer Pin 1 Orientations

© 2024 Copyright Diodes Incorporated. All Rights Reserved. PI3HDX511F Document Number DS40011 Rev 5-2 www.diodes.com PI3HDX511F A Product Line of Diodes Incorporated Cover Tape Round Sprocket Holes (10 pitches cumulative tolerance on tape ±0.2mmDo Po F Ao So Bo W Embossed Cavity Center lines of Cavity Direction of Unreeling T B1 Ko R (min) Figure 7-5 Standard Embossed Carrier Tape Dimensions Table 7-1. Constant Dimensions Tape Size D0 D1 (Min) E1 P0 P2 R (See Note 2) S1 (Min) T (Max) T1 (Max) 8mm 1.5 +0.1 -0.0 1.0 2.0 ± 0.05 0.6 0.6 0.1 12mm 1.5 3016mm 2.0 ± 0.124mm 32mm 2.0 50 N/A (See Note 3)44mm 2.0 ± 0.15 Table 7-2. Variable Dimensions Tape Size P1 B1 (Max) E2 (Min) F So T2 (Max.) W (Max) A0, B0, & K0 8mm Specific per package type. Refer to FR-0221 (Tape and Reel Packing Information) 4.35 6.25 3.5 ± 0.05 N/A (see note 4) 2.5 8.3 See Note 1 24mm 20.1 22.25 11.5 ± 0.1 12.0 24.3 NOTES: 1. A0, B0, and K0 are determined by component size. The cavity must restrict lateral movement of component to 0.5mm maximum for 8mm and 12mm wide tape and to 1.0mm maximum for 16,24,32, and 44mm wide carrier. The maximum component rotation within the cavity must be limited to 20o maximum for 8 and 12 mm carrier tapes and 10o maximum for 16 through 44mm. 2. Tape and components will pass around reel with radius “R” without damage. 3. S1 does not apply to carrier width ≥32mm because carrier has sprocket holes on both sides of carrier where Do≥S1. 4. So does not exist for carrier ≤32mm because carrier does not have sprocket hole on both side of carrier.

© 2024 Copyright Diodes Incorporated. All Rights Reserved. PI3HDX511F Document Number DS40011 Rev 5-2 www.diodes.com PI3HDX511F A Product Line of Diodes Incorporated D B C Access Hole at Slot Location (40 mm min Dia) W2(measured at hub) W1(measured at hub) Width=2.5mm Min, Depth=10.0mm Min A Figure 7-6 Reel Dimensions Table 7-5. Reel Dimensions by Tape Size Tape Size A N (Min) See Note A W1 W2(Max) W3 B (Min) C D (Min) 8mm 178 ±2.0mm or 330±2.0mm 60 ±2.0mm or 100±2.0mm Shall Ac- commodate Tape Width Without Interference mm 20.2mm 12mm 12.4 +2.0/-0.0 mm 18.4 mm 16mm 330 ±2.0mm 100 ±2.0mm 24mm 24.4 +2.0/-0.0 mm 30.4 mm 32mm 32.4 +2.0/-0.0 mm 38.4 mm 44mm 44.4 +2.0/-0.0 mm 50.4 mm NOTE: diameter (N(min)) will by 100±2.0mm.

© 2024 Copyright Diodes Incorporated. All Rights Reserved. PI3HDX511F Document Number DS40011 Rev 5-2 www.diodes.com 8. Important Notice 1. DIODES INCORPORATED (Diodes) AND ITS SUBSIDIARIES MAKE NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH RE - GARDS TO ANY INFORMATION CONTAINED IN THIS DOCUMENT, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MER - CHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD PARTY INTELLECTUAL PROPERTY RIGHTS (AND THEIR EQUIVALENTS UNDER THE LAWS OF ANY JURISDICTION). 2. The Information contained herein is for informational purpose only and is provided only to illustrate the operation of Diodes’ products described herein and application examples. Diodes does not assume any liability arising out of the application or use of this document or any product described herein. This document is intended for skilled and technically trained engineering customers and users who design with Diodes’ products. Diodes’ prod - ucts may be used to facilitate safety-related applications; however, in all instances customers and users are responsible for (a) selecting the appropriate Diodes products for their applications, (b) evaluating the suitability of Diodes’ products for their intended applications, (c) ensuring their applications, which incorporate Diodes’ products, comply the applicable legal and regulatory requirements as well as safety and functional-safety related standards, and (d) ensuring they design with appropriate safeguards (including testing, validation, quality control techniques, redundancy, malfunction prevention, and appropriate treatment for aging degradation) to minimize the risks associated with their applications. 3. Diodes assumes no liability for any application-related information, support, assistance or feedback that may be provided by Diodes from time to time. Any customer or user of this document or products described herein will assume all risks and liabilities associated with such use, and will hold Diodes and all companies whose products are represented herein or on Diodes’ websites, harmless against all damages and liabilities. 4. Products described herein may be covered by one or more United States, international or foreign patents and pending patent applications. Product names and markings noted herein may also be covered by one or more United States, international or foreign trademarks and trademark ap - plications. Diodes does not convey any license under any of its intellectual property rights or the rights of any third parties (including third parties whose products and services may be described in this document or on Diodes’ website) under this document. 5. Diodes’ products are provided subject to Diodes’ Standard Terms and Conditions of Sale ( https://www.diodes.com/about/company/terms- and-conditions/terms-and-conditions-of-sales/) or other applicable terms. This document does not alter or expand the applicable warranties provided by Diodes. Diodes does not warrant or accept any liability whatsoever in respect of any products purchased through unauthorized sales channel. 6. Diodes’ products and technology may not be used for or incorporated into any products or systems whose manufacture, use or sale is prohib- ited under any applicable laws and regulations. Should customers or users use Diodes’ products in contravention of any applicable laws or regulations, or for any unintended or unauthorized application, customers and users will (a) be solely responsible for any damages, losses or penalties arising in connection therewith or as a result thereof, and (b) indemnify and hold Diodes and its representatives and agents harmless against any and all claims, damages, expenses, and attorney fees arising out of, directly or indirectly, any claim relating to any noncompliance with the applicable laws and regula- tions, as well as any unintended or unauthorized application. 7. While efforts have been made to ensure the information contained in this document is accurate, complete and current, it may contain technical inaccuracies, omissions and typographical errors. Diodes does not warrant that information contained in this document is error-free and Diodes is under no obligation to update or otherwise correct this information. Notwithstanding the foregoing, Diodes reserves the right to make modifications, enhance- ments, improvements, corrections or other changes without further notice to this document and any product described herein. This document is written in English but may be translated into multiple languages for reference. Only the English version of this document is the final and determinative format released by Diodes. 8. Any unauthorized copying, modification, distribution, transmission, display or other use of this document (or any portion hereof) is prohibited. Diodes assumes no responsibility for any losses incurred by the customers or users or any third parties arising from any such unauthorized use. 9. This Notice may be periodically updated with the most recent version available at https://www.diodes.com/about/company/terms-and-conditions/ important-notice The Diodes logo is a registered trademark of Diodes Incorporated in the United States and other countries. All other trademarks are the property of their respective owners. © 2025 Diodes Incorporated. All Rights Reserved. www.diodes.com

Product Information

PI3HDX511F specifications and overview.

Summary

Low power DisplayPort 1.2 Redriver with DDC/AUX CH Switch Rev 2-1

Description

Low power DisplayPort 1.2 Redriver with DDC/AUX CH Switch Rev 2-1

Source title PI3HDX511F Datasheet(PDF) - Diodes Incorporated

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PI3HDX511F

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PI3HDX511F

Document overview

Technical content

2.1 Revision History

2.2 Products Comparison

Applications

2.3 Related Products

2.4 Reference Document

2.5 Product Status Definition

Contents

3.1 Package Pinout

35 SDA_SINK

3.2 Pin Description

2 CEXT/VDD15 PWR

12 HPD_SRC O HPD output to source side

16 SDA_SRC IO Source side DDC Data

17 SCL_SRC IO Source side DDC Clock

19 ROUT_S0 I

25 OUT_CLK+ O TMDS outputs with ROUT = 50Ω, when ROUT_S0 = "1"

26 OUT_CLK- O TMDS outputs with ROUT = 50Ω, when ROUT_S0 = "1"

27 OUT_D0+ O TMDS outputs with ROUT = 50Ω, when ROUT_S0 = "1"

28 OUT_D0- O TMDS outputs with ROUT = 50Ω, when ROUT_S0 = "1"

30 OUT_D1+ O TMDS outputs with ROUT = 50Ω, when ROUT_S0 = "1"

31 OUT_D1- O TMDS outputs with ROUT = 50Ω, when ROUT_S0 = "1"

32 OUT_D2+ O TMDS outputs with ROUT = 50Ω, when ROUT_S0 = "1"

33 OUT_D2- O TMDS outputs with ROUT = 50Ω, when ROUT_S0 = "1"

34 SCL_SINK IO Sink side DDC Clock for connector

35 SDA_SINK IO Sink side DDC Data for connector

40 LDO_EN I

4.1 Block Diagram

4.2 Function Description

300 Kohm pull-down

5.1 Absolute Maximum Ratings

5.2 Recommended Operation Conditions

5.3 Electrical Characteristics

5.3.1 DC Electrical Characteristics

5.3.2 AC Electrical Characteristics

5.4 Output Eye: EQ Settings and Input Trace Length (Informative)

5.4.1 Test Setup

5.4.2 Output Waveforms

6.2 Application Block Diagram

6.3 Output Eye Measurement Data

6.4 Layout Guidelines

6.4.1 Power and Ground

6.4.2 High-speed signal Routing

6.5.2 HDMI Compliance Test Report: Pass

7.1 Packaging Mechanical Outline

7.2 Mechanical Data

7.3 Part Marking Information

7.4 Tape & Reel Materials and Design

PI3HDX511F specifications and overview.

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