PI3HDX1204B1

Features

Document overview

• PDF pages: 36

Technical content

Features

y HDMI 2.0 compliant Limiting-type ReDriver to compensate high insertion loss of the long TMDS signal transmission y Supports Dual-mode DP HBR3 to HDMI 2.0 Level Shifting y Double the jitter performance than conventional CMOS-process ReDriver y Input EQ supports 16 steps up to +22.2dB @ 3GHz (6Gbps), 4 steps De-emphasis and 4 steps output voltage swing setting y Independent each channel configuration for Equalization, Output Swing and De-emphasis y Built-in channel activity detector with selectable input termination between 50 Ω to VCC and 200kΩ to VCC y Pin Strap and I2C selectable device programming mode support y Supply Voltage: 3.3V y Industrial Temperature Range: -40 oC to 85oC y Totally Lead-Free & Fully RoHS Compliant (Notes 1 & 2) y Halogen and Antimony Free. “Green” Device (Note 3) y For automotive applications requiring specific change control (i.e. parts qualified to AEC-Q100/101/104/200, PPAP capable, and manufactured in IATF 16949 certified facilities), please contact us or your local Diodes representative. https://www.diodes.com/quality/product-definitions/ y Packaging (Pb-free & Green): à 42-contact TQFN (3.4x9mm)

Ordering Information

PI3HDX1204B1ZHEX ZH 42-pin TQFN (3.5x9mm) PI3HDX1204B1ZHIEX ZH Industrial-temp, 42-pin TQFN (3.5x9mm) Notes:

• E = Pb-free and Green
• X suffix = Tape/Reel HDMI 2.0 6Gbps Limiting ReDriver with High EQ, Low Jitter and DP++ Level Shifter bP Lead-free Green Notes: 1. No purposely added lead. Fully EU Directive 2002/95/EC (RoHS), 2011/65/EU (RoHS 2) & 2015/863/EU (RoHS 3) compliant. 2. See https://www.diodes.com/quality/lead-free/ for more information about Diodes Incorporated’s definitions of Halogen- and Antimony-free, "Green" and Lead-free. 3. Halogen- and Antimony-free "Green” products are defined as those which contain <900ppm bromine, <900ppm chlorine (<1500ppm total Br + Cl) and <1000ppm antimony compounds.

© 2023 Copyright Diodes Incorporated. All Rights Reserved. PI3HDX1204B1 Document Number DS42401 Rev 5-2 www.diodes.com 2. General Information

2.1 Revision History

July 2016 − Application chapter: Updated reference schematics in application chapter. Add load switch AP2151 requirement to protect sink to source-side devices back drive. Sep 2016 − Finial datasheet release with package pin-out typo fixed - pin name 30, 37 and 38 Dec 2016 − Correct typos by removing Threshold detector VTH1/0, Output Swing Control VOD0 table in the func - tional description. Those pins do not bond out in PI3HDX1204B1. Jan 2017 − In Fig 6-6 sink application circuit, removed load switch and regulator. Oct 2017 − Ch2. Similar product comparison table added. Nov 2019 1 Updated Section 1 Description Updated Section 6.2 Recommended Operation Conditions Updated Section 6.3.5 Switching Characteristics Nov 2019 2 Updated Section 5.1 Address Assignment Dec 2019 3 Updated Section 6.3.2 Power Dissipation Nov 2020 4 Updated Section 4.2.5 Output Voltage Swing Setting Nov 2023 5 Added Section 4.2.2 Signal Detector Updated Typo, VCC and I2C

© 2023 Copyright Diodes Incorporated. All Rights Reserved. PI3HDX1204B1 Document Number DS42401 Rev 5-2 www.diodes.com

Contents

© 2023 Copyright Diodes Incorporated. All Rights Reserved. PI3HDX1204B1 Document Number DS42401 Rev 5-2 www.diodes.com 3. Pin Configuration 18 19 20 21 42 41 40 39 DE1 DE0 VCC A0RX+ A0RX- A1RX+ A1RX- VCC A2RX+ A2RX- GND A3RX+ A3RX- VCC NC NC A0TX- VCC A0TX+ VCC A1TX+ A2TX+ A1TX- GND A2TX- VCC VCC A3TX+ A3TX- VOD1 SDA SCL PEN PIN_MODE BST3 BST2 BST1 BST0 GND Figure 3-1 Package Pin-out (Top-Side View)

© 2023 Copyright Diodes Incorporated. All Rights Reserved. PI3HDX1204B1 Document Number DS42401 Rev 5-2 www.diodes.com Table 3-1. Pin Description Pin # Pin Name Type Description Data Signals A0RX+ A0RX- I TMDS inputs for Channel A0, with internal 50Ω Pull-Up and ~200kΩ Pull-Up otherwise. A0TX+, A0TX- O TMDS outputs for Channel A0, with internal 50Ω Pull-Up and ~2kΩ Pull-Up otherwise. A1RX+, A1RX- I TMDS inputs for Channel A1, with internal 50Ω Pull-Up and ~200kΩ Pull-Up otherwise. A1TX+, A1TX- O TMDS outputs for Channel A1, with internal 50Ω Pull-Up and ~2kΩ Pull-Up otherwise. A2RX+, A2RX- I TMDS inputs for Channel A2, with internal 50Ω Pull-Up and ~200kΩ Pull-Up otherwise. A2TX+, A2TX- O TMDS outputs for Channel A2, with internal 50Ω Pull-Up and ~2kΩ Pull-Up otherwise. A3RX+, A3RX- I TMDS inputs for Channel A3, with internal 50Ω Pull-Up and ~200kΩ Pull-Up otherwise. A3TX+, A3TX- O TMDS outputs for Channel A3, with internal 50Ω Pull-Up and ~2kΩ Pull-Up otherwise. Control Signals 19 SCL I I2C Clock input. 18 SDA I/O I2C Data input/output. 17, 16, A4, A1, I I2C programmable address bits, with internal 100kΩ Pull-Up.

20 PEN I Power Enable with internal 100KΩ Pull-Up

21 Pin_Mode I Input with internal 100kΩ Pull-Up. When HIGH, each channel is programmed by the exter - nal pin voltage. When LOW, each channel is programmed by the data stored in the I 2C bus. BST[3:0] I Inputs with internal 100kΩ Pull-Up. This pins set the amount of Equalizer Boost in all chan - nel when Pin mode is HIGH. 23 VOD1 I Inputs with internal 100kΩ Pull-Up. This pin sets the output Voltage Level in all channel when Pin mode is HIGH. 2 DE[1:0] I Inputs with internal 100kΩ Pull-Up. This pins set the output De-Emphasis Level in all chan - nel when Pin_Mode is HIGH. 38, 37 NC NC Not Connected Power Pins 6, 12, 30, Center Pad GND GND Ground Pins 3, 9, 15, 24, 27, 33, 36 VCC PWR Power Supply Pins

© 2023 Copyright Diodes Incorporated. All Rights Reserved. PI3HDX1204B1 Document Number DS42401 Rev 5-2 www.diodes.com 4. Functional Description

4.1 Functional Block Diagram

Control Logic/Configuration Registers I2C Slave 50Ω or 2KΩ 50Ω or 200KΩ VCCVCC Output Driver Pin_Mode SDA/SCL TxRx De-emp De-emp Voltage Swing Buffer DE[1:0] A0, A1, A4 VOD1 Equalization BST[3:0] Figure 4-1 Functional Block Diagram

4.2 Function Settings

4.2.1 Output Termination Detector

On power up or when PEN becomes true, the output resistance is set to 2K ohms, and the input resistance is set to 200K ohms. The device continually looks to detect an external 50 ohm termination resistor on a per channel basis. If no 50 ohms is detected in the first 5ms of time, the channel is continually polled with 5ms detection cycle until detection occurs.

4.2.2 Signal Detector

The signal detector is used to detects whether the RX terminal has any valid input signal or not. If the input differential signal is lower than Vth-, then it has no output; if the input differential signal is higher than Vth+, then ReDriver will output the received signal.

4.2.3 Power Enable Function

One pin control or I2C control, when PEN is set to low, the IC goes into power down mode, both input and output termination set to 200K and 2K respectively. Individual Channel Enabling is done through the I2C register programming.

4.2.4 Equalization Setting

BST[3:0] are the selection pins for the equalization selection for each channel.

© 2023 Copyright Diodes Incorporated. All Rights Reserved. PI3HDX1204B1 Document Number DS42401 Rev 5-2 www.diodes.com Table 4-1. Table 1. Equalization Setting BST3 BST2 BST1 BST0 6Gbps (3GHz) 8Gbps (4GHz) 0 0 0 0 0.25 dB 0.4 dB 0 0 0 1 0.8 dB 1.1 dB 0 0 1 0 1.1 dB 1.6 dB 0 0 1 1 2.2 dB 3.1 dB 0 1 0 0 4.1 dB 5.4 dB 0 1 0 1 7.1 dB 8.9 dB 0 1 1 0 9.0 dB 10.8 dB 0 1 1 1 10.3 dB 12.2 dB 1 0 0 0 11.8 dB 13.8 dB 1 0 0 1 13.9 dB 15.8 dB 1 0 1 0 15.3 dB 17.3 dB 1 0 1 1 16.9 dB 19.0 dB 1 1 0 0 17.9 dB 20.0 dB 1 1 0 1 19.2 dB 21.3 dB 1 1 1 0 20.5 dB 22.6 dB 1 1 1 1 22.2 dB 24.3 dB

4.2.5 Output De-emphasis Setting

De-emphasis Setting: DE[1:0] are the selection bits for the de-emphasis value. Table 4-2. Output De-emphasis Setting DE1 DE0 De-emphasis 0 0 0 dB 0 1 -0.5 dB 1 0 -0.7 dB 1 1 -1.0 dB

4.2.6 Output Voltage Swing Setting

Swing Setting: VOD1, VOD0 are the selection bits for the output swing voltage value. Table 4-3. Output Voltage Swing Setting VOD1 VOD0 Output Voltage Swing 0 0 0.8 Vppd 0 1 0.95 Vppd 1 0 1.15 Vppd 1 1 1.3 Vppd

© 2023 Copyright Diodes Incorporated. All Rights Reserved. PI3HDX1204B1 Document Number DS42401 Rev 5-2 www.diodes.com

4.3 Output Eye Diagram Changes with Different EQ Setting

Figure 4-2 Eye Width vs. Input Equalization at Different Input trace Lengths Figure 4-3 Eye Height vs. Input Equalization at Different Input trace Lengths

© 2023 Copyright Diodes Incorporated. All Rights Reserved. PI3HDX1204B1 Document Number DS42401 Rev 5-2 www.diodes.com Table 4-4. Input Eye Diagram without Trace Boards 6-in trace 18-in trace 24-in trace 30-in trace 36-in trace Table 4-5. Output Eye Opening with Trace and Different EQ Settings, 6.0Gbps, VCC = 3.3V , 25C 6-in trace EQ=0001 (0.8dB) 12-in trace EQ=0100(4.1dB) 18-in trace EQ=0110(9.0dB) 24-in trace EQ=0111(10.3dB) 30-in trace EQ=0111(10.3dB) 48-in trace EQ=1000(11.8dB) Note: Trace Card Loss Informations is shown below. Frequency 3GHz 6GHz Units 6 inch Input Trace -2.1 -4 dB 12 inch Input Trace -4 -7.5 dB 18 inch Input Trace -6.1 -11.3 dB 30 inch Input Trace -10.14 -18 dB 36 inch Input Trace -12.13 -22 dB 48 inch Input Trace -16.42 -29 dB

© 2023 Copyright Diodes Incorporated. All Rights Reserved. PI3HDX1204B1 Document Number DS42401 Rev 5-2 www.diodes.com 5. I2C Programming

5.1 Address Assignment

Pin# A4 0 0 Program Controlled by Pin# A1 Program Controlled by Pin# A0 1=R, 0=W BYTE 0 : Reserved BYTE 1 Bit Type Power up condition Control affected Comment [7:0] R 0 Not used BYTE 2 Bit Type Power up condition Control affected Comment

7 R/W

Latch from PEN input at startup Ch3 Enable 1 = Enable

6 R/W Ch2 Enable

5 R/W Ch1 Enable

4 R/W Ch0 Enable

[3:0] R/W 0 Not used BYTE 3 Bit Ty pe Power up condition Control affected Comment Latch from BST[3:0] at startup BST3 Ch1

6 R/W BST2 Ch1

5 R/W BST1 Ch1

4 R/W BST0 Ch1

3 R/W BST3 Ch0

2 R/W BST2 Ch0

1 R/W BST1 Ch0

0 R/W BST0 Ch0

© 2023 Copyright Diodes Incorporated. All Rights Reserved. PI3HDX1204B1 Document Number DS42401 Rev 5-2 www.diodes.com BYTE 4 Bit Ty pe Power up condition Control affected Comment Latch from BST[3:0] at startup BST3 Ch3

6 R/W BST2 Ch3

5 R/W BST1 Ch3

4 R/W BST0 Ch3

3 R/W BST3 Ch2

2 R/W BST2 Ch2

1 R/W BST1 Ch2

0 R/W BST0 Ch2

Bit Ty pe Power up condition Control affected Comment

7 R/W Latch from VOD1 at startup VOD1 Ch3

6 R/W VOD0 = "1" VOD0 Ch3

5 R/W Latch from VOD1 at startup VOD1 Ch2

4 R/W VOD0 = "1" VOD0 Ch2

3 R/W Latch from VOD1 at startup VOD1 Ch1

2 R/W VOD0 = "1" VOD0 Ch1

1 R/W Latch from VOD1 at startup VOD1 Ch0

0 R/W VOD0 = "1" VOD0 Ch0

Bit Ty pe Power up condition Control affected Comment Latch from DE[1:0] at startup DE1 Ch3

6 R/W DE0 Ch3

5 R/W DE1 Ch2

4 R/W DE0 Ch2

3 R/W DE1 Ch1

2 R/W DE0 Ch1

1 R/W DE1 Ch0

0 R/W DE0 Ch0

BYTE 7-9 : Reserved BYTE A-F : Reserved

© 2023 Copyright Diodes Incorporated. All Rights Reserved. PI3HDX1204B1 Document Number DS42401 Rev 5-2 www.diodes.com

5.2 I2C Data Transfer Sequence

Notes: 1. only block read and block write from the lowest byte are supported for this application. 2. for some I C application, an offset address byte will be presented at the second byte in write command, which is called dummy byte here and will be simply ignored in this application for correct interoperation. I C Slave Device Address

© 2023 Copyright Diodes Incorporated. All Rights Reserved. PI3HDX1204B1 Document Number DS42401 Rev 5-2 www.diodes.com 6. Electrical

6.1 Absolute Maximum Ratings

6.2 Recommended Operation Conditions

Parameter Min. Typ. Max Units Power supply voltage (VCC to GND)(1) 3.0 3.3 3.6 V I2C (SDA, SCL) 3.6 V Supply Noise Tolerance up to 25 MHz(2) 100 mVp-p Ambient Temperature Industrial Temperature Range -40 85 Commercial Temperature Range 0 70 Note 1. Typical parameters are measured at VCC = 3.3 ± 0.3V , TA = 25°C. They are for the reference purposes, and are not production-tested 2. Allow supply noise (mVp-p sine wave) under typical condition

6.3 DC/AC Characteristics

6.3.1 LVCMOS DC Specifications

Symbol Parameter Conditions Min. Typ. Max Unit VIH DC input logic high VCC/2 + 0.7 VCC + 0.3 V VIL DC input logic low -0.3 VCC/2 - 0.7 V VOH At IOH = -200µA VCC + 0.2 V VOL At IOL = -200µA 0.2 V Vhys Hysteresis of Schmitt trigger input 0.8 V

6.3.2 Power Dissipation

Symbol Parameter Conditions Min. Typ. Max. Units Imax Supply Current PEN = 1, EQ = 0dB, De-emphasis = 0dB, All 4 channels 0.8V Swing 265 325 mA PEN = 1, EQ = 0dB, De-emphasis = 0dB, All 4 channels 1.3V Swing 300 350 mA IDDQ Quiescent Supply Current PEN = 0, high speed TMDS channels disabled 0.3 mA Note Stresses greater than those listed under MAXIMUM RAT- INGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for ex - tended periods may affect reliability.

© 2023 Copyright Diodes Incorporated. All Rights Reserved. PI3HDX1204B1 Document Number DS42401 Rev 5-2 www.diodes.com

6.3.3 Package Power Ratings

Package Theta Ja(still air) (°C/W) Theta Jc (°C/W) Max. Power Dissipation Rating (Ta ≤ 70°) 42-pin TQFN (ZH42) 33.69 15.17 1.63W

6.3.4 TMDS Differential Pins

Symbol Parameter Conditions Min. Typ. Max. Units VOH Single-ended High Level Output Voltage VCC = 3.3V , Rout = 50Ω VCC-10 VCC+10 mV VOL Single-ended Low Level Output Voltage VCC-600 VCC-400 mV Vswing Output Voltage Swing 700 1300 mVppd RT Input Termination Resistance VIN = 2.9V 45 50 55 Ω IOZ Leakage Current with Hi-Z I/O VCC = 3.6V 10 uA

6.3.5 Switching Characteristics

Symbol Parameter Conditions Min. Typ. Max. Units Tpd Propagation Delay 2000 ps Tr Tx Signal Rise Time (20% - 80%) VCC = 3.3V , RT = 50Ω, Pre-/De-emp = 0dB 40 ps Tf Tx Signal Fall Time (80% - 20%) 40 ps Tsk(p) Pulse Skew 10 50 ps Tsk(D) Intra-pair Differential Skew 23 50 ps Tsk(O) Inter-pair Differential Skew 100 ps TJit-Clk Peak-to-peak Output Jitter for Clock channel Pre-/De-emp = 0dB Data Input = 6Gbps HDMI Pattern, Clock input = 150MHz 15 30 ps TJit-Data Peak-to-peak Output Jitter for Data channels 18 50 ps tsx Select to switch Output 10 ns ten Enable Time 200 ns tdis Disable Time 10 ns

6.3.6 Signal Detector

Symbol Parameter Conditions Min. Typ. Max. Units Vth+ Assert Threshold of Signal Detector Signal swing @ 3GHz 130 210 mVppd Vth- De-assert Threshold of Signal Detector Signal swing @ 100 MHz 30 110 mVppd

© 2023 Copyright Diodes Incorporated. All Rights Reserved. PI3HDX1204B1 Document Number DS42401 Rev 5-2 www.diodes.com Figure 6-4 HDMI Source Test Point for Eye Diagram Figure 6-5 HDMI Sink Test Point for Eye Diagram

6.4 I2C Bus

Symbol Parameter Conditions Min. Typ. Max Units VCC Nominal Bus Voltage 3.0 3.6 V Freq Bus Operation Frequency 400 kHz VIH DC input logic high VCC/2 + 0.7 VCC + 0.3 V VIL DC input logic low -0.3 VCC/2 - 0.7 V VOL DC output logic low IOL = 3mA 0.4 V Ipullup Current Through Pull-Up Resistor or Cur- rent Source High Power specifi- cation 3.0 3.6 mA

© 2023 Copyright Diodes Incorporated. All Rights Reserved. PI3HDX1204B1 Document Number DS42401 Rev 5-2 www.diodes.com Symbol Parameter Conditions Min. Typ. Max Units Ileak-bus Input leakage per bus segment -200 200 uA Ileak-pin Input leakage per device pin -15 uA CI Capacitance for SDA/SCL 10 pF tBUF Bus Free Time Between Stop and Start condition 1.3 us tHD:STA Hold time after (Repeated) Start condition. After this period, the first clock is gener - ated. At pull-up, Max 0.6 us tSU:STA Repeated start condition setup time 0.6 us tSU:STO Stop condition setup time 0.6 us tHD:DAT Data hold time 0 ns tSU:DAT Data setup time 100 ns tLOW Clock low period 1.3 us tHIGH Clock high period 0.6 50 us tf Clock/Data fall time 300 ns tr Clock/Data rise time 300 ns tPOR Time in which a device must be operation after power-on reset 500 ms Note: 1. Recommended maximum capacitance load per bus segment is 400pF . 2. Compliant to I2C physical layer specification. 3. Ensured by Design. Parameter not tested in production. SDA SCL tf S tHD;STA tLOW tHD;DAT tSU;DAT HIGH tSU;STA tHD;STA Sr tSU;STO P S tf tr tBUF START STOP START t Figure 6-6 I2C Timing Diagram

© 2023 Copyright Diodes Incorporated. All Rights Reserved. PI3HDX1204B1 Document Number DS42401 Rev 5-2 www.diodes.com 7. Application/Implementation Note Information in the following applications sections is not part of the component specification, and does not warrant its accuracy or com- pleteness. Customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality.

7.1 Source Application

PI3HDX1204B1 is designed to accept AC-coupled as well as DC-coupled main link signals. When a dual-mode DP source is connected to the input of PI3HDX1204B1 in a source application, AC coupling capacitors must be placed at the input side. Title Size Document Number Rev Date: Sheet of A PI3HDX1204B1 Source Application Diagram 1 1Tuesday, July 05, 2016 Common Mode Choke 0.1u_0402 0.1u_0402 50 50 DDC Switch / Buffer 47K 20K HPD(5V ) A xRX+ A xRX- HPD(3V 3) 50 50 V DD 2K 2K +5V SD A(5V) SCL(5V) V DDVDD AP2151 +3.3V_SYS Load Switch PI6ULS5V9617 HDMI Connector Dual-mode DP Source AxTX- Pin_Mode, A[4,1:0] AxTX+ BST[3:0], DE[1:0], PS[1:0], VOD[1:0] SCL(3.3V) SDA(3.3V) 10K 10K PI3HDX1204B1 +3V3 ESD Protector PEN Figure 7-1 PI3HDX1204B1 Source Application Circuit

7.1.1 ESD Protectors on Output TMDS

As 8kV contact ESD is commonly required, ESD protectors are implemented at the output TMDS pins of PI3HDX1204B1 for source

7.1.2 Extra Component for Rise/fall Time Control

Per HDMI2.0 specification, rise/fall time of TMDS clock is kept at minimal 75ps while that of TMDS data is decreased to minimal 42.5ps if data rate is between 3.4Gbps and 6Gbps. Figure 7-2 HDMI2.0 Trise/fall Requirement PI3HDX1204B1 is designed to meet the rise/fall time of TMDS data. If output trace length is short, maybe 1” only, common-mode choke or external inductor can be considered for slowing down the rise/fall time for TMDS clock of PI3HDX1204B1. VCC VCC VCC

© 2023 Copyright Diodes Incorporated. All Rights Reserved. PI3HDX1204B1 Document Number DS42401 Rev 5-2 www.diodes.com

7.1.3 Leakage Blockage for VOFF Test

When performing VOFF test specified in HDMI 1.4a Compliance Test Specification, each output TMDS of PI3HDX1204B1 will be pulled to 3.3V via an external 50Ω resistor. In this case, current will pass through an internal ESD protector at the output TMDS pin of PI3HDX1204B1 and leakage will be found at VCC pin of PI3HDX1204B1. Figure 7-3 HDMI VOFF Test Setup Figure 7-4 HDMI VOFF Requirement To avoid this leakage, AP2151A power switch can be employed between the main 3.3V supply on a system and the VCC power plane of PI3HDX1204B1. Below is an example borrowed from an evaluation board schematic. Figure 7-5 Power Distribution Switch Example 7 .2 Sink Application PI3HDX1204B1 can also be employed in a sink application as it offers a range of equalization setting.

© 2023 Copyright Diodes Incorporated. All Rights Reserved. PI3HDX1204B1 Document Number DS42401 Rev 5-2 www.diodes.com VDD ESD Protector 50 50 +5V +5V AxRX+ HPD AxRX- SCL, SDA and HPD of the HDMI scalar chipset are assumed 5V tolerant. 50 50 BST[3:0], DE[1:0], PS[1:0], VOD[1:0] 47K 47K +5V HDMI Connector HDMI Scalar Chipset AxTX- Pin_Mode, A[4, 1:0] AxTX+ PEN +5V PI3HDX1204B1 SDA SCL VDD Figure 7-6 PI3HDX1204B1 Sink Application Circuit

7.2.1 ESD Protectors on Output TMDS

ESD protector selection guidance for source and sink applications is the same. VCC VCC

© 2023 Copyright Diodes Incorporated. All Rights Reserved. PI3HDX1204B1 Document Number DS42401 Rev 5-2 www.diodes.com 7 .3 DC/AC-coupled Application A0RX+ A0RX- A0TX+ A0TX- 50Ω50Ω VBias High-speed differential signal traces 4.7nF A0RX+ A0RX- A0TX+ A0TX- 50Ω50Ω 4.7nF VBias AC-Coupled Differential Signaling Application Circuits DC-Coupled Differential Signaling Application Circuits 50Ω50Ω VCC 50Ω50Ω VCC Receiver Receiver GND GND GND Figure 7-7 DC/AC-coupled Application Diagram 7 .4 Product Layout Guideline

7.4.1 AC Coupling Capacitor

Below is an example of placing AC coupling capacitors on high-speed channels

© 2023 Copyright Diodes Incorporated. All Rights Reserved. PI3HDX1204B1 Document Number DS42401 Rev 5-2 www.diodes.com Figure 7-8 AC Coupling Capacitor Placement

7.4.2 Output Trace Length

To fulfill minimal 75ps rise/fall time requirement of TMDS clock, 1.5 – 4.5” TMDS trace length between PI3HDX1204B1 and HDMI connector for source application is recommended. This trace length varies with PCB trace width, characteristics of common-mode choke/ESD protector and connector quality. If trace width is 5 mil, 2.7 – 3.3” is recommended. Isolation space should be larger than 5 mil to minimize the crosstalk so thus jitter. Below is the PI3HDX1204B1 placement on its evaluation board. Figure 7-9 Source-side Placement near to the HDMI Connectors

7.4.3 Differential Impedance (TDR)

Layout guideline especially for high-speed transmission is critical. Please refer to PI3DPxxx_PI3HDxxx_Layout Guideline for detailed recommendations. Differential impedance test is required for both source and sink applications per HDMI 2.0 specification. Figure 7-10 HDMI2.0 Differential Impedance Requirement for Source Application

© 2023 Copyright Diodes Incorporated. All Rights Reserved. PI3HDX1204B1 Document Number DS42401 Rev 5-2 www.diodes.com Figure 7-11 HDMI2.0 Differential Impedance Requirement for Sink Application The PCB impedance immediately before and after an ESD protector must be adjusted to compensate the capacitance loading of the ESD protector. Below is an example designing RClampe0544M in PI3HDX1204B1 evaluation board. Trace impedances before and after the ESD protector are tuned to compensate the capacitance of RClamp0544M. Semtech’s layout guideline is followed. Figure 7-12 ESD Protector on PI3HDX1204B1 Source EVB

7.4.4 GND via on the Thermal Pad Area

Several GND via are “MUST” required on thermal area. The via size is 12/24 mil. Below is the thermal pad via layout recommendation. Figure 7-13 Recommended Land Patterns

© 2023 Copyright Diodes Incorporated. All Rights Reserved. PI3HDX1204B1 Document Number DS42401 Rev 5-2 www.diodes.com 7 .5 General Layout Guideline As transmission data rate increases rapidly, any flaws and/or mis-matches on PCB layout are amplified in terms of signal integrity. Lay- out guideline for high-speed transmission is highlighted in this application note.

7.5.1 Power and Ground

To provide a clean power supply for Pericom high-speed device, few recommendations are listed below:

• Power (VCC) and ground (GND) pins should be connected to corresponding power planes of the printed circuit board directly without passing through any resistor.
• The thickness of the PCB dielectric layer should be minimized such that the VCC and GND planes create low inductance paths.
• One low-ESR 0.1uF decoupling capacitor should be mounted at each VCC pin or should supply bypassing for at most two VCC pins. Capacitors of smaller body size, i.e. 0402 package, is more preferable as the insertion loss is lower. The capacitor should be placed next to the VCC pin.
• One capacitor with capacitance in the range of 4.7uF to 10uF should be incorporated in the power supply decoupling design as well. It can be either tantalum or an ultra-low ESR ceramic.
• A ferrite bead for isolating the power supply for Pericom high-speed device from the power supplies for other parts on the printed circuit board should be implemented.
• Several thermal ground vias must be required on the thermal pad. 25-mil or less pad size and 14-mil or less finished hole are rec - ommended. G N D P la ne VIN V CC P la ne 10uF 1uF 0.1uF 0.1uF 0.1uF Bypass noise Power Flow VIN VIN Center Pad GND Plane Several Thermal GND Vias must be required on the Thermal Pad area Figure 7-14 Decoupling Capacitor Placement Diagram

7.5.2 High-speed Signal Routing

Well-designed layout is essential to prevent signal reflection:

• For 90Ω differential impedance, width-spacing-width micro-strip of 6-7-6 mils is recommended; for 100Ω differential impedance, width-spacing-width micro-strip of 5-7-5 mils is recommended.
• Differential impedance tolerance is targeted at ±15%.

© 2023 Copyright Diodes Incorporated. All Rights Reserved. PI3HDX1204B1 Document Number DS42401 Rev 5-2 www.diodes.com 7 .6 CTS Test Report 7.6.1 HDMI 2.0 Compliance Test Set-up Figure 7-24 HDMI 2.0 CTS Test Setup Note: Application Trace Card Information for CTS test HDMI FR4 trace 0 in 6 in 12 in 18 in 24 in 30 in 36 in

© 2023 Copyright Diodes Incorporated. All Rights Reserved. PI3HDX1204B1 Document Number DS42401 Rev 5-2 www.diodes.com 7.6.2 HDMI 2.0 Compliance Report

© 2023 Copyright Diodes Incorporated. All Rights Reserved. PI3HDX1204B1 Document Number DS42401 Rev 5-2 www.diodes.com 8. Mechanical/Packaging Information

8.1 Mechanical

For latest package info. please check: http://www.diodes.com/design/support/packaging/pericom-packaging/packaging-mechanicals-and-thermal-characteristics/

© 2023 Copyright Diodes Incorporated. All Rights Reserved. PI3HDX1204B1 Document Number DS42401 Rev 5-2 www.diodes.com

8.2 Part Marking Information

Our standard product mark follows our standard part number ordering information, except for those products with a speed letter code. The speed letter code mark is placed after the package code letter, rather than after the device number as it is ordered. After electrical test screening and speed binning has been completed, we then perform an “add mark” operation which places the speed code letter at the end of the complete part number. PI X XXX XXXX X XX E X Family DPX = Displayport HDX = HDMI VDP = ++DP Level Shifter Voltage Info: 2 = 1.2V to 1.8V; 3 = 3.3V PI = Pericom Blank = Tube; X = Tape & Reel Version Number (not always present) Package Code Blank = Standard; E = Pb-free & Green Device Number Figure 8-1 Device Naming Information PI3HDX 1204B1ZHE YYWWXX PI: Pericom 3HDX: 3.3V HDMI Product Family 1204B1: Part Number ZH: Package Code E: Pb-Free and Green YY: Year WW: Workweek 1st X: Assembly Code 2nd X: Fab Code Figure 8-2 Device Marking Information

© 2023 Copyright Diodes Incorporated. All Rights Reserved. PI3HDX1204B1 Document Number DS42401 Rev 5-2 www.diodes.com

8.3 Tape & Reel Materials and Design

The Pocketed Carrier Tape is made of Conductive Polystyrene plus Carbon material (or equivalent). The surface resistivity is 10 6Ohm/sq. maximum. Pocket tapes are designed so that the component remains in position for automatic handling after cover tape is removed. Each pocket has a hole in the center for automated sensing if the pocket is occupied or not, thus facilitating device removal. Sprocket holes along the edge of the center tape enable direct feeding into automated board assembly equipment. See Figures 3 and 4 for carrier tape dimensions. Cover Tape Cover tape is made of Anti-static Transparent Polyester film. The surface resistivity is 107Ohm/Sq. Minimum to 1011Ohm sq. maximum. The cover tape is heat-sealed to the edges of the carrier tape to encase the devices in the pockets. The force to peel back the cover tape from the carrier tape shall be a MEAN value of 20 to 80gm (2N to 0.8N). Reel The device loading orientation is in compliance with EIA-481, current version (Figure 2). The loaded carrier tape is wound onto either a 13- inch reel, (Figure 4) or 7-inch reel. The reel is made of Antistatic High-Impact Polystyrene. The surface resistivity 107Ohm/sq. minimum to 1011Ohm/sq. max. NOTE: LABELS TO BE PLACED ON THE REEL OPPOSITE PIN 1 TOP COVER TAPE SPROCKET HOLE (ROUND) CARRIER TAPE EMBOSSED CAVITY BARCODE LABEL Figure 8-3 Tape & Reel label Information END CARRIER TAPE TRAILER COVER TAPE COMPONENTS COVER TAPE START LEADER Top Left PIN 1 ORIENTATION Top Right PIN 1 ORIENTATION Bottom Left PIN 1 ORIENTATION Figure 8-4 Tape leader and Trailer Pin 1 Orientation

© 2023 Copyright Diodes Incorporated. All Rights Reserved. PI3HDX1204B1 Document Number DS42401 Rev 5-2 www.diodes.com Cover Tape Round Sprocket Holes (10 pitches cumulative tolerance on tape ±0.2mmDo Po F Ao So Bo W Embossed Cavity Center lines of Cavity Direction of Unreeling T B1 Ko R (min) Figure 8-5 Standard Embossed Carrier Tape Dimension Constant Dimensions Tape Size D0 D1 (Min) E1 P0 P2 R (See Note 2) S1 (Min) T (Max) (Max) 8mm 1.5 +0.1 -0.0 1.0 1.75 ± 0.1 4.0 ± 0.1 2.0 ± 0.05 0.6 0.6 0.1 12mm 1.5 3016mm 2.0 ± 0.124mm 32mm 2.0 50 N/A (See Note 3)44mm 2.0 ± 0.15 Variable Dimensions Tape Size P1 B1 (Max) E2 (Min) F So T2 (Max.) W (Max) A0, B0, & K0 8mm Specific per package type. Re- fer to FR-0221 (Tape and Reel Packing Information) or visit www.pericom.com/pdf/gen/ tapereel.pdf 4.35 6.25 3.5 ± 0.05 N/A (see note 2.5 8.3 See Note 1 NOTES: 1. A0, B0, and K0 are determined by component size. The cavity must restrict lateral movement of component to 0.5mm maximum for 8mm and 12mm wide tape and to 1.0mm maximum for 16,24,32, and 44mm wide carrier. The maximum component rotation within the cavity must be limited to 20o maximum for 8 and 12 mm carrier tapes and 10o maximum for 16 through 44mm. 2. Tape and components will pass around reel with radius “R” without damage. 3. S1 does not apply to carrier width ≥32mm because carrier has sprocket holes on both sides of carrier where Do≥S1. 4. So does not exist for carrier ≤32mm because carrier does not have sprocket hole on both side of carrier.

© 2023 Copyright Diodes Incorporated. All Rights Reserved. PI3HDX1204B1 Document Number DS42401 Rev 5-2 www.diodes.com D B C Access Hole at Slot Location (40 mm min Dia) W2(measured at hub) W1(measured at hub) Width=2.5mm Min, Depth=10.0mm Min A Figure 8-6 Reel Dimensions Reel Dimensions by Tape Size Tape Size A N (Min) (1) W1 W2(Max) W3 B (Min) C D (Min) 8mm 178±2.0mm or 330±2.0mm 60 ±2.0mm or 100±2.0mm Shall Accom- modate Tape Width Without Interference 1.5mm 13.0 +0.5/-0.2 mm 20.2mm 12mm 12.4 +2.0/-0.0 mm 18.4 mm 16mm 330±2.0mm 100 ±2.0mm 24mm 24.4 +2.0/-0.0 mm 30.4 mm 32mm 32.4 +2.0/-0.0 mm 38.4 mm 44mm 44.4 +2.0/-0.0 mm 50.4 mm NOTE: diameter (N(min)) will by 100±2.0mm.

© 2023 Copyright Diodes Incorporated. All Rights Reserved. PI3HDX1204B1 Document Number DS42401 Rev 5-2 www.diodes.com 9. Important Notice 1. DIODES INCORPORATED (Diodes) AND ITS SUBSIDIARIES MAKE NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH RE - GARDS TO ANY INFORMATION CONTAINED IN THIS DOCUMENT, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MER - CHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD PARTY INTELLECTUAL PROPERTY RIGHTS (AND THEIR EQUIVALENTS UNDER THE LAWS OF ANY JURISDICTION). 2. The Information contained herein is for informational purpose only and is provided only to illustrate the operation of Diodes’ products described herein and application examples. Diodes does not assume any liability arising out of the application or use of this document or any product described herein. This document is intended for skilled and technically trained engineering customers and users who design with Diodes’ products. Diodes’ prod - ucts may be used to facilitate safety-related applications; however, in all instances customers and users are responsible for (a) selecting the appropriate Diodes products for their applications, (b) evaluating the suitability of Diodes’ products for their intended applications, (c) ensuring their applications, which incorporate Diodes’ products, comply the applicable legal and regulatory requirements as well as safety and functional-safety related standards, and (d) ensuring they design with appropriate safeguards (including testing, validation, quality control techniques, redundancy, malfunction prevention, and appropriate treatment for aging degradation) to minimize the risks associated with their applications. 3. Diodes assumes no liability for any application-related information, support, assistance or feedback that may be provided by Diodes from time to time. Any customer or user of this document or products described herein will assume all risks and liabilities associated with such use, and will hold Diodes and all companies whose products are represented herein or on Diodes’ websites, harmless against all damages and liabilities. 4. Products described herein may be covered by one or more United States, international or foreign patents and pending patent applications. Product names and markings noted herein may also be covered by one or more United States, international or foreign trademarks and trademark ap - plications. Diodes does not convey any license under any of its intellectual property rights or the rights of any third parties (including third parties whose products and services may be described in this document or on Diodes’ website) under this document. 5. Diodes’ products are provided subject to Diodes’ Standard Terms and Conditions of Sale (https://www.diodes.com/about/company/terms- and-conditions/terms-and-conditions-of-sales/) or other applicable terms. This document does not alter or expand the applicable warranties provided by Diodes. Diodes does not warrant or accept any liability whatsoever in respect of any products purchased through unauthorized sales channel. 6. Diodes’ products and technology may not be used for or incorporated into any products or systems whose manufacture, use or sale is prohib- ited under any applicable laws and regulations. Should customers or users use Diodes’ products in contravention of any applicable laws or regulations, or for any unintended or unauthorized application, customers and users will (a) be solely responsible for any damages, losses or penalties arising in connection therewith or as a result thereof, and (b) indemnify and hold Diodes and its representatives and agents harmless against any and all claims, damages, expenses, and attorney fees arising out of, directly or indirectly, any claim relating to any noncompliance with the applicable laws and regula- tions, as well as any unintended or unauthorized application. 7. While efforts have been made to ensure the information contained in this document is accurate, complete and current, it may contain technical inaccuracies, omissions and typographical errors. Diodes does not warrant that information contained in this document is error-free and Diodes is under no obligation to update or otherwise correct this information. Notwithstanding the foregoing, Diodes reserves the right to make modifications, enhance - ments, improvements, corrections or other changes without further notice to this document and any product described herein. This document is written in English but may be translated into multiple languages for reference. Only the English version of this document is the final and determinative format released by Diodes. 8. Any unauthorized copying, modification, distribution, transmission, display or other use of this document (or any portion hereof) is prohibited. Diodes assumes no responsibility for any losses incurred by the customers or users or any third parties arising from any such unauthorized use. 9. This Notice may be periodically updated with the most recent version available at https://www.diodes.com/about/company/terms-and-conditions/ important-notice The Diodes logo is a registered trademark of Diodes Incorporated in the United States and other countries. All other trademarks are the property of their respective owners. © 2023 Diodes Incorporated. All Rights Reserved. www.diodes.com