Features
Document overview
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Technical content
Features
ÎÎ High-speed serial link with linear equalizer ÎÎ Support PCIe Gen 1/2/3 protocol, 10GbE, SATA3, SAS3 ÎÎ Supporting 8 differential channels ÎÎ Independent channel configuration of receiver equalization, output swing and flat gain ÎÎ Per Channel Activity Detector with selectable input termination between 50Ω to V DD and 200KΩ to VDD ÎÎ Per Channel Output Termination Detector on power up with selectable output termination between 50Ω to V DD and High impedance ÎÎ Very linear transfer function ÎÎ Fully compliant to PCISIG Link Training ÎÎ Single-ended mode receiver detection for PCIe ÎÎ Input Threshold detection ÎÎ Pin strap and I2C master/slave selectable device programming with external EEPROM ÎÎ 4-bit selectable address bit for I2C ÎÎ Supply Voltage: 3.3V±0.3V ÎÎ Industrial Temperature Range: -40 oC to 85oC ÎÎ Packaging (Pb-free & Green): à 54-contact TQFN (10mm x 5.5mm x 0.5mm pitch) - flowthrough pinout
Description
The PI3EQX12908A2 is an 8-channel PCIe Gen 2, 10GbE, SATA3, ReDriver™. The device provides programmable linear equaliza - tion, output swing and gain, by either pin strapping option or I 2C Control, to optimize performance over a variety of physical mediums by reducing Inter-symbol interference. The PI3EQX12908A2 supports eight 100-Ohm Differential CML data I/O’s and extends the signals across other distant data path - ways on the user’s platform. The programmable settings can be applied easily via pins, soft - ware (I2C) or loaded via an external EEPROM. When operating in the EEPROM mode, the configuration information is auto - matically loaded on power up, which eliminates the need for an external microprocessor or software driver. The PI3EQX12908A2 offers fully Linear Transfer function to ful - ly comply with all PCIe 3 Link Training signals. Eye Diagram 8-channel PCI Express Gen 3, 10GbE, SATA3 ReDriver™ with Linear Equalization A product Line of Diodes Incorporated PI3EQX12908A2 Host Channel Loss Pericom ReDriver Device End PointEqualizer, De-emphasis, Swing, and Amplifier Gain Long input trace, cable, or connectors Output trace Input trace Long output trace, cable, or connectors Before Channel Loss Before ReDriver After ReDriver TX TX RX RX
PI3EQX12908A2 www.diodes.com November 2017 Diodes Incorporated PI3EQX12908A2 Document Number DS40411 Rev 1-2 Block Diagram Pin Configuration - Top View (54-TQFN) er Voltage mode output buffer I+ + Buff r Conditional Output Load: 100-Ohm diff. or Hi-Z ut Input Threshold Detection Swing Control Buffer Flat gain control Flat gain control (2-bits) Output Swing control (1-bit) CML Input Buffer VDD Linear AmplifierEqualizer Power ManagementPRSNT# Equalization Control (4-bit) Conditional Input Load: 50-Ohm or 200K-ohm Rx detect I+ I- Repeats for 8 Channel I+O+ I+ O- 19 20 21 22 23 24 25 26 B0RX- B1RX+ B1RX- B2RX+ B3RX+ B3RX- A1RX+ A1RX- A3RX+ A3RX- GND B0TX- B0TX+ B2TX- A0TX+ A0TX- FGB1/AD0 RXDET GND SD_TH0 ENI2C EQB1/AD2 FGA1/SCL FGA0/SDA B0RX+ B2RX- VDD A0RX+ A0RX- VDD A2RX+ A2RX- EQA2 EQA1 EQA0 EQB2 SW0/I2C_RESET# A3TX- A3TX+ A2TX- A2TX+ A1TX- A1TX+ VDD B3TX- 4748 B3TX+ B2TX+ VDD B1TX- 5051525354 FGB0/AD1 PRSNT# VDD ALL_DONE EQB0/AD3 B1TX+
PI3EQX12908A2 www.diodes.com November 2017 Diodes Incorporated PI3EQX12908A2 Document Number DS40411 Rev 1-2 Pin Description (Flow-Thru Pinout) Pin # (54-TQFN) Pin Name Ty pe Description Data Signals A0R X+ A0RX- I I Differential inputs for Channel A0, with internal 50-Ohm pull-up and >200K-Ohm otherwise. A0TX+, A0TX- O O Differential outputs for Channel A0 A1R X+, A1RX- I I Differential inputs for Channel A1, with internal 50-Ohm pull-up and >200K-Ohm otherwise. A1TX+, A1TX- O O Differential outputs for Channel A1 A2RX+, A2RX- I I Differential inputs for Channel A2, with internal 50-Ohm pull-up and >200K-Ohm otherwise. A2TX+, A2TX- O O Differential outputs for Channel A2 A3R X+, A3RX- I I Differential inputs for Channel A3, with internal 50-Ohm pull-up and >200K-Ohm otherwise. A3TX+, A3TX- O O Differential outputs for Channel A3 B0R X+, B0RX- I I Differential inputs for Channel B0, with internal 50-Ohm pullup and >200KOhm otherwise. B0TX+, B0TX- O O Differential outputs for Channel B0 B1R X+, B1RX- I I Differential inputs for Channel B1, with internal 50-Ohm pullup and >200KOhm otherwise. B1TX+, B1TX- O O Differential outputs for Channel B1 B2R X+, B2RX- I I Differential inputs for Channel B2, with internal 50-Ohm pullup and >200KOhm otherwise. B2TX+, B2TX- O O Differential outputs for Channel B2 B3R X+, B3RX- I I Differential inputs for Channel B3, with internal 50-Ohm pullup and >200KOhm otherwise. B3TX+, B3TX- O O Differential outputs for Channel B3
PI3EQX12908A2 www.diodes.com November 2017 Diodes Incorporated PI3EQX12908A2 Document Number DS40411 Rev 1-2 Pin # (54-TQFN) Pin Name Ty pe Description Control Signals
48 ENI2C I
I2C Enable Pin. When tied to Low, each channel is programmed by the external pin voltage (Pin Mode). When tied to High, each channel is programmed by the data stored in the I2C bus (Slave Mode). When FLOAT, data is accesses from external EEPROM (Master Mode). ENI2C has pull-up / pull-down 90k-Ohm resistance (Default = V DD / 2). When ENI2C = 1 (I2C Mode) 50 SCL I/O I2C SCL clock input in I2C Slave Mode (ENI2C = High). This pin becomes clock output when loading from EEPROM in I2C Master Mode (ENI2C = FLOAT). 49 SDA I/O I2C SDA data input/output in I2C Master or Slave Mode. 54, 53, 47, 46 AD[0:3] I I2C programmable address bits in I2C Master or Slave Mode. AD[0:2] have pull- up 90k-Ohm resistance. AD[3] have pull-up / pull-down 90k-Ohm resistance. (Default = V DD/2) 25 I2C_RESET# I Reset Pin for I2C. When Low, the registers are reset to default value. I2C_RESET# has pull-up 90k-Ohm resistance When ENI2C = 0 (Pin mode) 21, 20, 19 EQA[0:2] I These pins set the level of Equalizer in Bank A channels when ENI2C is Low. When ENI2C is High, the I2C registers provide independent control of each channel. See Table 1: Equalizer Settings. EQA[1] has pull-up 90k-Ohm resistance. EQA[0] and EQA[2] have pull-up / pull-down 90k-Ohm resistance (Default = V DD / 2). 46, 47, 23 EQB[0:2] I These pins set the level of Equalizer in Bank B channels when ENI2C is Low. When ENI2C is High, the I2C registers provide independent control of each channel, and the EQB[1:0] pins are converted to I 2C AD[2:3] inputs. See Table 1: Equalizer Settings. EQB[1] has pull-up 90k-Ohm resistance. EQB[0] and EQB[2] have pull-up / pull-down 90k-Ohm resistance (Default = V DD / 2). 49, 50 FGA[0:1] I These pins control the level of Flat Gain in Bank A channels when ENI2C is Low. When ENI2C is High, the I 2C registers provide independent control of each channel, and the FGA[1:0] pins are converted to I2C SCL/SDA. See Table 2: Flat Gain Settings. 53, 54 FGB[0:1] I These pins control the level of Flat Gain in Bank B channels when ENI2C is Low. When ENI2C is High, the I 2C registers provide independent control of each channel, and FGB[1:0] pins are converted to AD[0:1] inputs. See Table 2: Flat Gain Settings. FGB[0] and FGB[1] have pull-up 90k-Ohm resistance.
25 SW0 I This pins sets the Output Voltage Swing level in all channels when ENI
2C is Low. SW0 has pull-up 90k-Ohm resistance.
26 SD_TH0 I
Internal Signal Detect Threshold. This pin should be tied to V DD for normal operation. Refer to Table 4 for more options. SD_TH0 has pull-up 90k-Ohm resistance. In both I2C and Pin modes
22 RXDET I
Receiver Detection Control Pin. When High, receiver detection is enabled to support PCIe Mode. When Low, receiver detection is disabled to support 10GbE and SATA3 Modes and input is 50-Ohm to V DD. RXDET has pull-up 90k-Ohm resistance. Pin Description Cont.
PI3EQX12908A2 www.diodes.com November 2017 Diodes Incorporated PI3EQX12908A2 Document Number DS40411 Rev 1-2 Pin # (54-TQFN) Pin Name Ty pe Description
52 PRSNT# I
Cable Present Detect Input. When High, a cable is not present per PCIe Cabling Specification 1.0, and the device is put in lower power mode. When Low, the device is enabled and in normal operation. PRSNT# has pull-up 90k-Ohm resis - tance. Output 27 ALL_DONE O Valid Register Load Status Output. When LOW, the external EEPROM load has failed. When HIGH, the external EEPROM load is successful. Power Pins 9, 14, 36, 41, 51 V DD PWR 3.3V ± 10% Supply V oltage Center Pad, 24 GND PWR Supply GND Pin Description Cont.
reinitiated when PRSNT# or I2C_RESET# are toggled again. output chatter. When the input voltage is higher than Vth+, the channel is resumed immediately. to 200K and high impedance respectively. Individual channel enabling is done through the I2C register programming. EQA[2:0] and EQB[2:0] are the selection pins for the equalization selection for each of the channels of A and B respectively. Table 1. Equalization Setting
for Flat Gain value for A and B channels. Table 2. Flat Gain Setting SW0 is the selection bit for output swing for A and B channels. Table 3. Output Swing Setting Table 4. Signal Detect Threshold Level Setting via I2C Bus Mode
PI3EQX12908A2 www.diodes.com November 2017 Diodes Incorporated PI3EQX12908A2 Document Number DS40411 Rev 1-2 I2C Programming Address assignment A6 A5 A4 A3 A2 A1 A0 R/W 1 1 1 AD3 AD2 AD1 AD0 1=R, 0=W BYTE 0 Bit Ty pe Power up condition Control affected Comment
7 R A3 Signal Detector Output
1= Activity 0=no activity
6 R A2 Signal Detector Output
5 R A1 Signal Detector Output
4 R A0 Signal Detector Output
3 R B3 Signal Detector Output
2 R B2 Signal Detector Output
1 R B1 Signal Detector Output
0 R B0 Signal Detector Output
Bit Ty pe Power up condition Control affected Comment
7 R A3 RX Detector Output
1 = Far-end 50 -ohm detected 0 = Not detected
6 R A2 RX Detector Output
5 R A1 RX Detector Output
4 R A0 RX Detector Output
3 R B3 RX Detector Output
2 R B2 RX Detector Output
1 R B1 RX Detector Output
0 R B0 RX Detector Output
Bit Ty pe Power up condition Control affected Comment
7 R/W 0 A3 Power down
1 = Power down
6 R/W 0 A2 Power down
5 R/W 0 A1 Power down
4 R/W 0 A0 Power down
3 R/W 0 B3 Power down
2 R/W 0 B2 Power down
1 R/W 0 B1 Power down
0 R/W 0 B0 Power down
PI3EQX12908A2 www.diodes.com November 2017 Diodes Incorporated PI3EQX12908A2 Document Number DS40411 Rev 1-2 BYTE 3 Bit Ty pe Power up condition Control affected Comment
7 R/W 0
6 R/W 0 EQ2
5 R/W 0 EQ1
4 R/W 0 EQ0
3 R/W 0 FG1 Flat Gain
1 R/W 0 Reserved Swing
Bit Ty pe Power up condition Control affected Comment Bit Type Power up condition Control affected Comment I2C Programming Cont.
PI3EQX12908A2 www.diodes.com November 2017 Diodes Incorporated PI3EQX12908A2 Document Number DS40411 Rev 1-2 BYTE 6 Bit Type Power up condition Control affected Comment Bit Type Power up condition Control affected Comment Bit Type Power up condition Control affected Comment I2C Programming Cont.
PI3EQX12908A2 www.diodes.com November 2017 Diodes Incorporated PI3EQX12908A2 Document Number DS40411 Rev 1-2 BYTE 9 Bit Type Power up condition Control affected Comment Bit Type Power up condition Control affected Comment Bit Type Power up condition Control affected Comment
7 R/W 0 A3 Signal Detector
1=Power Down
6 R/W 0 A2 Signal Detector
5 R/W 0 A1 Signal Detector
4 R/W 0 A0 Signal Detector
3 R/W 0 B3 Signal Detector
2 R/W 0 B2 Signal Detector
1 R/W 0 B1 Signal Detector
0 R/W 0 B0 Signal Detector
I2C Programming Cont.
PI3EQX12908A2 www.diodes.com November 2017 Diodes Incorporated PI3EQX12908A2 Document Number DS40411 Rev 1-2 BYTE 12 Bit Type Power up condition Control affected Comment
7 R/W 0 A3 RX Detector
1=Power Down
6 R/W 0 A2 RX Detector
5 R/W 0 A1 RX Detector
4 R/W 0 A0 RX Detector
3 R/W 0 B3 RX Detector
2 R/W 0 B2 RX Detector
1=disable1 R/W 0 B1 RX Detector
0 R/W 0 B0 RX Detector
Bit Type Power up condition Control affected Comment
6 R/W 0
5 R/W 0
4 R/W 0
3 R/W 0
2 R/W 0
1 R/W 0 SD_TH1 Signal Detector
Threshold0 R/W 0 SD_TH0 BYTE 14 to 15 have '0' as Power-up condition I2C Programming Cont.
PI3EQX12908A2 www.diodes.com November 2017 Diodes Incorporated PI3EQX12908A2 Document Number DS40411 Rev 1-2 Reset and I2C Master Timing Diagram SCL/SDA I2C_RESET# Trstpw Master Load Trstd ENI2C HIZ conditionI2C_RESET# Recommended minimum reset pulse width Trstpw= 1μs I2C master cycle start from I2C_RESET# pulse go high, Trstd = 200μs ENI2C = HIZ to I2C_RESET#(high) (min), Ti2cm_rst = 1 uS. I2C Operation The integrated I2C interface operates as a master or slave device depending on the pin ENI2C being HIZ or HIGH respectively. Stan- dard mode (100Kbps) is supported with 7-bit addressing. The data byte format is 8-bit bytes, and supports the format of indexing to be compatible with other bus devices. In the Slave mode (ENI2C = HIGH), the device supports Read/Write. The bytes must be accessed in sequential order from the lowest to the highest byte with the ability to stop after any complete byte has been transferred. Address bits A3 to A0 are programmable to support multiple chips environment. The Data is loaded until a Stop sequence is issued. In the master mode (ENI2C = HIZ), PI3EQX12908A2 supports up to 16 masters connected in daisy chain through connecting I2C_ DONE pin to I2C_RESET# pin of the next part. Master EEPROM data starting address of the device address is indicated in the table below: AD3, AD2,AD1,AD0 EEPROM Data Starting Location 0000 00h 0001 10h 0010 20h 0011 30h 0100 40h 0101 50h 0110 60h 0111 70h 1000 80h 1001 90h
1010 A0h
1011 B0h
1100 C0h
1101 D0h
1110 E0h
1111 F0h
PI3EQX12908A2 www.diodes.com November 2017 Diodes Incorporated PI3EQX12908A2 Document Number DS40411 Rev 1-2 When tying multiple PI3EQX12908A2 devices to the SDA and SCL bus, use the guidelines below to configure the devices. The user also can refer the application notes for detail information.
- Use AD[3:0] address bits so that each device can loaded it's configuration from the EEPROM. Example below is for 4 devices. The first device in the sequence must be address 0x00h; subsequent devices must follow the address order listed below. – U4: AD[3:0] = 0011 = 0x30h
- For I2C Slave Mode operation, use a 2Kohms pull-up resistor on SDA and SCL pins. For I2C Master Mode operation, use a 1Kohm pull-up resistor on SDA and SCL pins.
- Daisy-chain I2C_RESET# and ALL_DONE from one device to the next device in the sequence so that they do not compete for the EEPROM at the same time. 1. Tie ALL_DONE of U1 to I2C_RESET# of U2 2. Tie ALL_DONE of U2 to I2C_RESET# of U3 3. Tie ALL_DONE of U3 to I2C_RESET# of U4 4. Optional: Tie ALL_DONE output of U4 to a LED to show the devices has been loaded successfully Below is an example of a 2 kbits (256 x 8-bit) EEPROM in hex format for 4pcs PI3EQX12908A2 device. Bold fonts in yellow are register setting from Byte0 to Byte15 for each device in each line. Bold fonts in red is the EEPROM data location. :10000000000000FF0000FFFFFFFFFF0000FF620194 :10001000000000FFFF0000FFFFFFFF0000FF620184 :10002000000000FFFFFF0000FFFFFF0000FF620174 :10003000000000FFFFFFFF0000FFFF0000FF620164 :1000400000000000000000000000000000000000B0 :1000500000000000000000000000000000000000A0 :100060000000000000000000000000000000000090 :100070000000000000000000000000000000000080 :100080000000000000000000000000000000000070 :100090000000000000000000000000000000000060 :1000A0000000000000000000000000000000000050 :1000B0000000000000000000000000000000000040 :1000C0000000000000000000000000000000000030 :1000D0000000000000000000000000000000000020 :1000E0000000000000000000000000000000000010 :1000F0000000000000000000000000000000000000 :00000001FF 2k bits (256 x 8-bit) EEPROM Date Example Below is the sample of the I2C master reading waveform based on the setup above.
PI3EQX12908A2 www.diodes.com November 2017 Diodes Incorporated PI3EQX12908A2 Document Number DS40411 Rev 1-2 Transferring Data Every byte put on the SDA line must be 8-bits long. Each byte has to be followed by an acknowledge bit. Data is transferred with the most significant bit (MSB) first (see the I2C Data Transfer diagram). The PI3EQX12908A2 will never hold the clock line SCL LOW to force the master into a wait state. Acknowledge Data transfer with acknowledge is required from the master. When the master releases the SDA line (HIGH) during the acknowledge clock pulse, the PI3EQX12908A2 will pull down the SDA line during the acknowledge clock pulse so that it remains stable LOW during the HIGH period of this clock pulse as indicated in the I2C Data Transfer diagram. The PI3EQX12908A2 will generate an acknowledge after each byte has been received. Data Transfer A data transfer cycle begins with the master issuing a start bit. After recognizing a start bit, the PI3EQX12908A2 will watch the next byte of information for a match with its address setting. When a match is found it will respond with a read or write of data on the fol- lowing clocks. Each byte must be followed by an acknowledge bit, except for the last byte of a read cycle which ends with a stop bit. For a write cycle, the first data byte following the address byte is an index byte that is used by the PI3EQX12908A2. Data is transferred with the most significant bit (MSB) first. SCL Macro A Macro B SCLO (Before arbitration) SCLO (Before arbitration) SCLO (After arbitration) SCLO (After arbitration) After SCL line has become “H”, take the timing until the next state of SCLO = L After SCL line has become “H”, take the timing until the next state of SCLO = L SCL Synchronization When more than one I2C device becomes a master device and drives the SCL line, each device senses the state of SCL line and automati- cally adjust the the drive timing by adjusting the timing to the timing to the slowest one.
PI3EQX12908A2 www.diodes.com November 2017 Diodes Incorporated PI3EQX12908A2 Document Number DS40411 Rev 1-2 1.Readsequencestart R/W ACK ACK ACK NOACK stop DEVSEL DATAOUT DATAOUTN ACK ACK ACK DATAINNDATAIN1 ACKACK R/W start stop 2.Writesequence 3.Combinedsequence INDEXBYTE ACKACK R/W start DATAOUT1 ACKACK R/W start ACK NOACKDATAOUTN stop Notes: 1. only block read and block write from the lowest byte are supported for this application. 2. for some I2C application, an offset address byte will be presented at the second byte in write command, which is called dummy byte here and will be simply ignored in this application for correct interoperation. I C Slave2 DEVSEL INDEX BYTE DEVSEL DEVSEL I C Slave2 I C Slave2 I2C Data Transfer Sequence SDA SCL SDA SCL S START condition P STOP condition I2C START and STOP conditions. I2C Data Transfer Start & Stop Conditions A HIGH to LOW transition on the SDA line while SCL is HIGH indicates a START condition. A LOW to HIGH transition on the SDA line while SCL is HIGH defines a STOP condition, as shown in the figure below. When a STOP condition is detected, index byte value will be reset to 0.
PI3EQX12908A2 www.diodes.com November 2017 Diodes Incorporated PI3EQX12908A2 Document Number DS40411 Rev 1-2 LVCMOS I/O DC Specifications (VDD = 3.3 ± 10%, TA = -40 to 85°C) Symbol Parameter Conditions Min. Ty p. Max. Units VIH DC input logic high VDD/2 + 0.7 VDD + 0.3 V VIL DC input logic low -0.3 VDD/2 - 0.7 V VOH DC output logic high At IOH = -200µA VDD - 0.2 V VOL DC output logic low At IOL = +200µA 0.2 V Vhys Hysteresis of Schmitt trigger input 0.8 V SDA and SCL I/O for I2C-bus (VDD = 3.3 ± 10%, TA = -40 to 85°C) Symbol Parameter Conditions Min. Ty p. Max. Units VIH DC input logic high VDD/2 + 0.7 VDD + 0.3 V VIL DC input logic low -0.3 VDD/2 - 0.7 V VOL DC output logic low IOL = 3mA 0.4 V Vhys Hysteresis of Schmitt trigger input 0.8 V tof Output fall time from V IHmin to VILmax Bus capacity = 10 to 400pF 250 ns fSCLK SCLK clock frequency 100 kHz High Speed I/O AC/DC Specifications (VDD = 3.3 ± 10%, TA = -40 to 85°C) Receiver Input (100Ω differential) Symbol Parameter Conditions Min. Ty p. Max. Units CRX RX AC coupling capacitance 220 nF S11 Input return loss 10MHz to 4GHz dif- ferential 13 dB 1GHz to 4GHz common mode 4 Maximum Ratings (Above which useful life may be impaired. For user guidelines, not tested.) Note: Stresses greater than those listed under MAXIMUM RATINGS may cause permanent damage to the de - vice. This is a stress rating only and functional op - eration of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
PI3EQX12908A2 www.diodes.com November 2017 Diodes Incorporated PI3EQX12908A2 Document Number DS40411 Rev 1-2 Symbol Parameter Conditions Min. Ty p. Max. Units S22 Output return loss 10MHz to 4GHz differ- ential 21 dB 1GHz to 4GHz common mode 4 RIN DC single-ended input impedance 50 Ω DC differential input impedance 100 ROUT DC single-ended output impedance 50 Ω DC differential output impedance 100 ZRX-HIZ DC input CM input impedance during reset or power down 200 kΩ VRX-DIFF-PP Differential Input Peak-to-peak Voltage Operational 1.2 Vppd Input source common-mode noise DC – 200MHz 150 mVppd TTX-IDLE-SET-TO- IDLE Max time to electrical idle after sending an EIOS 4 8 ns TTX-IDLE-TO-DIFF- DATA Max time to valid diff signal after leaving electrical idle 4 8 ns Vth + On threshold of signal detector Signal swing @ 4GHz 130 210 mVppd Vth - Off threshold of signal detector Signal swing @ 100MHz 30 110 mVppd VDD Power supply voltage 3 3.3 3.6 V Pmax Max Supply power PRSNT#=0 1 W Imax Max Supply current 330 mA Pidle Supply power PRSNT#=1 36 mW GP5GHZ Peaking gain (Compensation at 5GHz, rela - tive to 100MHz, 100mVp-p sine wave input) EQ<3:0> = 1111 EQ<3:0> = 1000 EQ<3:0> = 0000 16.1 13.5 8.0 dB Variation around typical -3 +3 GP6GHZ Peaking gain (Compensation at 6GHz, rela - tive to 100MHz, 100mVp-p sine wave input) EQ<3:0> = 1111 EQ<3:0> = 1000 EQ<3:0> = 0000 17.2 14.8 9.0 dB Variation around typical -3 +3 GF Flat gain (100MHz, EQ<3:0> = 1000, SW<1:0> = 01) FG<1:0> = 11 FG<1:0> = 10 FG<1:0> = 01 FG<1:0> = 00 +2.0 -0.5 -2.0 -4.0 dB Variation around typical -3 +3 V1dB_100M -1dB compression point of output swing (at 100MHz) SW0=1 SW0=0 1000 900 mV ppd V1dB_6G -1dB compression point of output swing (at 6GHz) FG= 0dB, EQ = 0000 or 0(h) SW0=1 SW0=0 600 540 mVppd High Speed I/O AC/DC Specifications Cont.
PI3EQX12908A2 www.diodes.com November 2017 Diodes Incorporated PI3EQX12908A2 Document Number DS40411 Rev 1-2 Symbol Parameter Conditions Min. Ty p. Max. Units VCoup Channel isolation 100MHz to 5GHz, Fig- ure 1 (Note 1) 28 dB Vnoise_input Input-referred noise 100MHz to 5GHz, = 0000, Figure 2 0.5 mV RMS 100MHz to 5GHz, = 1010, Figure 2 0.4 V noise_output Output-referred noise (Note 2) 100MHz to 5GHz, = 0000, Figure 2 0.7 mV RMS 100MHz to 5GHz, = 1010, Figure 2 0.8 1.6 Latency tpd Latency From input to output 0.2 ns Jitter Rj Additive Random Jitter at 8Gb/s (worst case) PRBS31@24hrs 36” 5mils FR4 VID = 0.8mVp-p DE = 0dB EQ = 0100 0.0258 UI Note 1: Measured using a vector-network analyzer (VNA) with -15dBm power level applied to the adjacent input. The VNA detects the signal at the output of the victim channel. All other inputs and outputs are terminated with 50Ω. Note 2: Guaranteed by design and characterization. High Speed I/O AC/DC Specifications Cont.
PI3EQX12908A2 www.diodes.com November 2017 Diodes Incorporated PI3EQX12908A2 Document Number DS40411 Rev 1-2 Characteristics of the SDA and SCl bus lines for Standard Mode I2C-bus devices(1) Symbol Parameter Conditions Min. Ty p. Max. Units fSCL SCL clock frequency 100 _ kHz tHD;STA Hold time (repeated) START condition. After this period, the first clock pulse is generated. 4.0 _ mstLOW LOW period of the SCL clock 4.7 _ tHIGH HIGH period of the SCL clock 4.0 _ tSU;STA Set-up time for a repeated START condition 4.7 _ tHD;DAT Data hold time 10 _ ns tSU;DAT Data set-up time 250 _ nstr Rise time of both SDA and SCL signals - 1000 tf Fall time of both SDA and SCL signals 300 tSU;STO Set-up time for STOP condition 4.0 _ ms tBUF Bus free time between a STOP and STOP condition 4.7 _ Cb Capacitive load for each bus line - 400 pF Notes: 1. All values referred to VIH min and VIL max levels
PI3EQX12908A2 www.diodes.com November 2017 Diodes Incorporated PI3EQX12908A2 Document Number DS40411 Rev 1-2 RX1+ RX1- RX2+ RX2- TX1+ TX1- TX2+ TX2- 4-PORT VECTOR NETWORK ANALYZER N52454 PI3EQX12908A2 AGGRESSOR SIGNAL (0dBm) VICTIM INPUT 50Ω 50Ω 50Ω 50Ω VICTIM ONTPUT Channel-Isolation Test Configuration RX_+ RX_- 50Ω 50Ω TX_+ TX_- BALUN PSPL 5315A (200kHz TO 17GHz) POWER METER GIGATRONICS 8652A WITH 80301A HEAD (10MHz to 18GHz) PI3EQX12908A2 Noise Test Configuration AB C FR4 Signal Source SmA Connector SmA Connector ≤30IN In Out D.U.T. AC Test Circuit Referenced in the Electrical Characteristic Table
PI3EQX12908A2 www.diodes.com November 2017 Diodes Incorporated PI3EQX12908A2 Document Number DS40411 Rev 1-2 SDA SCL tf S tHD;STA tLOW tHD;DAT tSU;DAT HIGH tSU;STA tHD;STA Sr tSU;STO P S tf tr tBUF START STOP START I2C Timing VD+ Common Mode Voltage V_D+ - V_D- 0V VCM VDIFF VD- VDIFFp-p VDIFFp-p Definition of Differential Voltage and Differential Voltage Peak-to-Peak
PI3EQX12908A2 www.diodes.com November 2017 Diodes Incorporated PI3EQX12908A2 Document Number DS40411 Rev 1-2 Application Diagrams Applications Information GENERAL RECOMMENDATIONS The PI3EQX12908A2 is a high performance circuit capable of delivering excellent performance. Careful attention must be paid to the details associated with high-speed design as well as providing a clean power supply. Refer to the information below and Revision 4 of the LVDS Owner's Manual for more detailed information on high speed design tips to address signal integrity design issues. PCB LAYOUT CONSIDERATIONS FOR DIFFERENTIAL PAIRS The Differential inputs and LPDS outputs have been optimized to work with interconnects using a controlled differential impedance of 85 - 100Ω. It is preferable to route differential lines exclusively on one layer of the board, particularly for the input traces. The use of vias should be avoided if possible. If vias must be used, they should be used sparingly and must be placed symmetrically for each side of a given differential pair. Whenever differential vias are used the layout must also provide for a low inductance path for the return currents as well. Route the differential signals away from other signals and noise sources on the printed circuit board. POWER SUPPLY BYPASSING Two approaches are recommended to ensure that the PI3EQX12908A2 is provided with an adequate power supply. First, the supply (VDD) and ground (GND) pins should be connected to power planes routed on adjacent layers of theprinted circuit board. The layer thickness of the dielectric should be minimized so that the VDD and GND planes create a low inductance supply with distributed capacitance. Second, careful attention to supply bypassing through the proper use of bypass capacitors is required. A 0.1 μF bypass capacitor should be connected to each VDD pin such that the capacitor is placed as close as possible to the PI3EQX12908A2. Smaller body size capacitors can help facilitate proper component placement. Additionally, capacitor with capacitance in the range of 1 μF to 10 μF should be incorporated in the power supply bypassing design as well. These capacitors can be either tantalum or an ultra-low ESR ceramic. Notes: Hot Plug Detect feature operation is dependent on certain channel conditions, such as length. For hot plug detect, reset will automatically go back to receiver detect (RXDET) cycle. 220nF 220nF 220nF 220nF 0-48in 0-48in PI3EQX12908A2 AXRX+ AXRX- AXTX+ AXTX- 50 ohm50 ohm PRSNT# SDA SCL AGND SDA SCL 3.3V V DD GND VDD
PI3EQX12908A2 www.diodes.com November 2017 Diodes Incorporated PI3EQX12908A2 Document Number DS40411 Rev 1-2 Application Schematics HOST Device o r Connector RX TX RX TX reserve for debug purpose Cn I2C SDA / EEPROMSDA NC I2C SCL / EEPROMSCL Connect to I2C SDA R31=0ohm R32=0ohm SCL/DEMA1/FGA1 SDA/DEMA0/FGA0 R31=NC ENI2C=High (I2C co ntrol) R11=on, R19 =NC SDA/DEMA0/FGA0 NCConnect to EEPROM SCL SCL/DEMA1/FGA1 I2C SCL / EEPROMSCL 0AGF/0AMED/ADSmho0=23R I2C SCL / EEPROMSCLConnect to I2C SCL I2C SDA / EEPROMSDA R32=NC R31=0ohmSCL/DEMA1/FGA1 Connect to EEPROM SDA I2C SDA / EEPROMSDA ENI2C=NC(Master mode) R11=NC, R19 =NC ENI2C=Low (Pin strap c ontrol) R11=NC , R19 =on Cn PI3EQX12908A2 8Gbps 0.1uF 10Gbps Cn IC Part 0.176uF~0.265uF PI3EQX12908A2 Speed Location 10GBASE-KR: 10GBASE-KX4:4.7nF Attention the IC part and differential TX AC coupling capacitor value. ps. PI3EQX8908A/10908A pin 24 is GND(2016Mar22 ) D0RX_N D1RX_P D1RX_N D2RX_P D2RX_N ALL_DONE# EQA2 SD_TH H0RX_N H2RX_P H2RX_N H0RX_P H1RX_P ALL_DONE# AD3/EQB0 H3RX_N H1RX_N H3RX_P D2RX_N D2RX_P D0RX_P RX_DET H2TX_N EQA2 FGB0/AD1 I2C_RST/SW0 EQA1 SD_TH H0TX_N ENI2C H0TX_P SDA/FGA0 ENI2C H1TX_N H3TX_P FGB1/AD0 EQA0 H2TX_P AD3/EQB0 EQB2 EQA0 SCL/FGA1 AD2/EQB1 H3TX_N H1TX_P EQB2 D0TX_P D0TX_N D1TX_P D1TX_N D2TX_P D2TX_N D3TX_P D3TX_N SDA/DEMA0/FGA0 SCL/DEMA1/FGA1 FGB1/AD0FGB0/AD1 0AGF/ADS1AGF/LCS PRSNT# PRSNT# I2C_RST//SW0 I2C SDA / EEPROM SDA I2C SCL / EEPROM SCL VDD_3.3V VDD_3.3V VDD_3.3VVDD_3.3V VDD_3.3VVDD_3.3V VDD_3.3V VDD_3.3V VDD_3.3V VDD_3.3V 0 ohm or NC C6 0.176uF~0.265uF_0402 R140 ohm or NC C5 0.176uF~0.265uF_0402 0 ohm or NC C10 0.176uF~0.265uF_0402 R25 0 ohm or NC R320 ohm or NC R10 2K ohm C15 0.176uF~0.265uF_0402 0 ohm or NC C11 0.176uF~0.265uF_0402 C9 0.176uF~0.265uF_0402 R19 0 ohm or NC R31 0 ohm R18 0 ohm or NC R24 0 ohm or NC C4 0.176uF~0.265uF_0402 C1 0.176uF~0.265uF_0402 LED_R 1 2 C12 0.176uF~0.265uF_0402 R310 ohm or NC 0 ohm or NC 0 ohm or NC 0 ohm or NC C18 0.1u_0402 C16 0.176uF~0.265uF_0402 R120 ohm or NC PI3EQX12908A2ZFE@TQFN54 EQA2 EQA1 B0TX+ B0TX- VDD A0RX+ B1TX+ B1TX- A0RX- A1RX+ B2TX+ B2TX- A1RX- VDD B3TX+ B3TX- A2RX+ A2RX- FGB1/AD0 EQA0 RXDET A3RX- EQB2 GND FGB0/AD1 A1TX- A1TX+ B2RX+ VDD PRSNT# A0TX- A0TX+ B1RX- B1RX+ FGA1/SCL FGA0/SDA VDD B3RX- B0RX- B0RX+ ENI2C B3RX+ B2RX- EQB1/AD2 I2C_Reset#/SW0 SD_TH A3RX+ A3TX- A3TX+ EQB0/AD3 A2TX- A2TX+ ALL_DONE# VDD C13 0.176uF~0.265uF_0402 R10 ohm or NC C3 0.176uF~0.265uF_0402 0 ohm or NC EC1 1.0uF_0805 C14 0.176uF~0.265uF_0402 R20 0 ohm or NC C8 0.176uF~0.265uF_0402 R27 0 ohm or NC R23 0 ohm or NC C2 0.176uF~0.265uF_0402 R130 ohm or NC C7 0.176uF~0.265uF_0402 R11 0 ohm or NC R16 0 ohm or NC R17 0 ohm or NC R40 0 ohm or NC C17 0.1u_0402 R15 0 ohm or NC R28 0 ohm or NC R33 0 ohm or NC 0 ohm or NC R26 0 ohm or NC
PI3EQX12908A2 www.diodes.com November 2017 Diodes Incorporated PI3EQX12908A2 Document Number DS40411 Rev 1-2 Packaging Information 54-TQFN (ZF) 16-0180
Ordering Information
Ordering Number Package Code Package Description PI3EQX12908A2ZFEX ZF 54-Contact, Very Thin Quad Flat No-Lead (TQFN) Thermal Resistance - 54-contact ZF Package/72-contact ZL Package: Notes:
- Thermal characteristics can be found on the company web site at www.diodes.com/design/support/packaging/
- E = Pb-free and Green
- X suffix = Tape/Reel For latest package info. please check: http://www.diodes.com/design/support/packaging/pericom-packaging/packaging-mechanicals-and-thermal-characteristics/
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