Features
Document overview
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Technical content
Features
ÎÎ 5 & 10Gbps serial link with linear equalizer. ÎÎ USB3.1 and USB3.0 Compatible ÎÎ Full Compliancy to USB3.1 Super Speed Standard ÎÎ Single 10Gbps differential signal pairs ÎÎ Pin Adjustable Receiver Equalization ÎÎ Pin Adjustable Flat Gain ÎÎ 100Ω Differential CML I/O’s ÎÎ Automatic Receiver Detect ÎÎ Auto "Slumber" mode for adaptive power management ÎÎ Single Supply Voltage: 3.3V ÎÎ Packaging: Î 18-pin, X2QFN 2x2 mm (XUA18)
Description
The PI3EQX1001 is a low power, high performance 10.0 Gbps 1-Channel USB 3.1 linear ReDriver™ designed specifically for the USB 3.1 protocol. The device provides programmable equalization, and flat gain to optimize performance over a variety of physical mediums by reducing Inter-Symbol Interference. PI3EQX1001 supports one 100Ω Differential CML data I/O’s between the Protocol ASIC to a switch fabric, over cable, or to extend the signals across other distant data pathways on the user’s platform. The integrated equalization circuitry provides flexibility with signal integrity of the signal before the ReDriver. The channels’ input signal level determines whether the output is active. The PI3EQX1001 also includes an automatic receiver detect function. The receiver detection loop will be active again if the corresponding channel’s signal detector is idle for longer than 7.3mS. The channel will then move to Unplug Mode if load not detected, or it will return to Low Power Mode (Slumber Mode) due to inactivity. Block Diagram Figure1 USB 3.0 Cable Smart Phone External Storage Device PC Monitor Tablet PC Pericom USB 3.1ReDriver Notebook Pericom USB 3.1ReDriver PI3EQX1001 1-Channel USB3.1 GEN-2 ReDriver A product Line of Diodes Incorporated
www.diodes.com November 2017 Diodes Incorporated PI3EQX1001 Document Number DS40424 Rev 1-2 Pin Description Pin # Pin Name Ty pe Description 1, 5, 10 VDD Power 3.3V power supply, +/-0.3V 13 FG Input The DC flat gain selection. 4-level input pins. With internal 100KΩ pull-up resistor and 200kΩ pull-down resistor. 14 EQ Input The EQ selection. 4-level input pins. With internal 100KΩ pull-up resistor and 200kΩ pull-down resistor. 16, 17 RXP , RXN Input CML input terminals. With selectable input termination between 50Ω to VDD, 67kΩ to VbiasRx or 67kΩ to GND. 8, 7 TXP, TXN Output CML output terminals. With selectable output termination between 50Ω to VDD, 4K to VDD, 4K to VbiasTx or Hi-Z
11 RXDET_EN Input
Receiver detection Enable pin. With internal 300kΩ pull-up resistor. “High” – Receiver detection is enabled. “Low” – Receiver detection is disabled.
4 EN Input
Channel Enable. With internal 300kΩ pull-up resistor. “High” – Channel is in normal operation. “Low” – Channel is in power down mode. 3, 6, 9, 12, 15, 18, Center Pad GND GND Supply Ground
2 NC NC No Connect
Pin Diagram (18-pin, X2QFN 2x2mm) XUA18 151617 NC GND 987 VDD EN VDD EQ FG RXDET_EN VDD GND TXP GND TXN RXN RXP GND GND GND GND
www.diodes.com November 2017 Diodes Incorporated PI3EQX1001 Document Number DS40424 Rev 1-2 Power Management Notebooks, netbooks, and other power sensitive consumer devices require judicious use of power in order to maximize battery life. In order to minimize the power consumption of our devices, Diodes has added an additional adaptive power management feature. When a signal detector is idle for longer than 1.3ms, the corresponding channel will move to low power mode ONLY. (It means both channels will move to low power mode individually). In the low power mode, the signal detector will still be monitoring the input channel. If a channel is in low power mode and the input signal is detected, the corresponding channel will wake-up immediately. If a channel is in low power mode and the signal detector is idle longer than 6ms, the receiver detection loop will be active again. If load is not detected, then the Channel will move to Device Unplug Mode and monitor the load continuously. If load is detected, it will return to Low Power Mode and receiver detection will be active again per 6ms. Operating Modes Mode RIN ROUT PD 67KΩ to GND HIZ Unplug Mode 67KΩ to VbiasRx 4KΩ to VbiasTx Deep Slumber Mode 50Ω to Vdd 4KΩ to VbiasTx Slumber Mode 50Ω to Vdd 4KΩ to Vdd Active Mode 50Ω to Vdd 50Ω to Vdd
www.diodes.com November 2017 Diodes Incorporated PI3EQX1001 Document Number DS40424 Rev 1-2 Equalization Setting: EQ is the selection pin for the equalization selection Equalizer setting (dB) EQ @2.5GHz @5GHz 0 (Tie 0Ω to GND) 5.1 10.9 R (Tie Rext to Gnd) 1.9 6.7 F (Leave Open) 3.5 8.9 (Default) 1 (Tie 0Ω to VDD) 6.8 13.1 Flat Gain Setting: FG is the selection pin for the DC gain Flat Gain Settings FG dB 0 (Tie 0Ω to GND) -3 R (Tie Rext to Gnd) -1.5 F (Leave Open) 0 (Default) 1 (Tie 0Ω to VDD) +2 Channel Enable Setting: EN is the channel enable pin Channel Enable Setting EN Setting
0 Disabled
1 Enabled (Default)
Receiver Detection Setting: RXDET_EN is the receiver detection pin Receiver Detection Setting RXDET_EN Setting
www.diodes.com November 2017 Diodes Incorporated PI3EQX1001 Document Number DS40424 Rev 1-2 Note: Stresses greater than those listed under MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. Control pin Specifications (VDD = 3.3 ± 0.3V TA = 0 to 70oC) Symbol Parameter Min. Ty p. Max. Units 2-level control pins VIH DC input logic High VDD*0.65 V VIL DC input logic Low VDD*0.35 V IIH Input High current 25 uA IIL Input Low current -25 uA 4-level control pins V IH DC input logic "High" 0.92*VDD VDD V VIF DC input logic "Float" 0.59*VDD 0.67*VDD 0.75*VDD V VIR DC input logic "With Rext to GND" 0.25*VDD 0.33*VDD 0.41*VDD V VIL DC input logic "Low" GND 0.08*VDD V IIH Input High current 50 uA IIL Input Low current -50 uA Rext External resistor connects to GND (±5%) 64.6 68 71.4 kΩ AC/DC Electrical Characteristics (VDD = 3.3 ± 0.3V TA = 0 to 70oC) Power and Latency Symbol Parameter Conditions Min. Ty p. Max. Units Vdd-3.3 Supply voltage 3.0 3.3 3.6 V Iactive Active mode current consumption EN=1 (VDD=3.3V, 10Gbps, compliance test pattern, RXDET_EN=High) 65 88 mA Islumber Slumber mode current consumption EN=1 (VDD=3.3V, no input signal longer than T slumber /RXDET_EN=High) 8 11 mAIDeepSlumber Deep slumber mode current con- sumption EN=1 (VDD=3.3V, no input signal longer than T DeepSlumber/ RXDET_EN=High) 0.4 0.7 Iunplug Unplug mode current consumption EN=1, no output load is detected 0.3 0.5 Ipd Power Down mode current con- sumption EN=0 10 50 µA tpd Latency From input to output 2 ns Maximum Ratings (Above which useful life may be impaired. For user guidelines, not tested.)
www.diodes.com November 2017 Diodes Incorporated PI3EQX1001 Document Number DS40424 Rev 1-2 Symbol Parameter Conditions Min. Ty p. Max. Units CML Receiver Input (100Ω differential) Receiver Electrical Specification Crxparasitic The parasitic capacitor for RX 1.0 pF RRX-DIFF-DC DC Differential Input Impedance 72 120 ΩRRX-SINGLE_ DC DC single ended input impedance DC impedance limits are need to guar - antee RxDet. Measured with respect to GND over a voltage of 500mV max 18 30 ZRX-HIZ-DC- PD DC input CM input impedance for V>0 during reset or power down (Vcm=0 to 500mV) 25 kΩ C ac_coupling AC coupling capacitance 75 265 nF VRX-CM-AC-P Common mode peak voltage AC up to 5GHz 150 mV- peak VRX-CM-DC- Active-Idle- Delta-P Common mode peak voltage |Avguo(|VTX-D+ + VTX-D-|)/2-Avgu1(|VTX-D+ + VTX-D-|)/2| Between U0 and U1. AC up to 5GHz 200 mV- peak Transmitter Electrical Specification VTX-DIFF-PP Ouput differential p-p voltage swing Differential Swing |VTX-D+-VTX-D-| 1.2 Vppd RTX-DIFF-DC DC Differential TX Impedance 72 120 Ω VTX-RCV-DET The amount of voltage change al- lowed during RxDet 600 mV Cac_coupling AC coupling capacitance 75 265 nF TTX- EYE(10Gbps) Transmitter eye, Include all jittter At the silicon pad. 10Gbps 0.646 UI TTX- EYE(5Gbps) Transmitter eye, Include all jittter At the silicon pad. 5Gbps 0.625 UI TTX-DJ- DD(10Gbps) Transmitter deterministic jittter At the silicon pad. 10Gbps 0.17 UI TTX-DJ- DD(5Gbps) Transmitter deterministic jittter At the silicon pad. 5Gbps 0.205 UI Ctxparasitic The parasitic capacitor for TX 1.1 pF RTX-DC-CM Common mode DC output Imped- ance 18 30 Ω VTX-DC-CM The instantaneous allowed DC com - mon mode voltage at the connector side of the AC coupling capacitors |VTX-D++VTX-D-|/2 0 2.2 V VTX-C Common-Mode Voltage |VTX-D++VTX-D-|/2 VDD- 1.5V VDD V VTX-CM-AC- PP-Active Active mode TX AC common mode voltage VTX-D++VTX-D- for both time and amplitude 100 mVpp AC/DC Electrical Characteristics Cont.
www.diodes.com November 2017 Diodes Incorporated PI3EQX1001 Document Number DS40424 Rev 1-2 Symbol Parameter Conditions Min. Ty p. Max. Units VTX-CM-DC- Active_Idle- Delta Common mode delta voltage |Avguo(|VTEX-D+ + VTX-D-|)/2-Avgu1(|VTX- D+ + VTX-D-|)/2| Between U0 to U1 200 mV- peak VTX-Idle-Diff- AC-pp Idle mode AC common mode delta voltage|VTX-D+-VTX-D-| Between Tx+ and Tx- in idle mode. Use the HPF to remove DC components. =1/ LPF. No AC and DC signals are applied to Rx terminals . 10 mVppd V TX-Idle-Diff- DC Idle mode DC common mode delta voltage |VTX-D+-VTX-D-| Between Tx+ and Tx- in idle mode. Use the LPF to remove DC components. =1/ HPF. No AC and DC signals are applied to Rx terminals. 10 mV Channel Performance G p Peaking gain (Compensation at 5GHz, relative to 100MHz, 100mVp- p sine wave input, FG=F) EQ=0 EQ=R EQ=F EQ=1 10.9 6.7 8.9 13.1 dB Variation around typical -3 +3 dB G F Flat gain (100MHz, EQ=F) FG=0 FG=R FG=F FG=1 -1.5 dB Variation around typical -3 +3 dB V SW_100M -1dB compression point output swing (at 100MHz) 1000 mVppd VSW_5G -1dB compression point output swing (at 5GHz) 750 mVppd V noise-input Input-referred noise 100MHz to 5GHz, FG=1, EQ=R, Figure 2 0.6 mVRMS 100MHz to 5GHz, FG=1, EQ=1, Figure 2 0.5 Vnoise-output Output-referred noise1 100MHz to 5GHz, FG=1, EQ=R, Figure 2 0.8 mVRMS 100MHz to 5GHz, FG=1, EQ=1, Figure 2 1 Signal and Frequency Detectors Vth_upm Unplug mode detector threshold Threshold of LFPS when the input imped- ance of the redriver is 67kohm to Vbi- asRx only. Used in the unplug mode. 200 800 mVppd Vth_dsm Deep slumber mode detector thresh - old LFPS signal threshold in Deep slumber mode 100 600 mVppd Vth_am Active mode detector threshold Signal threshold in Active and slumber mode 45 175 mVppd F th LFPS frequency detector Detect the frequency of the input CLK pattern 100 400 MHz Note: 1. Guaranteed by design and characterization. AC/DC Electrical Characteristics Cont.
www.diodes.com November 2017 Diodes Incorporated PI3EQX1001 Document Number DS40424 Rev 1-2 Figure3. Test Condition Referenced in the Electrical Characteristic Table D.U.T. Signal Source SmA Connector In Out A SmA Connector B C FR4 24IN Figure2. Noise test configuration
www.diodes.com November 2017 Diodes Incorporated PI3EQX1001 Document Number DS40424 Rev 1-2
Ordering Information
Ordering Number Package Code Package Description PI3EQX1001XUAEX XUA 18-Pin, 2X2mm (X2QFN) Packaging Mechanical: 18-pin X2QFN 14-0039 Notes:
- Thermal characteristics can be found on the company web site at www.diodes.com/design/support/packaging/
- E = Pb-free and Green
- X suffix = Tape/Reel For latest package info. please check: http://www.diodes.com/design/support/packaging/pericom-packaging/packaging-mechanicals-and-thermal-characteristics/
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