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Document overview
- Manufacturer or author: Provided By ALLDATASHEET.COM(FREE DATASHEET DOWNLOAD SITE)
- PDF pages: 19
Technical content
Features
- Integrated High Performance 12A, 8.5m Ω MOSFET
- Very small, high density fully-optimized solution with simple PCB layout
- Fast dynamic response to power source failures, with 80ns reverse current turn-off delay time
- Accurate sensing capability to indicate system fault conditions (-6mV reverse threshold)
- Internal charge pump
- Active low fault flag output
Applications
- N+1 Redundant Power Systems
- Servers & High End Computing
- Telecom Systems
- High-side Active ORing
Package Information
The PI2127 is offered in the following package:
- 17-pin 7mm x 8mm thermally enhanced LGA package, achieving <10°C/W RθJ-PCB Typical Application: Figure 1: PI2127 High Side Active ORing Figure 2: PI2127 response time to an input short fault condition
Picor Corporation • picorpower.com PI2127 Rev 1.3 Page 2 of 19 Pin Description Pin Name Pin Number Description NC 1, 3, 5, 7 Not Connected: Leave pins floating. PG 2 Control Circuitry Return: This pin is the floating return path for the controller circuitry. Connect this pin via a resistor to the low side return (ground). FT 4 Fault Status Output: This open collector pin pulls low to indicate one of the several potential fault conditions may exist. The Fault pin will pull low after a reverse or forward fault has been detected with a defined delay time (8μs). In addition, the FT pin will pull low when the controller input voltage is below the VC under-voltage threshold VS-PG < 7V (VSUVF). When VS-PG > 7.15V (VSUVR) and 6mV < VSP-SN < 275mV this pin clears (High). Leave this pin open if unused. GND 6 FT Return: This pin is the return (ground) for the open collector fault circuitry. Connect this pin to logic ground. SN 8 Negative Sense Input: Connect SN pin to the trace between D pin (outside of the PI2127 foot print) and the output load. The polarity of the voltage difference between SP and SN provides an indication of current flow direction through the MOSFET. D 9, 10, 11, Drain: The Drain of the internal N-channel MOSFET and fault level shift circuit. Connect this pin to the output load. S 12, 13, 14 Source-The source of the internal N-channel MOSFET and bias for the control circuitry. Connect this pin to the input power source bus voltage. SP 15 Positive Sense Input: Connect SP pin to the trace between S pin (outside of the PI2127 foot print) and the input source. The polarity of the voltage difference between SP and SN provides an indication of current flow direction through the MOSFET. Package Pin-Out 17-pin LGA (7mm x 8mm) Top view
Picor Corporation • picorpower.com PI2127 Rev 1.3 Page 3 of 19 Absolute Maximum Ratings Note: Unless otherwise specified, all voltage nodes are referenced to “PG” Drain-to-Source Voltage (VDS) 60V @ 25°C Source Current (Is) Continuous 12A Source Current (Is) Pulsed (10μs) (1) 100A Source Current (Is) Pulsed (300ns) (1) 150A Single Pulse Avalanche Current (TAV<11μs) (1) 33A Junction-to-Ambient Thermal Resistance (RθJ-A) 45°C/W (0LFM) Junction-to-PCB Thermal Resistance (RθJ-PCB) 10°C/W S (Source), -0.3V to 13V / 10mA SP -0.3V to 17.3V / 10mA SN, D (Drain) -0.3V to 60V / 10mA GND -50V to +0.3V / 10mA FT to GND -0.3V to 20V / 10mA D (Drain) to GND -0.3V to 60V / 10mA Storage Temperature -65oC to 150oC Operating Junction Temperature -40°C to 140°C Internal MOSFET Operating Junction Temperature -40°C to 150°C Soldering Temperature for 20 seconds 260oC ESD Rating CDM Class IV Electrical Specifications Unless otherwise specified: -40°C < TJ < 125°C, VS-PG =10.5V, VPG=VGND=0V, VD=VS Parameter Symbol Min Typ Max Units Conditions Control Circuit Supply (S to PG) Operating Supply Range VS-PG 8.5 10.5 V No VC limiting Resistor Quiescent Current IVC 1.5 2.0 mA Normal operation, no fault Clamp Voltage VS-CLM 11 11.7 12.5 V I S=3mA Clamp Resistance RS 10 Ω Delta IS=10mA Under-Voltage Rising Threshold V SUVR 6.1 7.15 8.5 V Under-Voltage Falling Threshold V SUVF 6 7.00 7.9 V Under-Voltage Hysteresis VSUV-HS 100 150 200 mV
Picor Corporation • picorpower.com PI2127 Rev 1.3 Page 4 of 19 Electrical Specifications Unless otherwise specified: -40°C < TJ < 125°C, VS-PG =10.5V, VPG=VGND=0V, VD=VS Parameter Symbol Min Typ Max Units Conditions DIFFERENTIAL AMPLIFIER AND COMPARATORS (Continued) Common Mode Input Voltage VCM -3 3 V SP to S and SN to S Differential Operating Input Voltage(1) V SP-SN -80 400 mV SP-SN SP Input Bias Current ISP 35 55 75 μA V SP = VSN = VS SN Input Bias Current ISN 35 55 75 μA V SP = VSN = VS SN Current During Fault Condition(3) I SN-FLT 5 7.5 mA VSN = 60V, VSP = VS =VD=0V MOSFET Turn On Threshold V FET-ON +1 +6 +11 mV V SP-PG = 10.5V, @ 25°C Reverse Comparator Threshold V RVS-TH -11 -6 -2 mV V SP-PG = 10.5V, @ 25°C Reverse to On Hysteresis VRVS-HY 10 12 14 mV V SP-PG = 10.5V, @ 25°C Reverse Fault to MOSFET Turn-off Time tRVS 80 150 ns V SP-SN = ± 50mV step Forward Comparator Threshold V FWD-TH 250 275 300 mV Forward Comparator Hysteresis V FWD-HY 15 25 35 mV Internal N-Channel MOSFET Drain-to-Source Breakdown Voltage BV DSS 60 V VS=VGND=VFT=VSP=0V ID=2mA , Tj=25°C; VSN=10.5V Source Current Continuous IS 12 A In ON state, Tj=25°C D Pin Current During Fault (3) (including level-shift circuitry) ID-FLT 4 mA VD=60V; VGND=VFT=VS=VSP=0V, Tj=25°C, VSN=10.5V Drain-to-Source On Resistance R DSon 8.5 11 mΩ In ON state, IS=10A, Tj=25°C Body Diode Forward Voltage VF-BD 0.75 1.0 V In OFF state, IS=4A, Tj=25°C Fault Fault Output Low Voltage FTV 0.2 0.5 V I FT=2mA, VS-PG ≥ 4.5V Fault Output High, Leakage Current I FT 10 μA V FT=14V Fault Delay time TFT-DLY 4 8 16 μs V SP-SN = ± 50mV step Note 1: These parameters are not production tested but are guaranteed by design, characterization, and correlation with statistical process control. Note 2: Current sourced by a pin is reported with a negative sign. Note 3: Current flow during input short fault condition. See the Fault Circuit description in the Application Information section for more detail
Picor Corporation • picorpower.com PI2127 Rev 1.3 Page 5 of 19 Functional Description: The PI2127 integrated Cool-ORing product takes advantage of two different technologies combining an 8.5m Ω on-state resistance (R DS(on)) N-channel MOSFET with high density control circuitry. This combination provides superior density, minimizing PCB space to achieve an ideal ORing diode function, significantly reducing power dissipation and eliminating the need for heat sinking, while minimizing design complexity. The PI2127’s 8.5mΩ on-state resistance MOSFET used in the conduction path enables a dramatic reduction in power dissipation versus the performance of a diode used in conventional ORing applications due to its high forward voltage drop. Due to the inherent characteristics of the MOSFET, current will flow in the forward and reverse directions while the gate remains a bove the gate threshold voltage. Ideal ORing applications should not allow reverse current flow, so the controller has to be capable of very fast and accurate detection of reverse current caused by input power source failures, and very fast turn off of the gate of the MOSFET. Once the gate voltage falls below the gate threshold, the MOSFET is off and the body diode will be reverse biased preventing reverse current flow and subsequent excessive voltage droop on the redundant bus. Differential Amplifier: The PI2127 integrates a high-speed low offset voltage differential amplifier to sense the difference between the Sense Positive (SP) pin voltage and Sense Negative (SN) pin voltage with high sensitivity to fault current. The amplifier output is connected to the Reverse and Forward comparators. Reverse Current Comparator: RVS The reverse current comparator provides the critical function in the controller, detecting negative voltage caused by reverse current. Gate drive is enabled when SP is 6mV higher than SN. When the SN pin is 6mV higher than the SP pin, the reverse comparator will force the gate discharge circuit to turn off the MOSFET in typically 80ns and assert the Fault ( FT ) low to report a fault condition. The reverse comparator will hold the gate low until the SP pin is 6mV higher than the SN pin. The reverse comparator hysteresis is shown in Figure 3. Figure 3: Reverse comparator hysteresis: VSP - VSN Forward Voltage Comparator: FWD The FWD comparator detects when a forward voltage condition exists and SP is above 275mV (typical) positive with respect to SN. When SP-SN is more than 275mV, the FWD comparator will assert the Fault ( FT ) low to report a fault condition. Internal Voltage Regulator: The PI2127 control circuitry and the gate driver are biased through the S pin. An internal regulator clamps the S voltage (V S-PG ) to 11.7V. The internal regulator circuit has a comparator to monitor S input with respect to the PG pin and pulls the MOSFET GATE low when V S-PG is lower than the Under- Voltage Threshold. Fault Indication: FT The FT pin is an open collector NPN that will be pulled low during following fault conditions. Typical Condition Indication of possible faults
1 Reverse: V SP-VSN ≤ -6mV Input supply shorted
(MOSFET turned OFF)
2 Forward: V SP-VSN ≥ +275mV
Open FET, Gate short, Gate open, or High current (MOSFET turned ON)
3 Forward V SP-VSN ≤ +6mV Shorted FET on power-up
(MOSFET turned OFF) 4 UVLO 4.5V < V S-PG<7.15V Controller not ready (MOSFET turned OFF)
Picor Corporation • picorpower.com PI2127 Rev 1.3 Page 7 of 19 Figure 6: PI2127 Timing Diagram.
Picor Corporation • picorpower.com PI2127 Rev 1.3 Page 10 of 19 Figure 19: Plot of PI2127 response time to reverse current detection
Application Information
The PI2127 is designed to replace high side ORing diodes in high current, medium voltage redundant power architectures. Replacing a traditional diode with a PI2127 will result in significant power dissipation reduction as well as board space reduction, efficiency improvement and additional protection features. This section describes in detail the procedure to follow when designing with the PI2127 Active ORing solution. Control Circuitry Bias: The PI2127 control circuitry and the gate driver for the internal MOSFET are biased through the S pin. An internal regulator clamps the S pin voltage (V S-PG) to 11.7V typically. A bias resistor (R PG) is required if the voltage at the S pin is higher than the minimum Voltage Clamp (V S- CLM). R PG should be connected between PG pin and ground (VS return). Minimize the resistor value for low S voltage levels to avoid a voltage drop that may reduce V S-PG lower than required. Select the value of R PG using the following equations: mAI V VR VC PGMax SS PG 1 . 0max min −= −− RPG maximum power dissipation: PG PGMin SS RPG R V VPd max )( −− −= Where: min−SV : S pin minimum applied voltage max−SV : S pin maximum applied voltage PGMax SV − : Controller maximum clamp voltage, 12.5V
Picor Corporation • picorpower.com PI2127 Rev 1.3 Page 11 of 19 PGMin SV − : Controller minimum clamp voltage, 11V maxVCI : Controller maximum bias current, use 2.0mA mA1 . 0: 0.1mA is added for margin Example: 40V <VS-PG <50V Ω =−=+ −= − kmA V V mAIC V VR PGMax SS PG 1 . 131 . 2 5 . 12 40 1 . 0max min () mWk V V R V VPdR PG PGMin SS PG 1161 . 13 11 50)( max =Ω −=−= −− Alternative Bias Circuit with Device Enable: Constant current circuit In a wide operating input voltage range the size of RPG may be become large to support power dissipation. A simple constant current circuit can be used instead of RPG to reduce power dissipation and can be used as a device enable. As shown in Figure 20, the constant current circuit consists of an NPN transistor (Q1), Zener diode D current limit resistor (R LIMIT) and Zener bias resistor (RZ). R LIMIT and R Z can be very low power resistors and Q1 is a signal transistor where its Collector- Emitter Voltage (V CEO) is equal or greater than the input operating voltage and supports 2.5mA at the operating input voltage. Figure 20: Constant current bias circuit Pulling the Q1 base (EN) to the system return (RTN) will turn off the transistor and the controller return (PG pin) will float and eventually the MOSFET will be turned off. An open collector device can be used to enable and disable the PI2127. The constant current circuit should guarantee current greater than the PI2127 maximum Quiescent current VC), 2.0mA. RLIMIT can be calculated from the following equation: MAX VC BEMIN Z LIMIT I on V V R _ ) (− Where: MIN ZV _ : Minimum Zener diode voltage ) (on VBE : Q1 Base-Emitter On maximum voltage, for default use ) (on VBE =0.7V Zener Diode Selection: Select a Zener diode with a low reverse current requirement to minimize RZ. Zener diodes with higher break down voltage will have lower reverse current and reduce Q1 collector current variation. Zener diodes with a breakdown voltage of 6V and higher will require low bias current for accurate voltage breakdown. R Z maximum value can be calculated with the following equation: Note that the surface mount resistors have limited operating voltage capability. Be sure to pick a resistor package that can meet the maximum operating voltage (Vin). MAX B Z MAX ZMIN in Z I I V V R Where: MIN inV _ : Min input voltage MAX ZV _ : Zener diode maximum breakdown voltage ZI : Zener diode required reverse current MAX BI _ : Q1 required maximum base current which calculated from the following equation: MIN FE MAX C MAX B h II _ = MAX CI _ : Q1 maximum expected collector current. MIN FEh _ : Q1 minimum gain. Internal N-Channel MOSFET BVDSS: The PI2127’s internal N-Channel MOSFET breakdown voltage (BV DSS) is rated for 60V at 25°C and will degrade to 55.5V at -40°C, refer to Figure 10. Drain to source voltage should not exceed BV DSS in nominal operation. During a fast switching transient the MOSFET can tolerate voltages higher than its BV DSS rating under avalanche conditions, refer to the Absolute Maximum Ratings table. In Active ORing applications when one of the input power sources is shorted, a large reverse current is
Picor Corporation • picorpower.com PI2127 Rev 1.3 Page 12 of 19 sourced from the load through the MOSFET. Depending on the output impedance of the system and the parasitic inductance, the reverse current in the MOSFET may exceed the source pulsed current rating (150A) just before the PI2127 MOSFET is turned off. The peak current during an input short condition is calculated as follows, assuming that the output has very low impedance and it is not a limiting factor: PARASITIC RVS S PEAK L t VI *= Where: PEAKI : Peak current in PI2127 MOSFET before it is turned off. SV : Input voltage or load voltage at S pin before input short condition did occur. RVSt : Reverse fault to MOSFET turn-off time. PARASITICL :Circuit parasitic inductance The high peak current during an input short and before the MOSFET turns off, stores energy in the circuit parasitic inductance, and as soon as the MOSFET turns off, the stored energy will be released and this will produce a high negative voltage and ringing at the MOSFET source. At the same time the energy stored at the drai n side of the internal MOSFET will be released and produce a voltage higher than the load voltage. This event will create a high voltage difference between the drain and source of the MOSFET. The MOSFET will avalanche, but this avalanche will not affect the MOSFET performance because the PI2127 has a fast response time to the input fault condition and the stored energy will be well below the MOSFET avalanche capability. MOSFET avalanche during input short is calculated as follows: * ** 3 . 1 * 3 . 1*2 PEAKPARASITIC SDSS DSS AS I LV BV BVE −= Where: ASE : Avalanche energy DSSBV : MOSFET breakdown voltage (60V) Power dissipation: In Active ORing circuits the MOSFET is always on in steady state operation and the power dissipation is derived from the total source current and the on-state resistance of the MOSFET. The PI2127 internal MOSFET power dissipation can be calculated with the following equation: ) ( on DSMOSFET R IsPd ∗ = Where: Is: Source Current MOSFETPd : MOSFET power dissipation RDS(on): MOSFET on-state resistance Note: For the worst case condition, calculate with maximum rated R DS(on) at the MOSFET maximum operating junction temperature because R DS(on) is temperature dependent. Refer to Figure 11 for normalized R DS(on) values over temperature. The PI2127 maximum R DS(on) at 25°C is 11m Ω and will increase by 43% at 125°C junction temperature. The Junction Temperature rise is a function of power dissipation and thermal resistance. ) ( on DSJAMOSFETJA R Is R Pd R Trise∗ ∗ = ∗ =θθ Where: JARθ : Junction-to-Ambient thermal resistance (45°C/Watt) This may require iteration to get to the final junction temperature. Figure 13 and Figure 16 show the PI2127 internal MOSFET final junction temperature curves versus conducted current at maximum R DS(on), given ambient temperatures and air flow. Fault Circuit: FT is an open collector pin and should be pulled up to the logic voltage via a resistor (10KΩ). An internal level shift circuit is implemented to change the PI2127 controller fault out put reference from the PG pin voltage level to the GND pin voltage level. The level shift circuit is biased from the D pin to stay active when the bias voltage at S pin is not available. In the event of an input short fault condition, the S pin will be pulled low (ground) and the PI2127 control circuit will lose its bias voltage. If the output voltage is supplied from a redundant source, then the level shifter stays biased and the FT pin will be pulled low to indicate that the MOSFET is in the OFF condition. During start-up and before the output voltage is established, the FT pin will be floating until the approximately 4.5V is present at the S pin or at D pin. Thereafter the FT pin is pulled low and stays low until the PI2127 controller bias voltage V S-PG increases above the controller Under-Voltage Threshold (V SUVR) and no fault conditions are present. Once this
Picor Corporation • picorpower.com PI2127 Rev 1.3 Page 13 of 19 happens, the MOSFET is turned on and the FT pin will be high resistance to indicate that the MOSFET is in RDS(on) with no fault conditions existing. Note that in case of an input fault condition, where the S pin is at ground and the output (D pin and SN pin) are at a high voltage there will be two current paths, one path from D pin to GND and the other path from SN pin to SP. The current path from D pin to GND and S pins is due to the level shift circuit and will draw current from the output as a function of the voltage between D pin and GND (V D-GND) based on the following equation: Ω −= − k VVI GND D FLT D 5 . 0 Where: FLT DI − : Maximum D pin current during input short fault condition GND DV − : Voltage difference between the D pin and ground. The current path from SN pin to S pin is a function of the SN voltage based on the following equation: PAR GND SN FLT SN R VVI 12 −= − Where: FLT SNI _ : SN current during input short fault condition GND SNV − : Voltage difference between SN pin (or load voltage) and ground. PARR : Resistance of the internal path, 10K Ω typical and 8kΩ minimum The level shift circuit worst case power dissipation during input short is: Ω −= − k VVPd GND D ) 5 . 0 (2 The thermal resistance and power dissipation of the level shift circuit will limit the voltage applied at the D pin during a shorted input condition. When the PCB temperature exceeds 110°C, the applied voltage must be derated according to Figure 21. The plot in Figure 21 is calculated using the worst case power dissipation during an input short with R θJ-PCB= 100°C/W. Figure 21: Level shift circuit applied voltage de-rating (valid during an input short fault condition as a function of PCB Temperature)
Picor Corporation • picorpower.com PI2127 Rev 1.3 Page 14 of 19 Typical Application Example: Requirement: Redundant Bus Voltage = 40V ±5V Maximum Load Current = 9A (assume through each redundant path) Maximum Ambient Temperature = 60°C, no air flow (0LFM) The current flow parasitic inductance for each ORing device is 60nH. Solution: A single PI2127 for each redundant 40V power source should be used, configured as shown in the circuit schematic in Figure 23. R PG selection: 35V <VS-PG <45V Ω =−=+ −= − kmA V V mAIC V VR PGMax SS PG 71 . 101 . 2 5 . 12 35 1 . 0max min The closest 1% resistor available is 10.5kΩ () mWk V V R V VPdR PG PGMin SS PG 1105 . 10 11 45)( max =Ω −=−= −− The selected resistor should be capable of supporting the total power at maximum operating temperature, 60°C. An 0805 (2012) will support the power requirement. FT pin: Connect FT pin to the logic input and to the logic power supply via a resistor, as required for the proper input level of the supervisor functions. Power Dissipation and Junction Temperature: First use Figure 13 (Junction Temperature vs. Input Current) to find the final junction temperature for 9A load current at 60°C ambient temperature. In Figure 13 (illustrated in Figure 22) draw a vertical line from 9A to intersect the 60°C ambient temperature line. At the intersection draw a horizontal line towards the Y- axis (Junction Temperature). The Junction Temperature at maximum load current (9A) and 60°C ambient is 115°C. R DS(on) is 11mΩ maximum at 25°C and will increase as the Junction temperature increases. From Figure 11, at 115°C RDS(on) will increase by 38%, then Ω = ∗ Ω =mm Ron DS 18 . 15 38 . 1 11) ( maximum at 115°C Maximum power dissipation is: W m A R Iin Pdon DS 23 . 1 18 . 15 ) 9 (2 ) ( max = Ω ∗ = ∗ = Recalculate TJ: Cm AW CC TJ ° =⎟ max Figure 22: Example 1 final MOSFET junction temperature at 9A/60°C TA Reverse Current Threshold: The following procedure demonstrates how to calculate the minimum required reverse current in the internal MOSFET to generate a reverse fault condition and turn off the internal MOSFET. At maximum junction temperature (115°C) and maximum R DS(on): mAm mV R Vreverse Is on DS TH RVS 39518 . 15 ) ( − =Ω −= =− Peak current under input short is: At typical response time: AnH ns V L t VI PARASITIC RVS S PEAK 6060 80 * 45* ===
Picor Corporation • picorpower.com PI2127 Rev 1.3 Page 15 of 19 At maximum response time: AnH ns V L t VI PARASITIC RVS S PEAK 5 . 11260 150 * 45* === Avalanche Energy: * ** 3 . 1 * 3 . 1*2 PEAKPARASITIC SDSS DSS AS I LV BV BVE −= J A nHV VEAS μ897 5 . 112 * 60 *45 60 * 3 . 1 60 * 3 . 1*2 1 2 =−= The avalanche energy is well below the total MOSFET specified peak current of 150A for 300ns and below the rated avalanche energy. The specified energy can be calculated from Single Pulse Avalanche Current as specified in the Absolute Maximum Ratings table: mJ s A Vt I BVAV AS DSS 14 11 33 60 3 . 12 1* 3 . 12 Figure 23 : Two PI2127 in High Side ORing configuration VC bias through Constant current circuit Select an NPN transistor with V CEO equal or higher than the input voltage (V in) plus any expected transient voltage and capable of handling the expected maximum power dissipation. Any NPN transistor with V CEO ≥ 60V in a small footprint is suitable. An exemplary NPN is the BC846 from NXP Semiconductors: From the BC846 datasheet: NPN general-purpose transistor V CEO = 65V Collector-Emitter maximum voltage IC = 100mA maximum collector current hFE = 110 minimum at I C=2mA VBE = 0.580V to 0.70V Base-Emitter voltage at IC = 2mA and 25°C RθJ-A = 500°C/W Junction to ambient thermal resistance. Select Zener Diode: A Zener diode with low bias current and V Z=10 in small foot print is suitable for this application. An exemplary Zener diode is the MM3Z10VST1 the from ON Semiconductor From the MM3Z10VST1 datasheet: 10V, 200mW Zener Diode V Z = 9.80V to 10.2V Zener voltage range IR = 10 μA will hold the Zener breakdown voltage at 9.8V Ω =−= = kmA V V I on V V R MAX VC BEMIN Z LIMIT 33 . 41 . 2 7 . 0 8 . 9) ( Or 4.32kΩ 1% AmA h II MIN FE MAX C MAX B μ27 . 27110 _ = = = R Z Calculation: Use 120μA as minimum for the Zener diode reverse leakage current and Q2 base current combined. Ω =−=+ = kA V V I I V V R MAX B Z MAX ZMIN in Z 248120 2 . 10 40 μ Select RZ= 249kΩ 1% Maximum Q1 collector current: mAk V V R V VI MINLIMIT MIN BEMAX Z MAX C 29 . 298 . 0 * 32 . 4 50 . 0 2 . 10 _ =Ω −=−= Maximum Q2 power dissipation )]([ * ___ 1 MAX EBMIN ZCLM VCMAXMAX C Q V VV VinI Pd − − −= − mW V V V V mAPdQ 57 )] 7 . 0 8 . 9 ( 11 45 [ * 29 . 21 = − − −= Transistor temperature rise CW CmWR Pd TA J QRISEQ ° =°== − 50 . 28 500 * 57 *11 θ
Picor Corporation • picorpower.com PI2127 Rev 1.3 Page 17 of 19 Package Drawing:
Ordering Information
Part Number Package Transport Media PI2127-01-LGIZ 7mm x 8mm 17-pin LGA T&R
Picor Corporation • picorpower.com PI2127 Rev 1.3 Page 18 of 19 Footprint Recommendation:
Picor Corporation • picorpower.com PI2127 Rev 1.3 Page 19 of 19 Warranty Vicor products are guaranteed for two years from date of shipment against defects in material or workmanship when in normal use and service. This warranty does not extend to products subjected to misuse, accident, or improper application or maintenance. Vicor shall not be liable for collateral or consequential damage. This warranty is extended to the original purchaser only. EXCEPT FOR THE FOREGOING EXPRESS WARRANTY, VICOR MAKES NO WARRANTY, EXPRESS OR LIMITED, INCLUDING, BUT NOT LIMITED TO, THE WARRANTY OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE. Vicor will repair or replace defective products in accordance with its own best judgment. For service under this warranty, the buyer must contact Vicor to obtain a Return Material Authorization (RMA) number and shipping instructions. Products returned without prior authorization will be returned to the buyer. The buyer will pay all charges incurred in returning the product to the factory. Vicor will pay all reshipment charges if the product was defective within the terms of this warranty. Information published by Vicor has been carefully checked and is believed to be accurate; however, no responsibility is assumed for inaccuracies. Vicor reserves the right to make changes to any products without further notice to improve reliability, function, or design. Vicor does not assume any liability arising out of the application or use of any product or circuit; neither does it convey any license under its patent rights nor the rights of others. Vicor general policy does not recommend the use of its components in life support applications wherein a failure or malfunction may directly threaten life or injury. Per Vicor Terms and Conditions of Sale, the user of Vicor components in life support applications assumes all risks of such use and indemnifies Vicor against all damages. Vicor’s comprehensive line of power solutions includes high density AC-DC and DC-DC modules and accessory components, fully configurable AC-DC and DC-DC power supplies, and complete custom power systems. Information furnished by Vicor is believed to be accurate and reliable. However, no responsibility is assumed by Vicor for its use. Vicor components are not designed to be used in applications, such as life support systems, wherein a failure or malfunction could result in injury or death. All sales are subject to Vicor’s Terms and Conditions of Sale, which are available upon request. Specifications are subject to change without notice. Vicor Corporation Picor Corporation
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