PI1004-1

PI1004-1 VICOR | Alldatasheet

Document overview

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Technical content

Features

• 0.5% Typical initial output voltage accuracy
• Remote differential output voltage sense
• 6 Bit DAC, with 12.5 mV resolution
• 5 V to 12 V Operation
• Power good output with blanking
• Programmable adaptive voltage positioning (AVP)
• Over voltage protection (OVP) output or programmable VID offset
• Programmable soft start
• Optimized for VRM/VRD 10.X specifications
• 20 MHz Gain bandwidth amplifier
• Enable input

Applications

• Supports FPA
• Intel® VR10.X CPU Power
• Workstation CPU Power
• Isolated DC-DC Converters Package
• 24-Lead (4mm x 4mm) QFN Typical Circuit Vin PRM-AL VTM PI1004 VoutVf Vref VID DAC } D0-D5+ ZVS VI K Figure 1 - Basic connection in FPA application.

Description

The PI1004 IC combines a Voltage Identification Digital Input (VID) controlled reference with control and supervisory functions to accurately set the regulator output voltage at the point of load, for isolated and CPU DC-DC converters in desktop and server applications. The PI1004 feature set is intended to be used in conjunction with a variety of power architectures, including Factorized Power Architecture (FPA), to provide CPU power in accordance with Intel ® VR10.X requirements. The feature set includes a precision error amplifier for remote differential sensing of the output voltage, a six bit programmable VID reference voltage output with 12.5 mV resolution, and flexible adaptive voltage positioning. The regulation voltage can also be sh ifted below the VID range with a programmable offset current. The controller includes an over-voltage indi cator output, an open collector power-good output, under-voltage lockout and an externally programmable soft start. The PI1004 is available in two options; PI1004-1 : Programmable VID offset current and no OVP output. The VID offset current is used to create an offset to the DAC output. PI1004-2: OVP output and no VID offset.

Picor Corporation • picorpower.com PI1004 Data Sheet Rev. 2.5 Page 2 of 16 Pin Description PIN # Pin Name Description 1- 6 VID[0:5] Voltage identification digital inputs. The VID inputs program the reference voltage on the REFOUT pin. Tying all VID pins high is treated as a fault and sets the fault latch. To hardwire the VID code, the inputs may be connected to Vcc or SGND as applicable. See Table 1 for VID codes. 7 PWRGD Power-good open-collector output. This pin is an open circuit when (REFIN-230 mV) ≤ VO ≤ (REFIN+160 mV) and the input bus voltage is not in a UVLO condition. When VO is outside the VO window, (REFIN- 230 mV ) < VO < (REFIN+160 mV) or the input bus voltage is in a UVLO condition, or if the ENABLE is low, the PWRGD output is low. 8 OFFSET PI1004-1 only. Provides a programmable VID offset current. A current equal to the current out of the OFFSET pin is added to IAVP to provide a fixed negative offset. To program the offset connect aresistor between OFFSET and SGND. The current is nominally equal to 0.25 V / ROFFSET. Not used tie to Vcc. 8 OVP PI1004-2 only. Over-voltage protection signal, TTL output. When VO ≥ (REFIN+220 mV) and the input bus voltage is not in a UVLO condition and ENABLE is high, OVP is high. When VO < (REFIN+220 mV) or the input bus voltage is in a UVLO condition, or ENABLE is low, OVP is low. 9 ENABLE Logic input control of biasing. If ENABLE = low the PI1004 is disabled and quiescent current is reduced to <400 uA. If ENABLE = high the PI1004 is enabled and the part operates normally if Vcc > UVLO. 10 SS Soft start programming terminal. The error amp non-inverting input (EAIP) is clamped below the level of the SS pin. An internal 5uA charging current is provided to program soft start with an external capacitor. Soft start pin is discharged and held low with ENABLE low, UVLO, or VID=x11111. To control soft-start connect a capacitor between the SS pin and SGND. 11 VO Output voltage positive sense signal used for the power good and over-voltage protection circuits. Connect directly to the output or if feedback divider is employed, connect to the output through a voltage divider with the same ratio as the feedback divider. 12 ISN Load current negative sense terminal. Connect ISN to the negative side of the sense resistor. If AVP is not used, tie ISN to SGND. 13 ISP Load current positive sense terminal. Connect ISP to the positive side of the sense resistor to detect load current for AVP. If AVP is not used, tie ISP to SGND. 14 RG Adaptive voltage positioning gain resistor connection. The sink current from the IAVP pin is: IAVP = 4*[V(ISP)-V(ISN)]/RG. If AVP is not used, tie RG to Vcc. 15 IAVP Adaptive voltage positioning sink current. This pin sinks current proportional to the load. Connect to the EAIP pin with an AVP resistor (RAVP) tied from EAIP to REFOUT. The regulator output voltage will drop with increasing load. If AVP is not used, connect IAVP to Vcc. 16 REFIN Reference input voltage for the over-voltage protection and power good indicators. Normally REFIN is tied to REFOUT. 17 EAIP Non-inverting input to the error amplifier. If AVP and offset are not used, connect EAIP to REFOUT. To use AVP connect directly to IAVP and to REFOUT through a resistor. 18 EAIN Inverting input to the error amplifier. Connect EAIN to the positive remote output voltage sense point through the feedback network. Run in parallel to the SGND connection to avoid noise pick-up. 19 EAO Error amplifier output terminal. 20 REFOUT Reference output voltage as defined by the VID codes in Table 1. The reference is capable of sourcing up to 1 mA of current. In a typical CPU application REFOUT is connected to REFIN to set the thresholds for Power Good and to EAIP through a resistor to enable Adaptive Voltage Positioning. 21 VCC Internal circuit supply. Bypass Vcc to SGND with a 0.1 µF capacitor. 22 SGND Internal substrate connection and negative output voltage sense terminal. Connect to the negative remote output voltage sense point and run in parallel with the positive sense line to avoid noise pick-up. 23,24 NC No connect. Post package programming pin.

Picor Corporation • picorpower.com PI1004 Data Sheet Rev. 2.5 Page 3 of 16 Absolute Maximum Ratings Package Connection Diagram Electrical Specifications Unless otherwise specified: -40°C < Tj < 125 °C, 4.5V < VCC < 13.2V These are stress ratings only and functional operation of the device at these ratings is not implied. Exposure to absolute maximum rating conditions for extended periods of time may affect reliability. VID5:0, ENABLE, SS, ISN, ISP, RG, IAVP, EAIP, Soldering Temp. IR or Convection PARAMETER MIN TYP MAX UNIT CONDITIONS SUPPLY SYSTEM Operating current 5 7 mA Enable > 0.8 V, VCC=9 V Shutdown current 160 400 µA Enable < 0.3 V Input supply range (Vcc) 4.5 13.2 V UV start threshold (Vcc) 4.1 4.3 4.5 V UV stop threshold (Vcc) 4.0 4.2 4.4 V UV hysteresis 30 130 200 mV VID REFERENCE System set point accuracy 0°C ≤ TA ≤ 70°C, VCC=8.5 V For all VID codes, measured (See Table 1 for nominal voltage.) -0.8 +0.8 % at EAO in unity gain Line regulation -0.05 0.05 % / V 0°C ≤ TA ≤ 70°C REFOUT drive capability 1 mA Input logic low 0.4 V Input logic high 0.8 V VID input bias current 0.1 µA ERROR AMPLIFIER Open loop gain 80 110 dB EAIP = 1.25 V Unity gain bandwidth 20 MHz Output slew rate 14 V/µsec 30 pF load Error amp source current 4 9 mA Error amp sink current 250 500 µA Input bias current 0.6 2 µA Input offset current 60 nA Input offset voltage -3 3 mV Unity Gain. EAIP = 1.25 V Common mode input range -0.05 Vcc - 2 V Output voltage range 0.5 Vcc -1.6 V CMRR 80 dB PSRR 80 dB 24-Lead (4mm x 4mm) QFN * Pin 8 has a different function for each PI1004 version: PI1004-1 pin 8 is OFFSET PI1004-2 pin 8 is OVP

Picor Corporation • picorpower.com PI1004 Data Sheet Rev. 2.5 Page 4 of 16 PARAMETER MIN TYP MAX UNITS CONDITIONS POWER GOOD OUTPUT (see Note1) Under-voltage trip threshold -280 -230 -185 mV 0°C ≤ TA ≤ 70°C Under-voltage clear threshold -185 -150 -100 mV 0°C ≤ TA ≤ 70°C Under-voltage hysteresis -100 - 80 -50 mV 0°C ≤ TA ≤ 70°C Over-voltage trip threshold 125 160 +185 mV 0°C ≤ TA ≤ 70°C Over-voltage clear threshold 75 110 +135 mV 0°C ≤ TA ≤ 70°C Over-voltage hysteresis 35 50 80 mV 0°C ≤ TA ≤ 70°C Output low 0.4 V IPWRGD = 4 mA (Enabled) IPWRGD = 250 µA (Disabled) PWRGD blanking TIME 50 100 300 µsec ENABLE INPUT Logic low threshold 0.3 V Logic high threshold 0.8 V 0°C ≤ TA ≤ 70°C Open circuit voltage 1.8 V Input pull-up current 2 µA OVP CIRCUIT (PI1004-2 only) (see Note1) Over-voltage trip threshold 180 220 250 mV 0°C ≤ TA ≤ 70°C Over-voltage clear threshold 120 150 180 mV 0°C ≤ TA ≤ 70°C Over-voltage hysteresis 40 70 100 mV 0°C ≤ TA ≤ 70°C OVP logic high 2.5 3.5 4.5 V Iovp = -2 mA OVP logic high current 2 4.5 mA OVP logic low 0.4 V Iovp = 0.5 mA OVP response time 0.5 µsec VO pin input current 0.25 0.6 µA REFIN pin input current 0.25 0.6 µA SOFT START CIRCUIT SS charge current 3 5 7 µA 0°C ≤ TA ≤ 70°C SS discharge current 0.2 0.7 mA SS clamp voltage 2.3 2.6 2.9 V SS reset voltage 0.2 0.25 0.3 V SS discharge voltage 0.1 V AVP CIRCUIT Common mode input voltage range -0.05 0.4 V Differential input voltage range 0 135 mV AVP current sink range 200 µA IAVP transconductance 0.97 1.00 1.03 mS RG=4 kΩ, ISP = 135 mV ISN = 0V IAVP headroom 0.2 V Input bias current, ISP, ISN 5 µA Programmable VID OFFSET (PI1004-1 only) OFFSET output voltage 240 250 260 mV R OFFSET = 10 kΩ OFFSET to IAVP headroom 0.2 V Electrical Specifications (continued) Note 1: Power good and overvoltage inputs are referenced to VO-REFIN

Table 1. Voltage Identification

1. (EAO) is equal to the maximum output voltage specified by the Intel design guide,

Voltage Regulator-Down (VRD) 10.0, February 2004.

1. EAO is held low during VID OFF codes.

a programmed VID offset function and no OVP function. DAC provides a minimum increment resolution of 12.5mV. will be explained further in the other sections. reflected as a sink current at the IAVP pin 15. AVP correction for load setting the slope of the load line. the fault conditions will result in a full soft-start interval. Table 2. I/O Functional States

Picor Corporation • picorpower.com PI1004 Data Sheet Rev. 2.5 Page 7 of 16 Applications Description becomes the control reference. The amplifier EAIN inverting input and the EAO output pin can be configured as a unity gain follower or as an inverting amplifier with the proper feedback components to set the close loop gain and frequency response of the voltage control loop. Differential sensing is accomplished by referencing the entire PI1004 to the negative return of the load (typically CPUVSS). The SGND pin serves a dual purpose of returning the PI1004 VCC current and sensing the low side of the load. The internal reference "rides" on SGND to compensate for voltage changes at the load. Special care must be taken in the layout to avoid noise pick-up or offsets due to ground loop currents. Fault Circuitry There are three input conditions that will set the fault latch determined by ENABLE, VIDOFF or UVLO states as shown in Table 2. Any fault will clamp the non-inverting error amp input (EAIP) and SS pin to SGND. The fault latch is reset when the SS pin drops below 0.25 V AND all faults are cleared at the Set dominant latch input. Power Good and Over-Voltage Protection The PWRGD and OVP (OVP in PI1004-2 only) pins provide output signals when the output voltage exceeds internally set thresholds. The inputs to the PWRGD and OVP comparators are referenced to REFIN and VO. The PWRGD and OVP signals are outputs for system use and do not trigger an internal fault. Programmable VID Offset REFOUT is set to the VR10 maximum output voltage according to Table 1. For PI1004-1, the no-load VID output voltage can be reduced to accommodate various load line tolerance bands with the OFFSET function. Once the value of RAVP has been chosen for the desired load line, ROFFSET can be selected for the required no-load offset. Refer to Figure 4d to determine resistor values setting the AVP and Offset parameters. Figures 5-10 demonstrate some of the dynamic performance of these functions such as AVP response time, REFOUT response to VID change, VID blanking interval, error amplifier unity gain slew rate and soft-start response to stepped Vcc in that order. Figures 11-14 demonstrate typical DAC error performance at specific temperatures and Figure 15 demonstrates the VID performance from -55 to 125 degrees Celsius at VID=1.2V. The PI1004 products were developed to enable Vicor’s FPA (Factorized Power Architecture) to meet Intel’s requirements defined in VRM/VRD 10.X specifications. A simplified schematic representation of this topology is shown in Figure 4a. DC Performance data of this configuration using the PI1004-1 is shown in Figures 16-17 and dynamic performance is shown in Figures 18a-g, 19a-b and 20. In addition to FPA applications, independent functions of the PI1004 can be used in different combinations as building blocks in control applications. The PI-1004 can be used as a VID controlled reference in an embedded power converter circuit. The PI1004 error amp can be configured as a unity gain buffer to provide the VRD capable reference to the non-inverting input to the control amp. If AVP is required, a method for sensing the load current would need to be implemented. In isolated applications as shown in Figure 4b, the reference and error amplifier might replace a TL431 (Vcc power is required for the PI1004) while the PWRGD, OVP and AVP blocks replace a quad comparator. The PI1004 is a candidate for any application that uses a reference and several amplifiers or comparators especially where digital or hard-wire setting of voltages can be accommodated. The IC can be used as a programmable reference control for a converter or power supply with a positive reference based trim configuration as shown in Figure 4c. For these applications a programmable output voltage and over- voltage features can be created using the error amp as a buffer creating a VR10 reference for the SC/trim input of the converter. Care must be taken not to exceed the amplifier output sink and source current capabilities and to be compatible with the converter reference pin. The AVP block of circuits can be used to create two independent voltage to current converters providing a sink current that is the sum of the two at the IAVP pin. Again consideration of the specified range for these functions is required. Finally the Power Good block can be used as basic comparators for voltage monitoring with the addition of an independent output on the OVP pin in the PI1004-2 An additional bit of resolution can be added to the DAC by using the circuit shown in Figure 4d with proper sequencing by the microprocessor 6.25 mV increments are possible.

Picor Corporation • picorpower.com PI1004 Data Sheet Rev. 2.5 Page 10 of 16 1110 24 23 OFFSET SS VO ISN NC NC ISP RG IAVP EAIP SGND REFOUT Out - PI1004-1 REFIN

21 VCCVcc

1 VID0

VID_6.25mV RAVP RG Inverted 2N2222 Rsense Roffset RBit 7 RAVP 250 6.25 Figure 4d - Application circuit using the AVP and Offset features of the PI1004-1 plus optional 7 Bit resolution. Note: Inverted forced Beta of Q2 βI = IE ≤ 0.01 Example IEQ2 = 10µA IB = 10µA =1mA R2 = VIDpullup – 0.6V IB R1 = 10 • R2 IB 0.01 Component value selection for AVP, Offset and 7 Bit resolution Example a. Select AVP droop voltage at full load ΔVDROOP = 100mV b. Select I AVP droop current at full load (200µA max) ΙAVP = 100µA c. Select current sense input voltage at maximum load (V ISP – VISN) VSENSE = 120mV d. Select V Offset voltage level to center DAC voltage VOFFSET = 25mV e. Add VID6 (seven bit) resolution Q1, Q2 circuit 1. R AVP = ΔVdroop = 100mV= 1KΩ 2. RG = 4•VSense = 4•120mV= 4.8KΩ 3. R Offset = 250mV•RAVP = 250mV•1KΩ = 10KΩ 4. RBit7 = 250mV

• RAVP = 250mV
• 1KΩ = 40KΩ 5. I EQ2 = 250mV = 250mV = 6.25µA IAVP 100µA VOffset 25mV RBit7 40KΩ 6.25mV 6.25mV IAVP 100µA See R1 and R2 Note above.

E D A NXL e NXb MILLIMETERS 0.08mm(.003") 0.10mm(.004") E2/2 D2/2 Top View Side View Bottom View Controlling Dimensions: Millimeters PICOR 1004-X (LOT#) DATE CODE DIM MIN NOM MAX MIN NOM MAX D 4.00 .157 E 4.00 .157 e 0.50 .020 INCHES Picor Corporation • picorpower.com PI1004 Data Sheet Rev. 2.5 Page 15 of 16 Package Description Layout Guidelines Good layout technique is required for systems that combine sensitive amplifiers and switching converters. Extra care must be taken to provide high frequency decoupling and to avoid introducing noise at sensitive nodes.

• The capacitors for V CC decoupling and Soft Start should provide low impedance paths to each pin and be referenced to SGND close to the PI1004.
• The connections from load V SS to SGND and the load VCC to EAIP form an output voltage sense pair and should be routed in parallel to avoid noise pick-up. If the layout allows PI1004 return current to flow through the load V SS to SGND connection, trace resistance must be considered to avoid an excessive offset voltage within the trace.
• The PI1004 EA integrator capacitor should be routed in a short loop to minimize noise pick-up. G and ROFFSET should be tied to SGND near the PI1004 to avoid noise pickup. PARAMETER SYMBOL TYPICAL UNIT Maximum Junction-to-Ambient 2 θJA 46 °C/W Maximum Junction-to-Case θJC 2° C / W Thermal Resistance Ratings PART NUMBER PACKAGE BRANDING TEMP. RANGE TRANSPORT MEDIA PI1004-1-QAHG 24 lead (4mm x 4mm) QFN 1004-1 -40°C to 125°C T&R PI1004-2-QAHG 24 lead (4mm x 4mm) QFN 1004-2 -40°C to 125°C T&R

Ordering Information

Note 2: In accordance with JEDEC JESD 51-5 Note 3: This product is MSL classified at the peak soldering reflow temperature listed in the Absolute Maximum Rating section to meet the lead free requirements of the joint IPC® and JEDEC® standard J-STD-020C.

Picor Corporation • picorpower.com • PI1004 Data Sheet P/N 28955 Rev. 2.5 10/05 Vicor’s comprehensive line of power solutions includes high-density AC-DC & DC-DC modules and accessory components, fully configurable AC-DC & DC-DC power supplies, and complete custom power systems. Information furnished by Vicor is believed to be accurate and reliable. However, no responsibility is assumed by Vicor for its use. No license is granted by implication or otherwise under any patent or patent rights of Vicor. Vicor components are not designed to be used in applications, such as life support systems, wherein a failure or malfunction could result in injury or death. All sales are subject to Vicor’s Terms and Conditions of Sale, which are available upon request. Specifications are subject to change without notice. Vicor Corporation

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Tel: 800-735-6200 Fax: 978-475-6715 Email Vicor Express: vicorexp@vicr.com Technical Support: apps@vicr.com