PHY1076

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1. Ordering Information Please refer to the Packaging section for test and package location ordering code definitions. Part Number Description Package PHY1076-01QD-RR Enhanced 2.7G LASER driver and Post Amp QFN36, 6mmx6mm in Tape and Reel , RoHS compliant (see Figure 41) PHY1076-01QS-RR NOT FOR USE IN NEW DESIGNS Enhanced 2.7G LASER driver and Post Amp QFN36, 6mmx6mm in Tape and Reel , RoHS (see Figure 41) 2. Pin Description Pin No Name Direction Type Description

1 SA_SDA

1,4 I/O LVTTL 2-wire serial interface. Connects to EEPROM in stand-alone mode

2 RESET I/P CMOS Reset

3 VDD_RXO

Power Limiting amplifier output power supply

4 VSS_RX

Ground Receiver section ground connection 5 RXOUT- O/P CML Limiting amplifier differential serial data output. 6 RXOUT+ O/P CML Limiting amplifier differential serial data output.

7 SDA

I/O LVTTL 2-wire serial data interface. Used in Digital Diagnostics Mode.

8 SCL

I/P LVTTL 2-wire serial interface clock. Used in Digital Diagnostics Mode.

9 RREF I/P Analog Connect to Ground through a 10k resistor

10 TX_FAULT O/P LVTTL

(open collector) Transmit fail alarm. A logic 1 indicates a fault in the transmission system. Requires external pull up for SFP MSA compliance

11 TX_DISABLE

I/P LVTTL Output disable (active high). Disables Laser drive. On chip 8k pull up

12 VSS_TX

Ground Transmission circuitry ground connection

13 TXIN+ I/P CML Differential Laser driver input from host

14 TXIN- I/P CML Differential Laser driver input from host

15 RATESEL I/P LVTTL Toggles between two low pass filter characteristics. External 30k pull down resistor required for SFP MSA compliance

16 VSS_TX

Ground Transmission circuitry ground connection 17 NC No connection. Leave open circuit

18 MPD I/P Analog Monitor photodiode input

19 LASER_BIAS O/P Analog Laser bias current output

20 VDD_TX

Power Transmission circuitry power supply connection

21 VDD_TXO

Power Transmission circuitry power supply connection

22 VSS_TX

Ground Transmission circuitry ground connection

23 LASER- O/P High speed Laser differential driver output

24 LASER+ O/P High speed Laser differential driver output

25 VSS_TX

Ground Transmission circuitry ground connection

26 VGG Ground Ground substrate connection

27 VDD_TX

Power Transmission circuitry power supply connection

28 SHUTDOWN O/P CMOS Gate drive for optional Laser shutdown FET switch

29 TSENSE I/P Analog External temperature sensing transistor connection

30 RSSI I/P Analog Receive signal strength indicator & regulated supply for Rx

31 LOS O/P LVTTL

(open collector) Loss of signal output. Requires external pull up for SFP MSA compliance

32 RXIN+ I/P CML Limiting amplifier differential serial data input

33 RXIN- I/P CML Limiting amplifier differential serial data input

34 VSS_RX

Ground Receiver ground connection

35 VDD_RX

Power Limiting amp power supply

36 SA_SCL

1,4 I/P LVTTL EEPROM 2-wire serial interface clock - PADDLE Ground Ground / Thermal Paddle

1 Used in stand-alone mode only

2 All VDDs are internally connected by back-to-back protection diodes. VDDs should not be powered up independently. 3 All VSSs are internally connected to the IC substrate connection. 4 Internally pulled high with an 8kΩ pull-up resistor.

1. Key Specifications 3.1. Absolute Maximum Ratings Parameter Conditions Min Typ Max Unit Supply Voltage - 0.5 +6.5 V Voltage on any pin VSS - 0.5 VDD + 0.5 V Storage Temperature 150 °C Soldering Temperature For 25 seconds 260 °C Junction Temperature 140 °C ESD Human Body Model 2 kV Under absolute maximum rating conditions device not guaranteed to meet specifications; permanent damage may be incurred by operating beyond these limits. 3.2. Continuous Ratings Parameter Conditions Min Typ Max Unit Operating Supply Voltage Continuous operation 2.97 3.3 3.63 V Current consumption Idd = Iddo + (Km*Imod) + (Kb*Ibias) mA Current Consumption (Iddo) High Swing, OMA LOS, Vref = 113 2448Mbps Filter 155Mbps Filter 118 110 mA Current consumption (Km) 0.536 Current consumption (Kb) 0.075 Operating temperature Ambient Still Air, Max Bias and Modulation Current -40 25 +95 °C 3.3. Receiver 3.3.1. Receive Limiting Amplifier Parameter Symbol Conditions Min Typ Max Unit Sensitivity Differential, BER=1*10 -12 (125 - 2.125Gbps) 5 7.5 mVpp Max Differential Input TJ within spec 1200 mVpp Input Return Loss Differential, f<2GHz, device powered on 10 dB Output Return Loss Differential, f<2GHz, device powered on 10 dB Low Frequency Cutoff High pass 3dB point for RX system 15 kHz Differential Output Swing High swing mode Low swing mode 800 400 1100 520 mVpp Total Jitter, Tj Measured over RX input voltage range 125Mbps - 2.7Gbps 100 mUI pp Duty Cycle Distortion 125Mbps - 2.7Gbps 40 60 % Output Resistance RXOUT+/- Single ended to VDD_RXO 40 50 60 Ω

Parameter Symbol Conditions Min Typ Max Unit Input Impedance Differential RXIN+ to RXIN-, DC 85 115 Ω Rate select change time t_ratesel Using RATESEL pin 5 µs Output Rise and Fall Times (20%-80%)

155 Mbps filter, slow CMLslew = ‘1’ , low swing 200 300

155 Mbps filter, fast CMLslew = ‘0’, low swing 192 300

155 Mbps filter, slow CMLslew = ‘1’ , high swing 261 400

155 Mbps filter, fast CMLslew = ‘0’, high swing 253 400

2488 Mbps filter, slow CMLslew = ‘1’ , low swing 71 100

2488 Mbps filter, fast CMLslew = ‘0’, low swing 63 90

2488 Mbps filter, slow CMLslew = ‘1’, high swing 96 120

2488 Mbps filter, fast CMLslew = ‘0’, high swing 83 110

3.3.2. R SSI Indicator and Rx PD Regulator Parameter Symbol Conditions Min Typ Max Unit Voltage on RSSI pin Ireg=2mA (10nF & 100Ω minimum load) 2.4 V Current sourced by RSSI pin Measured using Rx Power ADC 0 2000 µA 3.3.3. Receive Photocurrent LOS Parameter Symbol Conditions Min Typ Max Unit RSSI LOS assert time 10 µs RSSI LOS de-assert time 40 µs Electrical Hysteresis 20log10 (RSSIdeassert / RSSIassert) 2 4 dB RSSI LOS assert level range Set by AVG_LOS_set, Address F4h 4.0 411 µA 3.3.4. OMA LOS Parameter Symbol Conditions Min Typ Max Unit OMA LOS assert time t_loss_on 100 µs OMA LOS de-assert time t_loss_off 20 µs Electrical Hysteresis 20log10 (Vdeassert / Vassert) 2.5 5.5 dB OMA LOS assert level Set by OMA_LOS_set, Address F3h 10 50 mV

t_loss_on t_loss_off OMA Signal LOS Figure 3 - OMA LOS Detection 3.4. Transmitter 3.4.1. Transmitter Inputs Parameter Symbol Conditions Min Typ Max Unit High-Speed Data Input Signal Voltage Differential, AC-coupled, from 125Mbps to 2.7Gbps 200 2400 mVpp High-Speed Data Input Impedance Differential, DC 80 100 120 Ω Input Return Loss Differential, f<2GHz, device powered on 10 dB Input common mode return loss Both inputs shorted together, measured using 25Ω source termination, 100MHz – 2.5GHz 10 dB 3.4.2. Laser Driver Parameter Symbol Conditions Min Typ Max Unit Modulation Current Imod 7 70 mA Electrical 20% to 80% rise / fall time Measured using 50Ω effective termination, AC and DC coupled applications 55 65 ps Total Jitter contribution Measured over modulation current range 100 mUI pp Laser output compliance range Allowed voltage for Laser driver output pins in dynamic operation, referenced to ground (VSS_TX). 600 mV Bias current output compliance Minimum allowed voltage for pin LASER_BIAS, referenced to ground (VSS_TX) 300 mV 3.4.3. Laser Mean Power Control Loop Parameter Symbol Conditions Min Typ Max Unit Bias Current 0.5 100 mA Bias current off Transmitter disabled 10 µA Max current at MPD pin Sink current 2.6 mA Turn on/off overshoot Bias current overshoot, Loop_BW=1 15 % APC -3dB Loop Bandwidth f Loop_BW Loop_BW = “0” Loop_BW = “1” 5 15 kHz Bias loop settling time t_settle Loop_BW = “0” Loop_BW = “1” 5 500 ms µs

3.4.4. Eye Safety Internal Fixed Limits Operation outside these limits causes a TX_FAULT to be asserted Parameter Symbol Conditions Min Typ Max Unit High supply voltage assert limit VeyeHa 3.75 4.10 V High supply voltage de-assert limit V eyeHd 3.65 4.05 V High Supply Hysteresis 0.05 0.15 V Parameter Symbol Conditions Min Typ Max Unit Low supply voltage assert limit V eyeLa 2.70 2.95 V Low supply voltage de-assert limit V eyeLd 2.75 2.95 V Low Supply Hysteresis 0.01 0.15 V RREF pin voltage limit RREF voltage applied to pin after calibration 0.9 1.1 V 3.4.5. Fault Timing Parameter Symbol Condition Min Typ Max Unit Time to initialize t_init From power on or application of Vcc>2.97V during plug in 300 ms Hard TX_DISABLE assert time t_off Time from rising edge of TX_DISABLE to when the optical output falls below 10% of nominal 2 µs Hard TX_DISABLE negate time t_on Time from falling edge of TX_DISABLE to when the modulated optical output rises above 90% of nominal 800 µs Hard TX_FAULT assert time t_fault Time from fault to TX_FAULT on 100 µs TX_DISABLE pulse width t_reset Time TX_DISABLE must be held high to reset TX_FAULT 5 µs TX_FAULT deassert time t_faultdass Time to deassert TX_FAULT after TX_DISABLE 300 ms

3.5. 2-Wire Serial Interface 3.5.1. AC Electrical Characteristics Parameter Symbol Comment Min Typ Max Unit SCL clock frequency fSCL 0 100 kHz LOW period of the SCL clock tLOW 4.7 – µs HIGH period of the SCL clock tHIGH 4.0 – µs Set-up time for a repeated START condition t SU:STA 4.7 – µs Hold time (repeated) START condition t HD:STA 4.0 – µs Data hold time tHD:DAT 0 3.45 µs Data set-up time tSU:DAT 250 – ns Rise time of both SDA and SCL signals tR – 1000 ns Fall time of both SDA and SCL signals tF – 300 ns Set-up time for STOP condition t SU:STO 4.0 – µs Bus free time between a STOP and START condition t BUF 4.7 – µs Output fall time from VIHmin to VILmax tof 10pF < Cb(1) < 400pF 0 250 ns Capacitance for each I/O pin C i See note 1 – 10 pF 1 Cb = capacitance of a single bus line in pF. tHD:STA tSU:STA tHIGH tLOW tSU:DAT tHD:DAT tR tF tSU:STO tBUF SDA SCL oft Figure 6 - SDA and SCL bus timing

3.5.2. DC Electrical Characteristics Parameter Symbol Condition Min Typ Max Unit Low level input voltage VIL - 0.5 0.3 VDD V High level input voltage VIH 0.7 VDD VDD + 0.5 V Low level O/P voltage VOL 3 mA sink current 0 0.4 V I/P current each I/O pin Ii 0.1VDD < Vi < 0.9VDD -10 10 mA 3.5.3. DC Characteristics: TX_FAULT; TX_DISABLE;LOS Parameter Comment Min Typ Max Unit LVTTL Voltage Out High External 4.7k to 10k pull-up Host VCC - 0.5 Host VCC + 0.3 V LVTTL Voltage Out Low External 4.7k to 10k pull-up 0 0.5 V LVTTL Voltage In High Internal pull-up 2.0 VDD + 0.3 V LVTTL Voltage In Low Internal pull-up 0 0.8 V R pull-up Internal pull-up 6 10 kΩ

1. Functional Description 4.1. Overview RSSI RAM LASER safety 2-wire slave LOS AGC Receiver LOS CML RXIN+ RXIN- Programmable LPF Modulation DAC Mean power DAC Bias current LASER+ LASER- LASER_BIAS MPD Transmitter Safety critical shutdown SHUTDOWN TX_FAULT Control interface 2-wire master Control registersController TX_DISABLE RXOUT+ RXOUT- TXIN+ TXIN- RESET SDA SA_SDA SA_SCL SCL TSENSE RREF Temperature ADC RATESEL Comp Figure 10 - Top-level block diagram of the PHY1076-01

4.2. Receiver Features The receiver input is designed to be AC -coupled to the transimpedance amplifier, with internal 100 Ω differential termination. The AGC amplifier is followed by a low -pass filter with programmable cut -off frequency, enabling the PHY1076-01 receiver to support six discrete data rates in the range 1 25 Mbps to 2.7 Gbps. The filter output is followed by a limiting stage. F or minimum duty cycle distortion, DC feedback from the limiter output is used for offset cancellation. The output CML buffer completes the receiver chain, delivering the output at pins RXOUT+ and RXOUT -. The output edge rate is dependent on the programmable filter setting. Additionally, the output swing is programmable to satisfy different interface requirements (e.g. CML, AC-coupled LVPECL compatible). The PHY1076-01 includes a regulator to deliver a controlled voltage to the receiver photodiode cathode at the RSSI pin. The current at RSSI is digitized for use in measuring the received signal strength. This signal can also be used to generate a Loss of Signal (LOS) alarm, with a pre- set hysteresis for assert and de-assert levels. The LOS assert threshold can be adjusted using the LOSS LEVEL DAC. Alternatively, the LOS alarm can be programmed to detect the amplitude of the AC signal, the Optical Modulation Amplitude (OMA) at the receiver input. The OMA LOS assert threshold can be adjusted using the RX AMP DAC. 4.2.1. Input Stage Configuration The differential RXIN inputs from the ROSA can be terminated to a common mode voltage. This should be used for all recommended application frequencies of the PHY1076-01, where the inputs are AC coupled. The common mode voltage should be connected by setting RX_dccouple = ‘0’ (E8h rxControl0 bit 3). 4.2.2. Rate Selection Figure 11 - Low pass filter rate selection A programmable low pass filter provides band limiting in the received signal path. The filter bandwidth is set to 0.75 x signal data rate for optimum signal to noise performance and is controlled by a 3- bit control word as shown in Table 1. The rate selection register, rateSel , stores two 3 -bit codes for controlling the filter; code A in bits 0 to 2, and code B in bits 3 to 5. The selection between the two codes is determined by the RATESEL pin and the Soft Rate Select bit as shown in Figure 11 . Thus, the RATESEL pin can be used to switch between two pre-selected rates. The rateSel register is unique in that it is directly accessible from the 2-wire serial slave interface. Write accesses are routed to both the register in hardware and the RAM. Read accesses read the rateSel value from the hardware. This enables the PHY1076-01 to respond more quickly to updates of this register. This also means that during the intialization sequence, the bandwidth of the receiver can be set up before the dsfail alarm is cleared (see Section 5.2.2). This feature does not exist in the 2-wire serial master interface. When loading registers from EEPROM, rateSel is loaded via RAM in the same way as all other registers. signal out RATESEL F5h 0 - 2 RateselA RateselB rateSel Programmable low-pass filter bit 3 Soft Rate Select STAT_CON signal in 6Eh 3 - 5

Table 1 - Signal data rates supported by the low pass filter 4.2.3. CML Output Stage Configuration The CML output stage has two slew rate settings. For maximum receiver eye opening set CMLslew = ‘0’ (E8h rxControl0 bit 0). To minimize emitted radiation set CMLslew = ‘1’. The slew rates are defined in the table of Parametric Performance characteristics for the Receive limiting amplifier (Section 3.3.1). The signal swing can also be adjusted. Set HiLoSwing = ‘1’ (E9h rxControl1 bit 1) for higher amplitude differential output swing as defined in the table in section 3.3.1. Set HiLoSwing = ‘0’ for lower amplitude output swing. 4.2.4. Loss Of Signal RXIN+ RSSI RX AMP DAC OMA based LOS RXIN- E8h bit 2 bit 1 LOSpolarity LOStype rxControl0 Amplitude detect LOS LEVEL DAC Power detect Rx Power ADC OMA_LOS_setF3h rxPowerADCFBh AVG_LOS_setF4h Mean Rx power based LOS LOS LOS STAT_CON6Eh bit 1 Figure 12 - Control of the LOS pin Loss of signal (LOS) is determined in one of two ways. If LOStype = ‘1’ then the optical modulation amplitude (OMA) method is selected. The signal amplitude measured at RXIN+/- is compared against a threshold level set by the OMA_LOS_set register. If the OMA does not exceed the threshold then the LOS pin and consequently the LOS bit in STAT_CON will be asserted. If LOStype = ‘0’ then the mean received power based method is selected. The signal power detected on the receiver signal strength indicator (RSSI) pin is compared against a threshold level set by AVG_LOS_set. If the RSSI does not exceed the threshold then the LOS pin and LOS bit are asserted. The polarity of the LOS pin is controlled by LOSpolarity. If LOSpolarity = ‘0’ then LOS is set high during a loss of signal condition. Conversely, if LOSpolarity = ‘1’ then LOS is set high when a signal is detected. Bit 2 1 0 Data Rate 0 0 0 125/155 Mbps 0 0 1 622 Mbps 0 1 0 1062 Mbps 0 1 1 1250 Mbps 1 0 0 2125 Mbps 1 0 1 2488 Mbps 1 1 0 No Filter 1 1 1 N/A

4.3. Transmitter Features The transmitter input buffer provides the necessary drive to the Laser driver output stage. It is designed to be AC-coupled, with an internal 100Ω differential termination. The Laser driver output is designed to drive Laser s in common -anode configuration, using either AC or DC coupling. The driver circuit delivers a maximum peak to peak modulation current of 70mA. The maximum current delivered in DC -coupled mode is dependent on the Laser impedance. The voltage swing must remain in the compliance range of the output stage as specified in section 3.4.2. The PHY1076-01 Laser driver operates with an analog mean -power control loop, which is digitally programmed using the Mean Power DAC. Modulation current is controlled by a Laser modulation DAC with the characteristics shown in Table 3. The modulation DAC has a 375μA/bit resolution which suggests an upper limit of 96mA at full scale, however the modulation output stage is rated to 70mA only for jitter compliance. To satisfy the digital diagnostics requirements, the mean power, as represented by the monitor photocurrent, is measured using the MPD current monitor analogue to digital converter (Tx Power ADC). The bias current ADC (Tx Bias ADC) samples the Laser bias current. Register DAC Step Size Rated Range tx_power_set Mean Power DAC (8 bits) 11µA±1.0µA (Actual DAC range 0μA to 3060μA) 0 to 3mA modulationDACDefault Laser modulation DAC1 (8 bits) 363μA±50µA (Actual DAC range is 0mA to 93mA) 7mA to 70mA

1 Range of modulation current measured at LASER+/- (jitter within spec)

Table 3 - Characteristics of the modulation and bias current DACs 4.3.1. Bias Current Control E0h 1 - 2 Kselect txControl1 DFh bit 1 Loop_BW txControl0 MPDtxPowerADCFDh LASER_BIAS tx_power_setF2h txBiasADCFCh Tx Power ADC Mean Power DAC Comp Kfactor Tx Bias ADC VDD Figure 15 - Control registers affecting the APC loop The Laser bias current is controlled by the mean -power control loop in which the current from the monitor photodiode in the TOSA is compared with a reference current controlled by tx_power_set. Note: the comparator is sensitive to large step changes in the value written to tx_power_set (or a small step change at low values). This can cause the safety critical shutdown module to assert a TX_FAULT, as will writing zero to tx_power_set. Loop bandwidth and Kselect are used to optimize APC loop dynamics providing stability of the mean power control and the required transmitter start up time. These settings are affected by the coupling coefficient (Kfactor) between the Laser and monitor photodiode. The Kselect bits shown in Table 4 should be used as a guide for the set -up. For example, for a TOSA with Kfactor of 1/100 ( Laser bias current = 50mA, monitor diode current = 0.5mA) set Kselect = “01”.

Table 4 shows Kselect values that can be chosen to meet the start -up time and APC loop stability requirements: Coupling coefficient Kselect value 1 0 N/A 0 0 1/500 – 1/50 0 1 1/50 – 1/25 1 0 1/25 – 1/8 1 1 Table 4 – Kselect guide for the APC loop The bandwidth of the control loop response can be controlled with Loop_BW . For a critically damped loop, set Loop_BW to ‘0’. For a more rapid response, set Loop_BW to ‘1’. The frequency response of the loop is detailed in section 3.4.3 Laser Mean Power Control Loop. 4.3.2. Modulation Current Control The modulation current can be controlled in two ways: Set ModLUTdisab (DFh txControl0 bit5) to ‘1’ to directly access the modulation DAC. Then, adjust modulation current by writing to modulationDACDefault (D5h). Set ModLUTdisab to ‘0’ to enable the modulation current vs. temperature look -up table (LUT) in the PHY1076-01. The 45 byte LUT is indexed by the value in temperatureADC (FEh), where Index is given by: Index = (temperatureADC x 45) / 255 and the index rounds down to the lower temperature. When the LUT is switched from the enabled to disabled state, the last control value from the LUT will persist. On disabling the LUT the modulation DAC will not revert back to a value previously written to modulationDACDefault . A new value must be explicitly written to modulationDACDefault once the LUT has been disabled. On power up the modulation DAC will not be programmed with the value uploaded from the EEPROM and will default to taking the value from the LUT for the measured temperature. 4.3.3. Laser Driver Setup There is a trimming network on the output driver which adjusts the time constant for output damping on LASER ± . It is controlled by the value in txDriverCap (F6h) which is used to set the value of the time constant as shown in Table 5 based on the number of RC networks turned on. Set txDriverCap to '00' for no damping and fastest edge s. It is possible to enable combinations by programming txDriverCap with values that set more than one bit high. e.g. txDriverCap = 07h enables RxC/2 + RxC + Rx2C. Table 5 -Time constant selection for the Tx output damping network. txDriverCap Time constant (RC=34ps) Bit 0 RxC/2 Bit 1 RxC Bit 2 Rx2C Bit 3 Rx3C Bit 4 Rx4C Bits 5 to 7 Not used C 2C 3C 4C R R R R R C/2 LASER +/- From modulation driver Bit 4Bit 3Bit 2Bit 1Bit 0

power up or after a fault, there will be a short period during which the bias control loop is allowed to settle (t_settle, see Section 3.4.3) before the safety control loop circuit is enabled. Fault Status SDpolarity (TxControl2, Bit 3) SHUTDOWN Pin Voltage No Fault

0 High

1 Low

0 Low

1 High

Table 6 – Shutdown Output Voltage under Fault/No Fault conditions 4.4.2. MCU and Host Fault Management The MCU is responsible for maintaining and reporting alarms and warnings in accordance with the SFF- 8472 specification. When an alarm is triggered, the MCU must set HostSFTtxfault = ‘1’. This will cause the PHY1076-01 to report a fault on the TX_FAULT pin and in the STAT_CON register. The PHY1076-01 will not disable the Laser at this point. The MCU or the host could disable the Laser when a TX Fault is detected in STAT_CON by asserting Soft Tx Disable. 4.4.3. Watchdog A watchdog is implemented by the PHY107 6-01 to monitor the activity of the attached MCU in digital diagnostics mode. When WatchdogEn (E1h txControl2 bit0) is set to ‘1’, the PHY107 6-01’s watchdog feature is enabled. The MCU is required to increment the Watchdog[0:5] counter (E1h txControl2 ) at least every 100ms. If no change is detected in the counter, the PHY1076-01 will disable the Laser and will assert TX_FAULT. The Laser will be re -enabled, and TX_FAULT de-asserted when either the watchdog counter is incremented, or the watchdog feature is disabled by writing ‘0’ to WatchdogEn. On power up the watchdog feature is disabled.

4.5. Tsense Temperature Sensor The temperature is determined by measuring the BEΔV across an external transistor connected to the TSENSE pin. The transistor can be any standard npn silicon transistor with a beta > 100 connected in diode mode (base and collector tied together). It is recommended to use a BC847B or similar. Calibration and averaging of the temperature sensor readings using an external microcontroller are required to optimize the accuracy. Once optimiz ed, the PHY1076-01 can report temperature to SFF8472 requirements over the recommended operating conditions. The temperature sensor operating range and corresponding TSENSE input levels are shown in Table 7. Symbol Unit Minimum Maximum Temperature t °C -70 +115 TSENSE delta input voltage BEΔV mV 50 100 Table 7 – Temperature sensor operating range TSENSE Temperature ADC Signal Conditioning Switching Current Generator i10uAi200uA ∆VBE Figure 17 – Temperature sensor functional block diagram

5.2. Operation SCL RESET 2-wire serial interface slave EEPROM SA_SDA 2-wire serial interface master RAM Controller Hardware registers STAT_CON6Eh Host or MCU SDA SA_SCL arbiter alarmBytePHY107678h testControl79h modulationDACDefaultD5h txPowerDownD6h rxPowerDownDBh txControlDFh-E1h diagnosticsSelectE7h E8h-E9h rxControl F1h-F4h DACs F5h rateSel F6h txDriverCap FBh-FFh ADCs 7Fh tableSelect Figure 20 - Serial interfaces to RAM and the on-chip controller 5.2.1. Data Transfer Mechanisms Three distinct data paths are identified in Figure 20. When the PHY107 6-01 comes out of reset, the 2- wire serial slave interface is disabled. Only path 1 is active. The controller instructs the 2-wire serial master interface to attempt to transfer A2h register tables (SFF-8472 diagnostics and device settings) from the external EEPROM to RAM. If this is successful then the PHY1076-01 will operate in stand-alone mode. If the transfer fails, then the dsfail and eerxfail alarm bits in the alarmBytePHY107 6 (78h) register will be set and the PHY1076-01 will operate in diagnostics mode. Regardless of the outcome, when the EEPROM read process is complete the controller enables the 2-wire serial slave interface. The 2-wire serial master interface is then no longer used. The 2-wire serial slave interface has slave address A2h. In diagnostics mode, the host or external MCU uses the 2-wire serial slave interface to write to or read from copies of the device settings held in RAM. When the boot sequence is complete, the controller transfers data between the RAM and the actual registers implemented in hardware periodically every 10ms. In stand-alone mode the RAM space is not used once the boot sequence is complete. Reading from A2h will return zero. Path 3 is a special case which supports modules designed for stand- alone mode, enabling them to be set up or re -configured via the 2- wire serial interface slave . The PHY1076-01 can be forced into diagnostic mode if the data integrity numbers in the EEPROM are deliberately erased (see section 5.4.2). This enables the host/ MCU to access both the RAM (path 2) and the EEPROM (path 3). All accesses to the A0h address space are directed to the EEPROM only. Accesses to the A2h address space are examined as they arrive by the 2- wire serial slave module, which in turn instructs the arbitration logic. The destination for the transaction depends on the value of tabsel and the register address as shown in T able

write 00 lower RAM + EEPROM write 00 upper EEPROM write 03 upper RAM 1 Addresses 00h to 7Fh = lower. Addresses 80h to FFh = upper. Table 8 - Destination of 2-wire serial interface transactions as a function of write protection, tabsel and address. 5.2.2. Device Initialisation Sequence The Initialisation Sequence is illustrated in Figure 21. The Data_Ready_Bar bit in the STAT_CON register indicates when data from the ADCs may be read after power up. It is first set to ‘1’ before the 2-wire serial slave interface is enabled to indicate that the PHY1076-01 is not ready. Once initialisation is complete and the ADC data is ready Data_Ready_Bar is cleared to ‘0’. This event can be used by the external host/MCU as a signal that the PHY1076-01 is ready for device settings to be uploaded from the MCU to the PHY1076-01 RAM. The PHY1076-01 will not enter the main diagnostic function loop until the upload is complete. This is initiated by the host/MCU clearing the dsfail and eerxfail bits in the alarmBytePHY1076 (78h) register. When dsfail is cleared and the main loop is executed the contents of RAM will be transferred into the hardware registers of the PHY1076-01.

Success? Power up Transfer A2h registers from EEPROM to RAM Disable 2-wire serial slave interface Set dsfail alarm bit. Disable the LASER. Set Data_Ready_Bar. Yes No Diagnostic modeStand-alone mode Enable 2-wire serial slave interface 40 ms delay Start the 10ms poll timer Read ADCs WAIT WAIT Update TX_FAULT pin. Update STAT_CON register. Clear Data_Ready_Bar. WAIT dsfail set? Yes No DIAG MAIN Update TX_FAULT pin and STAT_CON register based on hardware status. Transfer RAM content to hardware registers. Erase RAM. Disable the LASER. Set Data_Ready_Bar. Enable 2-wire serial slave interface 15 ms delay Start the 10ms poll timer WAIT Read ADCs WAIT Index LUT using temp ADC value. Transfer value to modulation DAC. Enable LASER S-A MAIN When Data_Ready_Bar is cleared, the host/MCU can start to upload A2h register settings to the PHY1076-01. The PHY1076-01 waits for the host/MCU to finish the upload. When the upload is complete the host/MCU clears the dsfail bit. Wait for analogue circuits to finish initializing. Time delay, ms Figure 21 - PHY1076-01 initialisation sequence. Time delays for key stages are shown in ms.

5.2.3. Polling Loop Timer Figure 22 - PHY1076-01 polling loop timer function. A polling loop timer is implemented in the controller which expires every 10ms. This is used to schedule functions in both the boot sequence and the main diagnostic and stand-alone operating modes. The WAIT clouds shown in the flow diagrams represent the sequence of events shown in Figure 22. The reset timer is the timer enabled by wdInhibit in the diagnosticsSelect register (E7h). Refer to the registers map for details. The checksum function is executed in diagnostic mode only. The PHY1076-01 will generate a checksum of the device settings RAM area by addition of each of the bytes listed in Table 9, and store the result in the 16 bit ddmChecksum register (E5h to E6h) in big endian format. The checksum will allow the MCU to efficiently verify that the copies of these registers in the PHY1076-01 and in its own memory are coherent. Address Size (bytes) Name 80h 40 Reserved A8h 45 currentLUT D6h 1 txPowerDown D7h 4 undefined DBh 1 rxPowerDown DCh 3 undefined E8h 2 rxControl F1h 1 Vref F2h 1 tx_power_set F3h 1 OMA_LOS_set F4h 1 AVG_LOS_set F5h 1 rateSel Table 9 - Registers included in the checksum calculation MBIST selected Restart the poll timer. (Refresh the reset timer) Yes No WAIT No Timer expired Yes No Calculate checksum (Diagnostic mode only) Enter Memory BIST mode

5.3. Digital Diagnostics Mode 5.3.1. Introduction When used in digital diagnostic mode the PHY107 6-01 contains all of the necessary analogue and digital circuitry to generate the real time values required for SFF-8472 DDM reporting compliance. The power supply voltage, Temperature, TxBias, MPD and RSSI are all sampled using an on board A/D converter. The digitized values are then made available over the slave 2 -wire serial interface, such that they can be used in conjunction w ith SFF -8472 calibration constants, to provide the host user with the following five real time reports: Supply Voltage, Temperature, Tx Bias current, Tx Output Power and Rx Input Power. 5.3.2. On Chip Analogue to Digital Converter The PHY1076-01 contains a single successive approximation ADC. The ADC coding is either linear or multi- slope, depending on the parameter being sampled. The multi-slope stage enables the ADC to cover the very large dynamic range required for reporting Tx and Rx optical power within the S FF-8472 limits, using only 8- bits to cover an equivalent 12-bit dynamic range. The ADC conversion time takes approximately 1ms. 5.3.3. ADC Characteristics DDM Name ADC input Nominal Range Step Size Slope Accuracy Accuracy Supply Voltage VDD Min 1.6 – 1.9V 11 mV ±1.5mV Max 4.1 – 5.0V Temperature Temperature -70°C to +115°C 0.83 °C Tx Bias TxBias 0.0mA to 100mA 0.5mA Tx Power MPD 0.0µA to 32.0µA 0.96µA ±0.2μA ±3μA Offset 32.0µA to 416.0µA 4.2µA ±0.4μA 416.0µA to 2448.0µA 16 µA ±1.5μA Rx Power RSSI 0.0µA to 32.0µA 1.07µA ±0.2μA ±3μA Offset 32.0µA to 416.0µA 4.3µA ±0.4μA 416.0µA to 2448.0µA 17.3µA ±1.5μA Table 10 – ADC electrical characteristics 5.3.4. 3- Slope ADC Tx and Rx Power DDM reports are represented by an 8 bit (0- 255) ADC value even though the overall dynamic range for both of these parameters is 0µ A to 2448 µ A. A linear coding scheme would only provide 9.5µA resolution at low currents. Acceptable low current resolution coupled with wide dynamic range is possible by using a multi -slope gain stage within the ADC circuitry. The following formulae are used to convert the 8-bit ADC (0 to 255) value into a linear pseudo 12-bit ADC (0 to 2448) value: 0 < ADC ≤ 32: ADC_L = ADC 32 ≤ ADC ≤ 128 ADC_L = ((ADC – 32) * 4) + 32 128 ≤ ADC ≤ 255 ADC_L = ((ADC – 128) *16) + 416

Tx MPD Current / Rx RSSI Current (uA) ADC value (dec) Figure 25– 3-slope ADC Function 5.3.5. ADC DDM Register Locations The 8-bit ADC values can be accessed in their raw format at addresses FBh to FFh (tabsel = 03h). The ADC values are also accessible at addresses 60h to 69h (tabsel = 00h) where Tx Power and Rx Power ADC values are linearized by the PHY107 6-01 and, therefore, do not require any conversion from 3- slope format unlike the raw 8-bit ADC values. An external MCU is required to apply the correct calibration slope and offset values to the PHY1076-01 ADC DDM reports in order that the real time reports are meaningful. Table 11 shows the memory locations that should be addressed on the 2-wire slave interface to access the various DDM ADC values. All 8 bit or 12 bit ADC values are left aligned into the 16 bit registers with unused bits set to zero. For example the MSBit of Tx Output Power is located at the MSBit of 66h (tabsel = 00h). Address Location Name Size Table Select Byte (7F) = 00h A2h 60h to 61h Temperature 16-bit A2h 62h to 63h Vcc 16-bit A2h 64h to 65h Tx Bias 16-bit A2h 66h to 67h Tx Power 16-bit A2h 68h to 69h Rx Power 16-bit Table Select Byte (7F) = 03h A2h FBh rxPowerADC 8-bit A2h FCh txBiasADC 8-bit A2h FDh txPowerADC 8-bit A2h FEh temperatureADC 8-bit A2h FFh vddADC 8-bit Table 11 – ADC DDM register locations

5.4. Stand-Alone Mode In stand-alone mode, the PHY107 6-01 is initializ ed directly from an external 4 kbit (8 x 512 bit) Serial EEPROM. In normal operation, there is no access to the device settings information via the 2- wire serial interface. However, the Serial ID information as specified in the SFP MSA is still accessible. This mode supports temperature compensation of modulation current using a look-up table stored in EEPROM. 5.4.1. Data Integrity Checking The (read-only) ADCs located at addresses FBh to FFh are dual -functioned with (write- only) data integrity registers as follows: Addr Register Value(hex) FBh FCh FDh FEh FFh SerialEepromIdentifier0 SerialEepromIdentifier1 SerialEepromIdentifier2 SerialEepromChecksum0 SerialEepromChecksum1 1Bh 2Ch 3Dh or 4Eh Table 12 - Mapping of the data integrity numbers On power-up, the PHY107 6-01 will attempt to load its RAM from the EEPROM. If this is unsuccessful then eerxfail and dsfail are both set to ‘1’ (78h alarmBytePHY1076) and initialisation will be stalled. If the transfer is successful then the integrity of the data will be checked. This process is carried out in t he following sequence of events. First the PHY1076-01 checks that the data read from EEPROM at addresses FBh to FCh matches the values shown in Table 12. If there is a mismatch then dsfail is set to ‘1’ and initialisation will be stalled. If SerialEepromIdentifier2 = 3Dh then the PHY1076-01 will accumulate a 16 bit checksum for the A2h RAM address range 00h to FAh (excluding 7Fh). If this accumulated checksum does not compare correctly with the two SerialEepromChecksum bytes, then dsfail will be set to ‘1’ and initialisation will be stalled. Once all checks are complete, if no alarms have been set then the hardware registers in the PHY1076-01 are updated from the RAM. Data in RAM addresses FBh to FFh will subsequently be overwritten by the ADCs. 5.4.2. Device Setup If a module is powered up with a blank or corrupted EEPROM then the data integrity checking will fail and initialisation is stalled. However, the PHY107 6-01 can be forced into a ‘setup’ mode if the dsfail alarm is cleared by the host. This then permits the device to be configured and the EEPROM written in-system. To reconfigure or analyse a module with its EEPROM already written, writing zero to the data integrity register addresses in EEPROM will have the effect of forcing the PHY1076-01 into setup mode the next time it is powered up. 5.4.3. Writing to EEPROM The addressing of the RAM in the PHY1076-01 is consistent with the memory map for the module as a whole (see Figure 19). The table containing the SFF -8472 Diagnostics registers is selected by tabsel = 0 and the table containing the Device settings registers is selected by tabsel = 3. The serial EEPROM connected to a PHY1076-01 in stand-alone mode is typically small and is organized as shown below:

Figure 26 - Physical mapping of register tables into the EEPROM in the stand-alone mode The device settings area in EEPROM is effectively stored in the address range normally occupied by the SFF-8472 User EEPROM (in Diagnostics mode). When writing to Device settings two separate write transactions are required: one write (into RAM) with tabsel = 3, and one write (into EEPROM) with tabsel = 0. It is recommended that the write protect funct ionality of the EEPROM is utiliz ed to effectively protect stored settings after programming. SFF-8472 Diagnostic SFP MSA Diag (120) Vendor specific (8) Device settings (128) SFP MSA Serial ID (256) 00h 80h FFh 00h 80h FFh mapped to A0h mapped to A2h

1. Register Map All Maxim Integrated-specific registers are listed in this section. For details of other registers refer to the SFF-8472 Specification for Diagnostic Monitoring Interface for Optical Transceivers. Where a single power -on reset (PoR) value is shown for a range of addresses , that value applies to all bytes in the range. Note that the power on reset values may be overwritten during initialisation by the MCU (or from EEPROM in stand-alone mode). For registers containing a single 8- bit field, the most significant bit of the field is stored in bit 7 of the register byte. Multi-byte registers are stored in big-endian order unless specified otherwise. Note that ‘reserved’ or ‘internal use only’ register bits are specified as read only. These registers should not change from their PoR default settings. 6Eh STAT_CON Status and Control register for some SFF-8472 functions Bit Field name Type PoR 7 Tx Disable State R 0 Digital state of the TX Disable input pin. Updated within 100msec of change of pin.

6 Soft TX Disable R/W 0

Read/write bit that allows software disable of laser. Writing ‘1’ disables laser. This bit is “OR’d” with the hard TX_DISABLE pin value. 5 Reserved R 0 Reserved for future use.

4 Rx Rate Select State R 0

Digital state of the SFP RX Rate Select input pin. Updated within 100msec of change on pin.

3 Soft RX Rate Select R/W 0

Soft RX Rate Select read/write bit that allows software RX rate select. Writing ‘1’ selects full bandwidth operation. This bit is “OR’d” with the RATE_SELECT pin value. 2 TX Fault R 0 Digital state of the TX_FAULT output pin. Updated within 100msec of change on the pin. 1 LOS R/W 0 Digital state of the LOS output pin. Updated within 100msec of change on the pin.

0 Data_Ready_Bar R 0

Indicates PHY1076-01 has achieved power up and data is ready. Bit remains high until data is ready to be read at which time the device sets the bit low.

Status register for the PHY1076-01 control module. Bit Field name Type PoR

7 Wd4 R 0

This counter records the number of times that the PHY1076-01 has reset itself due to an internal timeout. The timer is controll ed by wdInhibit in the diagnosticsSelect register.

6 Wd3 R 0

5 Wd2 R 0

4 Wd1 R 0

3 Wd0 R 0

2 membistPassed R 0 Built-in self test (BIST) result (‘1’ = passed) from memory test initiated by testControl register bit 1. 1 dsfail R/W 0 Data structure corrupt (‘1’ = data integrity bytes read from EEPROM during power up are incorrect). Clearing this bit during initialisation is necessary in order to allow the PHY107 6-01 to resume its normal mission mode functions. 0 eerxfail R 0 EEPROM dma load fail. (‘1’ = no response from EEPROM during power up) 79h testControl This register puts the device into various test modes and should not be written to during normal operation. It should always have value ‘0’. Bit Field name Type PoR

7 ATBcontrol5 R/W 0 Analog Test Bus Control Bit0

6 ATBcontrol4 R/W 0 Analog Test Bus Control Bit1

5 ATBcontrol3 R/W 0 Analog Test Bus Control Bit2

4 ATBcontrol2 R/W 0 Analog Test Bus Control Bit3

3 ATBcontrol1 R/W 0 Analog Test Bus Control Bit4

2 ATBcontrol0 R/W 0 Analog Test Bus Control Bit5

1 startMemoryBist R/W 0 Set to ‘1’ to initiate Memory built-in self test (MBIST) 0 scanTestMode R/W 0 Set to 1’ to enter Scan test mode. 7Ah shutDownPassword Set to 42h to prevent the safety critical shutdown logic from disabling the Laser when a hardware fault is detected (see also txControl0). Type R/W PoR 00h 7Bh - 7Eh reserved Type R PoR 00h

Indirect addressing for register tables. 00h selects the SFF-8472 Diagnostics and user EEPROM register tables. 03h selects the PHY1076-01 Device settings table. Note that data read from this register is not valid. Type R/W PoR 00h 80h – A7h reserved Type R PoR 00h A8h– D4h currentLUT Modulation current vs. temperature Look -up table (LUT). The 45 entry L UT is indexed using the temperatureADC as follows: (temperatureADC x 45) / 255. Type R/W PoR 00h D5h modulationDACDefault Controls the modulation current (DAC) when the LUT is disabled. During power up, the temperature is sampled and the DAC is re- loaded with a value from the LUT. Type R/W PoR 00h D6h txPowerDown Selectively turns off the power supply to circuits in the transmitter module. ‘0’ = power on. ‘1’ = power off. Bit Field name Type PoR

7 VDDmeaspwrd R/W 0 -

6 TERMpwrd R/W 0 -

5 DACpwrd R/W 0 Power down DAC

4 DRIVERpwrd R/W 0 Power down Laser driver

3 TXBIASpwrd R/W 0 Power down transmit bandgap bias + current gen. (This will completely disable the IC).

2 DBuffApwrd R/W 0 Power down data buffer

1 TEMPpwrd R/W 0 Power down temperature sensor

0 SAFETYpwrd R/W 0 Power down SAFETY logic

DBh rxPowerDown Selectively turns off the power supply to circuits in the receiver module. ‘0’ = power on. ‘1’ = power off. Bit Field name Type PoR

7 LIMITpwrd R/W 0 Power down limiter

6 FILTpwrd R/W 0 Power down RX filter

5 COMPSpwrd R/W 0 ADC Comparator powerdown

4 AMPDETpwrd R/W 0 Power down amplitude detector

3 REGpwrd R/W 0 Power down regulator

2 AGCpwrd R/W 0 Power down AGC amp

1 CMLpwrd R/W 0 Power down CML (RX related)

0 RXBIASpwrd R/W 0 Power down receiver bandgap bias + current gen. DCh- DEh undefined Type R PoR 00h DFh txControl0 Control bits for the transmitter circuits. Bit Field name Type PoR

7 Osc_Mon R/W 0 Multiplexes the internal oscillator onto TX_FAULT pin

for monitoring (oscillator = ‘1’, normal operation = ‘0’)

6 Hardware_ignore R/W 0

Soft Disable for Safety Critical Shutdown. Set to ‘1’ to prevent Laser shutdown when the SCS circuits detect an electrical fault and asserts a tx fault condition.

5 ModLUTdisab R/W 0 Modulation Current LUT loop control (disable LUT =

‘1’)

4 SFTtxfault R/W 0

(Internal use only. Set to ‘0’.) This bit is internally updated and over written by the watchdog counter and is not intended to be used as a software Tx Fault assert function by an external host. Use E1h bit 7 for this purpose. 3 DAC_ready R/W 0 (Internal use only. Set to ‘0’.) 2 testBW R/W 0 (Internal use only. Set to ‘0’.) 1 Loop_BW R/W 0 Controls the average power control loop response. Set to ‘0’ for critical damping. 0 MPC_polarity R/W 1 (Internal use only. Set to ‘1’.)

Control bits for the transmitter circuits. Bit Field name Type PoR 7 Test_comp_hiZ R 0 (Internal use only. Set to ‘0’.) 6 Test_compout_en R 0 (Internal use only. Set to ‘0’.) 5 Test_compout R 0 (Internal use only. Set to ‘0’.) 4 Test_koff R 0 (Internal use only. Set to ‘0’.) 3 SDpolarity R/W 1 Controls the polarity of the SHUTDOWN pin. ( For SHUTDOWN pin = 1 for shutdown, set SDpolarity = 1).

2 Kselect1 R/W 0 Kselect[1:0] selects one of four gain settings for a

gain stage in the aut omatic power control loop (see Table 4). This optimizes the loop gain for the coupling coefficient of the TOSA. 1 Kselect0 R/W 0 0 Tempsel3i R 0 (Internal use only. Set to ‘0’.) E1h txControl2 Control bits for the transmitter circuits. Bit Field name Type PoR

7 HostSFTtxfault R/W 0 Set to ‘1’ to assert a tx fault condition on the

TX_FAULT pin.

6 Watchdog5 R/W 0 When the watchdog counter is enabled, it must be

incremented at least once every 100ms. If this does not occur then the PHY1076-01 will disable the Laser and assert a tx fault condition. Incrementing the counter or disabling the watchdog will cause normal operation to resume.

5 Watchdog4 R/W 0

4 Watchdog3 R/W 0

3 Watchdog2 R/W 0

2 Watchdog1 R/W 0

1 Watchdog0 R/W 0

0 WatchdogEn R/W 0 Watchdog Function Enable (enable = 1)

E5h– E6h ddmChecksum 16-bit checksum updated by the PHY107 6-01 every 10ms. See section 5.2.3 for a detailed description. Type R PoR 00h

E7h diagnosticsSelect Diagnostic functions (for internal use) are controlled by this register. Bit Field name Type PoR 7 - 0 spare 6 - R 0 spare 5 - R 0 spare 4 - R 0 spare 3 - R 0 spare 2 - R 0 spare 1 wdInhibit R/W 0 See also register 78h alarmBytePHY1076. Set to ‘1’ to disable the timer and prevent the chip from resetting itself if the timer is not serviced. Set to ‘0’ for normal operation. 0 tstclksel R/W 0 Set to ‘1 ’ to select the SA_SDA pin as the clock source for the digital macro instead of the internal oscillator. E8h rxControl0 Control bits for the receiver circuits. Bit Field name Type PoR

7 AMPDET

_dcfbdisable R 0 (Internal use only. Set to ‘0’.) 6 Gc_disable R 0 (Internal use only. Set to ‘0’.) 5 AGCdcfb_disable R 0 (Internal use only. Set to ‘0’.) 4 Trimsel R/W 0 (Internal use only. Set to ‘0’.)

3 RX_dccouple R/W 0

For AC coupled input, set to ‘0 ’ to terminate the differential signal at RXIN+/ - to a common mode voltage. Set to ‘1’ when the inputs are DC coupled.

2 LOSpolarity R/W 0 LOS pin sense (‘1’=Signal Detect;’0’=Loss of signal)

1 LOStype R/W 0 LOS Detection Type (‘1’=OMA;’0’=Mean RX power)

0 CMLslew R/W 0 RXOUT+/- slew rate control. Set to ‘0 ’ for a fast sle w rate. Set to ‘1’ for slow slew rate.

Control bits for the receiver circuits. Bit Field name Type PoR 7 - R 0 Spare 6 - R 0 Spare 5 - R 0 Spare

4 LorV R 0 Always set to ‘1’ for laser operation

3 Fosctrim1 R 0 (Internal use only. Set to ‘0’.) 2 Fosctrim0 R 0 (Internal use only. Set to ‘0’.)

1 HiLoSwing R/W 0 Controls the differential swing of the signal output on

RXOUT+/- (‘1’ = high amplitude, ‘0’ = low amplitude) 0 LIM_dcfbdisable R 0 (Internal use only. Set to ‘0’.) EAh - EFh rxControlSpare reserved Type R PoR 00h F0h undefined Type R PoR 00h F1h Vref Reference voltage trim DAC. The reference voltage can be set by adjusting Vref until the desired voltage is seen at pin RREF. RREF is pulled to ground by a 10 K Ω resistor for a 1V reference. Type R/W PoR 71h F2h tx_power_set Sets the Tx mean power DAC. This DAC therefore controls the average output power of the Laser. Type R/W PoR 00h F3h OMA_LOS_set Sets the threshold level for optical measurement amplitude based LOS detection. Type R/W PoR 00h F4h AVG_LOS_set Sets the threshold level for receiver signal strength indicator (RSSI) based LOS detection. Type R/W PoR 00h

Controls the bandwidth of the programmable low pass filter i n the receiver. The two rate selection fields A and B enable switching between two different bandwidths using the RATESEL pin. Bit Field name Type PoR 7 TRIM1 R/W 0 (Internal use only. Set to ‘0’.) 6 TRIM0 R/W 0 (Internal use only. Set to ‘0’.)

5 RateselB2 R/W 0

Rate Selection B. Selects one of six cut-off frequency settings (see Table 1). 4 RateselB1 R/W 0

3 RateselB0 R/W 0

2 RateselA2 R/W 0

Rate Selection A. Selects one of six cut-off frequency settings (see Table 1). 1 RateselA1 R/W 0

0 RateselA0 R/W 0

F6h txDriverCap Selects between different time constants for the trimming network which controls the tx driver output damping (see Table 5). Type R/W PoR 00h F7h- FAh reserved Type R PoR 00h FBh rxPowerADC This register is dual fu nctioned. Reads received optical power, Rx ADC value. Writes data integrity value SerialEepromIdentifier0. Type R/W PoR 00h FCh txBiasADC This register is dual functioned. Reads Laser bias, Tx Bias ADC value. Writes data integrity value SerialEepromIdentifier1. Type R/W PoR 00h FDh txPowerADC This register is dual functioned. Reads transmit optical power , Tx Power ADC value. Writes data integrity value SerialEepromIdentifier2. Type R/W PoR 00h FEh temperatureADC This register is dual functioned. Reads module temperature ADC value. Writes data integrity value SerialEepromChecksum0. Type R/W PoR 00h

FFh vddADC This register is dual functioned. Reads power supply, VDD ADC value. Writes data integrity value SerialEepromChecksum1. Type R/W PoR 00h

1. Simplified Interface Models X Predrive+/- OUT+ OUT- VDD X

50 VCM

Figure 30- Transmit input structure Figure 31- Transmit output structure VDD X VCM RXIN+ RXIN- VDD X RXOUT+ RXOUT- 5050 VDD X VDD X Figure 32- Receive input structure Figure 33- Receive output structure

1. Typical Applications PHY1076-01 SA_SDA 11 12 13 14 15 16 17 18 36 35 34 33 32 31 30 29 28SA_SCL RESETFrom MCU VDD_RXO VSS_RX RXOUT- RXOUT+ SDA SCL RREF +3.3V 10nF 10nF 10nF 10kΩ TX_FAULT +3.3V Host Board 4.7kΩ TX_DISABLE High Speed 100Ω Differential 2-wire serial interface to/from microcontroller From Host (SFP Connector) VSS_TX TXIN+ TXIN- 10nF 10nF VSS_TX RATESEL NC MPD VSS_TX VDD_TX VDD_TXO LASER_BIAS LASER- LASER+ VSS_TX VGG VDD_TX +3.3V 10nF 10nF +3.3V +3.3V +3.3V +3.3V From Host (SFP Connector) 30kΩ High Speed 100Ω Differential VDD_RX VSS_RX RXIN- RXIN+ LOS RSSI TSENSE SHUTDOWN 10nF 10nF 4.7kΩ +3.3V High Speed 100Ω Differential ROSA PD BIAS BC847B or similar Host Board 10nF +3.3V BLM15BD102 BLM15BD102 BLM15BD102 C pF LoadΩ seriesΩ R Ω 100Ω 1nF 5% 0.125W SMT0402 BLM15BD102 Ferrite Bead, Supplier:Murata 10nF 100nF Optional SHUTDOWN FET Figure 38 – PHY1076-01 in DDM Mode

SA_SDA 11 12 13 14 15 16 17 18 36 35 34 33 32 31 30 29 28SA_SCL RESET VDD_RXO VSS_RX RXOUT- RXOUT+ SDA SCL RREF +3.3V 10nF 10nF 10nF 10kΩ TX_FAULT +3.3V Host Board 4.7kΩ TX_DISABLE High Speed 100Ω Differential 2-wire interface used to set-up the PHY1076 and program EEPROM attached to pins 1 & 36. From Host (SFP Connector) VSS_TX TXIN+ TXIN- 10nF 10nF VSS_TX RATESEL NC MPD VSS_TX VDD_TX VDD_TXO LASER_BIAS LASER- LASER+ VSS_TX VGG VDD_TX +3.3V 10nF 10nF +3.3V From Host (SFP Connector) 30kΩ High Speed 100Ω Differential VDD_RX VSS_RX RXIN- RXIN+ LOS RSSI TSENSE SHUTDOWN 10nF 10nF 4.7kΩ +3.3V High Speed 100Ω Differential BC847B or similar Host Board 10nF +3.3V 5% 0.125W SMT0402 4 5 GND SDA SCL WP Vcc +3.3V 8K EEPROM (512 x 8) AT24C04 or similar BLM15BD102 Ferrite Bead, Supplier:Murata No Connection +3.3V +3.3V +3.3V BLM15BD102 BLM15BD102 BLM15BD102 C pF LoadΩ seriesΩ R Ω 10nF 100nF Optional SHUTDOWN FET ROSA PD BIAS 100Ω 1nF Figure 39 – PHY1076-01 in Stand-alone Mode 8.1. Power Supply Connections The PHY1076-01 has been designed as a low power device. In order to achieve low operating power consumption the transmitter and receiver circuitry in the PHY1076-01 share some common internal bias circuitry. This requires that the PHY1076-01 transmitter and receiver be powered up together for correct operation. Powering up the transmitter VDDs and not the receiver VDDs , or the reverse, will not damage the PHY1076-01 but will cause the part to function incorrectly. 8.1.1. Power Supply Filtering Although the Tx VDDs and Rx VDDs should be powered together and therefore, ultimately be connected at a common node, it is beneficial to separately filter the power supplies for the Tx VDD and Rx VDD supplies. Separately filtering the transmitter and receiver supplies off chip will reduce power supply noise and cross talk between the transmitter and receiver – it is generally good practice to separately filter and decouple the individual supplies on any multifunction IC. In addition to supplying separately filtered supplies to the Tx VDDs and Rx VDDs of the PHY1076-01, it is also recommended that any other ICs and digital circuitry connected to the PHY1076-01 in an application environment (e.g. SFP module) be suitably filtered and decoupled also. An example of this would be to supply a filtered digital supply for the external MCU , required to compliment the PHY107 6-01 in DDM SFF-8472 applications.

36 35 34 33 32 31 30 29 28 VDD_RXO VSS_RX RREF RX VDD 10kΩ VSS_TX VSS_TX VSS_TX VDD_TX VDD_TXO VSS_TX VGG VDD_TX 1.0uF +3.3V VDD_RX VSS_RX FERRITE RX VDD TX VDD TX VDD TX VDD CENTRE GROUND PADDLE PCB VIA CONNECT TO GROUND PLANE FERRITE 0.1uF0.1uF 0.1uF0.1uF TX VDD RX VDD Pin 3 Pin 35 Pin 20/21 Pin 27 TX VDD and RX VDD should be separately filtered and well decoupled. A single +3.3V connection should be used to power both TX VDD and RX VDD using a star topology filter scheme as shown above. The PHY1076-01 TX VDDs and RX VDDs should not be independently powered to avoid conduction between TX and RX VDD ESD diode circuits. Figure 40 – Recommended power supply connections and filtering. 8.1.2. Power-On-Reset The PHY1076-01 features an internal power-on-reset function that applies a reset to the digital logic once the supply voltage reaches a preset value (>2.0V). The internal power -on-reset typically takes 27ms after power has been applied based on a 50ms slow start voltage ramp. The PHY107 6-01 may be reset externally by applying a logic low pulse to the reset pin which is internally pulled up. This is useful t o guarantee the state of the PHY1076-01 logic when using the device in conjunction with an external MCU.

1. Packaging Figure 41 - QFN 36 Package Outline Drawing

Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. The parametric values (min and max limits) shown in the Electrical Characteristics table are guaranteed. Other parametric values quoted in this data sheet are provided for guidance. Maxim Integrated 160 Rio Robles, San Jose, CA 95134 USA 1- 408 -601 -1000  2012 Maxim Integrated The Maxim logo and Maxim Integrated are trademarks of Maxim Integrated Products, Inc. 10. Contact Information For technical support, contact Maxim at www.maximintegrated.com/support.