PHX5N50E PHILIPS | Alldatasheet

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Philips Semiconductors Objective specification PowerMOS transistor PHX5N50E Isolated version of PHP8N50E GENERAL DESCRIPTION QUICK REFERENCE DATA N-channel enhancement mode SYMBOL PARAMETER MAX. UNIT field-effect power transistor in a full pack, plastic envelope featuring high VDS Drain-source voltage 500 V avalanche energy capability, stable ID Drain current (DC) 4 A blocking voltage, fast switching and Ptot Total power dissipation 30 W high thermal cycling performance R DS(ON) Drain-source on-state resistance 0.8 Ω with low thermal resistance. Intended for use in Switched Mode Power Supplies (SMPS), motor control circuits and general purpose switching applications. PINNING - SOT186A PIN CONFIGURATION SYMBOL PIN DESCRIPTION 1 gate 2 drain 3 source case isolated LIMITING VALUES Limiting values in accordance with the Absolute Maximum System (IEC 134) SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT V DS Drain-source voltage - 500 V VDGR Drain-gate voltage R GS = 20 kΩ - 500 V ±VGS Gate-source voltage - 30 V ID Drain current (DC) T hs = 25 ˚C - 4 A Ths = 100 ˚C - 2.5 A IDM Drain current (pulse peak Ths = 25 ˚C - 16 A value) IDR Source-drain diode current Ths = 25 ˚C - 4 A (DC) IDRM Source-drain diode current Ths = 25 ˚C - 16 A (pulse peak value) Ptot Total power dissipation T hs = 25 ˚C - 30 W Tstg Storage temperature -55 150 ˚C Tj Junction temperature - 150 ˚C AVALANCHE LIMITING VALUE SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT W DSS Drain-source non-repetitive ID = 8 A; VDD ≤ 50 V; VGS = 10 V; unclamped inductive turn-off RGS = 50 Ω energy T j = 25˚C prior to surge - 510 mJ Tj = 100˚C prior to surge - 82 mJ W DSR

1 Drain-source repetitive ID = 8 A; VDD ≤ 50 V; VGS = 10 V; - 13 mJ

unclamped inductive turn-off RGS = 50 Ω ; Tj ≤ 150 ˚C energy 1. Pulse width and frequency limited by Tj(max) 123 case d g s November 1996 1 Rev 1.000

Philips Semiconductors Objective specification PowerMOS transistor PHX5N50E ISOLATION LIMITING VALUE & CHARACTERISTIC Ths = 25 ˚C unless otherwise specified SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT V isol R.M.S. isolation voltage from all f = 50-60 Hz; sinusoidal - 2500 V three terminals to external waveform; heatsink R.H. ≤ 65% ; clean and dustfree C isol Capacitance from T2 to external f = 1 MHz - 10 - pF heatsink THERMAL RESISTANCES SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT R th j-hs Thermal resistance junction to with heatsink compound - - 4.1 K/W heatsink R th j-a Thermal resistance junction to - 55 - K/W ambient STATIC CHARACTERISTICS Tj = 25 ˚C unless otherwise specified SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT V (BR)DSS Drain-source breakdown V GS = 0 V; ID = 0.25 mA 500 - - V voltage VGS(TO) Gate threshold voltage V DS = VGS ; ID = 0.25 mA 2.0 3.0 4.0 V IDSS Drain-source leakage current VDS = 500 V; VGS = 0 V; Tj = 25 ˚C - 10 100 µA VDS = 400 V; VGS = 0 V; Tj = 125 ˚C - 0.1 1.0 mA IGSS Gate-source leakage current VGS = ±30 V; VDS = 0 V - 10 100 nA R DS(ON) Drain-source on-state V GS = 10 V; ID = 4 A - 0.67 0.8 Ω resistance VSD Source-drain diode forward IF = 8 A ;VGS = 0 V - 1.4 2.0 V voltage November 1996 2 Rev 1.000

Philips Semiconductors Objective specification PowerMOS transistor PHX5N50E DYNAMIC CHARACTERISTICS Tj = 25 ˚C unless otherwise specified SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT g fs Forward transconductance V DS = 15 V; ID = 4 A 4 6 - S C iss Input capacitance V GS = 0 V; VDS = 25 V; f = 1 MHz - 1500 1800 pF C oss Output capacitance - 170 270 pF C rss Feedback capacitance - 70 120 pF Q g(tot) Total gate charge V GS = 10 V; ID = 8 A; VDS = 400 V - 65 - nC Q gs Gate to source charge - 8 - nC Q gd Gate to drain (Miller) charge - 34 - nC td on Turn-on delay time V DD = 30 V; ID = 2.8 A; - 20 40 ns tr Turn-on rise time V GS = 10 V; RGS = 50 Ω ; - 60 90 ns td off Turn-off delay time R GEN = 50 Ω - 200 250 ns tf Turn-off fall time - 75 90 ns trr Source-drain diode reverse IF = 8 A; -dIF/dt = 100 A/µs; - 500 - ns recovery time Q rr Source-drain diode reverse VGS = 0 V; VR = 100 V - 6 - µC recovery charge Ld Internal drain inductance Measured from drain lead 6 mm - 4.5 - nH from package to centre of die Ls Internal source inductance Measured from source lead 6 mm - 7.5 - nH from package to source bond pad November 1996 3 Rev 1.000

Philips Semiconductors Objective specification PowerMOS transistor PHX5N50E MECHANICAL DATA Dimensions in mm Net Mass: 2 g Fig.1. SOT186A; The seating plane is electrically isolated from all terminals. Notes 1. Observe the general handling precautions for electrostatic-discharge sensitive devices (ESDs) to prevent damage to MOS gate oxide. 2. Refer to mounting instructions for F-pack envelopes. 3. Epoxy meets UL94 V0 at 1/8". 10.3 max 3.2 3.0 4.6 max 2.9 max 2.8 seating plane 6.4 15.8 max 0.6 2.5 2.54 5.08 123 3 max. not tinned 0.5 2.5 0.9 0.7 M0.4 15.8 max. max. 13.5 min. Recesses (2x) 2.5 0.8 max. depth 1.0 (2x) 1.3 November 1996 4 Rev 1.000

Philips Semiconductors Objective specification PowerMOS transistor PHX5N50E DEFINITIONS Data sheet status Objective specification This data sheet contains target or goal specifications for product development. Preliminary specification This data sheet contains preliminary data; supplementary data may be published later. Product specification This data sheet contains final product specifications. Limiting values Limiting values are given in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of this specification is not implied. Exposure to limiting values for extended periods may affect device reliability.

Application information

Where application information is given, it is advisory and does not form part of the specification.  Philips Electronics N.V. 1996 All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, it is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent or other industrial or intellectual property rights. LIFE SUPPORT APPLICATIONS These products are not designed for use in life support appliances, devices or systems where malfunction of these products can be reasonably expected to result in personal injury. Philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such improper use or sale. November 1996 5 Rev 1.000