PHT6N03LT PHILIPS | Alldatasheet

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Philips Semiconductors Product specification TrenchMOS  transistor PHT6N03LT Logic level FET FEATURES SYMBOL QUICK REFERENCE DATA

  • ’Trench’ technology VDSS = 30 V
  • Very low on-state resistance
  • Fast switching ID = 5.9 A
  • Stable off-state characteristics
  • High thermal cycling performance R DS(ON) ≤ 30 mΩ (VGS = 5 V)
  • Surface mounting package R DS(ON) ≤ 28 mΩ (VGS = 10 V) GENERAL DESCRIPTION PINNING SOT223 N-channel enhancement mode PIN DESCRIPTION logic level field-effect power transistor using ’ trench’ 1 gate technology. The device has very low on-state resistance. It is 2 drain intended for use in dc to dc converters and general purpose 3 source switching applications. tab drain The PHT6N03LT is supplied in the SOT223 surface mounting package. LIMITING VALUES Limiting values in accordance with the Absolute Maximum System (IEC 134) SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT VDSS Drain-source voltage T j = 25 ˚C to 150˚C - 30 V VDGR Drain-gate voltage T j = 25 ˚C to 150˚C; RGS = 20 kΩ -3 0 V VGS Gate-source voltage - ± 13 V ID Continuous drain current Tamb = 25 ˚C; VGS = 10 V - 5.9 A Tamb = 100 ˚C; VGS = 10 V - 4.1 A IDM Pulsed drain current - 23.6 A PD Total power dissipation T amb = 25 ˚C - 1.8 W Tj, Tstg Operating junction and - 55 150 ˚C storage temperature ESD LIMITING VALUE SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT VC Electrostatic discharge Human body model (100 pF, 1.5 kΩ )- 2 k V capacitor voltage, all pins THERMAL RESISTANCES SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT R th j-sp Thermal resistance junction mounted on any pcb - - 15 K/W to solder point R th j-a Thermal resistance junction mounted on test pcb of fig:17 - 70 - K/W to ambient d g s 1 23 January 1998 1 Rev 1.300

Philips Semiconductors Product specification TrenchMOS transistor PHT6N03LT Logic level FET

ELECTRICAL CHARACTERISTICS

Tj= 25˚C unless otherwise specified SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT V(BR)DSS Drain-source breakdown V GS = 0 V; ID = 0.25 mA; 30 - - V voltage T j = -55˚C 27 - - V V(BR)GSS Gate-source breakdown I G = 1 mA 10 - - V voltage VGS(TO) Gate threshold voltage V DS = VGS ; ID = 1 mA 1 1.5 2 V Tj = 150˚C 0.6 - - V R DS(ON) Drain-source on-state V GS = 5 V; ID = 3.2 A - 24 30 m Ω resistance V GS = 10 V; ID = 3.2 A - 18 28 m Ω VGS = 5 V; ID = 3.2 A; Tj = 150˚C - - 51 m Ω gfs Forward transconductance VDS = 25 V; ID = 5.9 A 8 14 - S IDSS Zero gate voltage drain V DS = 30 V; VGS = 0 V; - 0.05 10 µA current T j = 150˚C - - 500 µA IGSS Gate source leakage current VGS = ±5 V; VDS = 0 V - 0.02 1 µA Tj = 150˚C - - 10 µA Q g(tot) Total gate charge I D = 5.9 A; VDD = 24 V; VGS = 5 V - 24 - nC Q gs Gate-source charge - 3 - nC Q gd Gate-drain (Miller) charge - 11 - nC td on Turn-on delay time V DD = 15 V; ID = 5.9 A; - 30 45 ns tr Turn-on rise time V GS = 5 V; RG = 5 Ω - 80 130 ns td off Turn-off delay time Resistive load - 95 135 ns tf Turn-off fall time - 40 55 ns Ld Internal drain inductance Measured from tab to centre of die - 3.5 - nH Ld Internal drain inductance Measured from drain lead to centre of die - 3.5 - nH Ls Internal source inductance Measured from source lead to source - 7.5 - nH bond pad C iss Input capacitance V GS = 0 V; VDS = 25 V; f = 1 MHz - 1050 - pF C oss Output capacitance - 270 - pF C rss Feedback capacitance - 140 - pF REVERSE DIODE LIMITING VALUES AND CHARACTERISTICS Tj = 25˚C unless otherwise specified SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT IS Continuous source current - - 5.9 A (body diode) ISM Pulsed source current (body - - 10 A diode) V SD Diode forward voltage I F = 5.9 A; VGS = 0 V - 0.75 1.2 V trr Reverse recovery time I F = 5.9 A; -dIF/dt = 100 A/µs; - 100 - ns Q rr Reverse recovery charge V GS = -10 V; VR = 25 V - 0.4 - µC January 1998 2 Rev 1.300

Philips Semiconductors Product specification TrenchMOS transistor PHT6N03LT Logic level FET AVALANCHE LIMITING VALUE SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT W DSS Drain-source non-repetitive ID = 5.9 A; VDD ≤ 15 V; - 60 mJ unclamped inductive turn-off VGS = 10 V; RGS = 50 Ω ; Tamb = 25 ˚C energy Fig.1. Normalised power dissipation. PD% = 100⋅PD /PD 25 ˚C = f(Tamb ) Fig.2. Normalised continuous drain current. ID% = 100⋅ID /ID 25 ˚C = f(Tamb ); conditions: VGS ≥ 5 V Fig.3. Safe operating area. Tamb = 25 ˚C ID & IDM = f(VDS ); IDM single pulse; parameter tp Fig.4. Transient thermal impedance. Zth j-amb = f(t); parameter D = tp/T 0 20 40 60 80 100 120 140 Tamb / C PD% Normalised Power Derating120 110 100 0.1 1 10 100 10000.01 0.1 100 7830-30 VDS / V ID / A RDS(ON) = VDS / ID tp = 10 us 100 us 1 ms 10 ms 100 ms DC 0 20 40 60 80 100 120 140 Ambient temperature, Tamb (C) ID% Normalised Current Derating 120 110 100 1E-07 1E-05 1E-03 1E-01 1E+01 1E+03 BUKX83 t / s Zth j-amb / (K/W) 1E+02 1E+01 1E+00 1E-01 1E-02 0.5 0.2 0.1 0.05 0.02 D = D = tp tp T T P t D January 1998 3 Rev 1.300

Philips Semiconductors Product specification TrenchMOS transistor PHT6N03LT Logic level FET Fig.5. Typical output characteristics, Tj = 25 ˚C. ID = f(VDS ); parameter VGS Fig.6. Typical on-state resistance, Tj = 25 ˚C. R DS(ON) = f(ID ); parameter VGS Fig.7. Typical transfer characteristics. ID = f(VGS ) ; conditions: VDS = 25 V; parameter Tj Fig.8. Typical transconductance, Tj = 25 ˚C. gfs = f(ID ); conditions: VDS = 25 V Fig.9. Normalised drain-source on-state resistance. a = RDS(ON) /RDS(ON)25 ˚C = f(Tj); ID = 3.2 A; VGS = 5 V Fig.10. Gate threshold voltage. VGS(TO) = f(Tj); conditions: ID = 1 mA; VDS = VGS 02468 1 00 BUK9830-30 VDS / V ID / A 2.5 3.5 4.5510 VGS / V = 0 1 02 03 04 05 06 00 9830-30 ID / A gfs / S Tj / C = 25 150 0 1 02 03 04 05 06 00 9830-30 ID / A RDS(ON) / mOhm VGS / V = 4.5 43.53 -50 0 50 100 1500 0.5 1.5

2 SOT223 30V Trench

a Normalised RDS(ON) = f(Tj) 01234560 60 9830-30 VGS / V ID / A Tj / C = 25 150 BUK959-60 -100 -50 0 50 100 150 2000 0.5 1.5 2.5 Tj / C VGS(TO) / V max. typ. min. January 1998 4 Rev 1.300

Philips Semiconductors Product specification TrenchMOS transistor PHT6N03LT Logic level FET Fig.11. Sub-threshold drain current. ID = f(VGS); conditions: Tj = 25 ˚C; VDS = VGS Fig.12. Typical capacitances, Ciss, Coss, Crss. C = f(VDS ); conditions: VGS = 0 V; f = 1 MHz Fig.13. Typical turn-on gate-charge characteristics. VGS = f(QG ); conditions: ID = 5.9 A; parameter VDS Fig.14. Typical reverse diode current. IF = f(VSDS ); conditions: VGS = 0 V; parameter Tj Fig.15. Normalised avalanche energy rating. W DSS % = f(Tamb ); conditions: ID = 5.9 A Fig.16. Avalanche energy test circuit. 0 0.5 1 1.5 2 2.5 31E-05 1E-05 1E-04 1E-03 1E-02 1E-01 Sub-Threshold Conduction 2% typ 98% 0 0.5 1 1.5 20 9830-30 VSDS / V IF / A Tj / C = 150 25 0.1 1 10 100100 1000 10000 9528-30 VDS / V C / pF Ciss Coss Crss 20 40 60 80 100 120 140 120 110 100 WDSS% Ambient temperature, Tamb (C) 0 5 10 15 20 250 9830-30 QG / nC VGS / V VDS / V = 6 24 L T.U.T. VDD RGS R 01 VDS -ID/100 shunt VGS W DSS = 0.5⋅LID 2 ⋅BV DSS /(BV DSS − VDD ) January 1998 5 Rev 1.300

Philips Semiconductors Product specification TrenchMOS transistor PHT6N03LT Logic level FET PRINTED CIRCUIT BOARD Dimensions in mm. Fig.17. PCB for thermal resistance and power rating for SOT223. PCB: FR4 epoxy glass (1.6 mm thick), copper laminate (35 µm thick). 4.6 4.5 January 1998 6 Rev 1.300