PHP8ND50E

PHP8ND50E PHILIPS | Alldatasheet

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Philips Semiconductors Product specification PowerMOS transistors PHP8ND50E, PHB8ND50E, PHW8ND50E FREDFET, Avalanche energy rated FEATURES SYMBOL QUICK REFERENCE DATA

• Repetitive Avalanche Rated VDSS = 500 V
• Fast switching
• Stable off-state characteristics ID = 8.5 A
• High thermal cycling performance
• Low thermal resistance R DS(ON) ≤ 0.85 Ω
• Fast reverse recovery diode trr = 180 ns GENERAL DESCRIPTION N-channel, enhancement mode field-effect power transistor, incorporating aFastR ecoveryEpitaxialD iode (FRED). This gives improved switching performance in half bridge and full bridge converters making this device particularly suitable for inverters, lighting ballasts and motor control circuits. The PHP8ND50E is supplied in the SOT78 (TO220AB) conventional leaded package. The PHW8ND50E is supplied in the SOT429 (TO247) conventional leaded package. The PHB8ND50E is supplied in the SOT404 surface mounting package. PINNING SOT78 (TO220AB) SOT404 SOT429 (TO247) PIN DESCRIPTION 1 gate 2 drain 1 3 source tab drain LIMITING VALUES Limiting values in accordance with the Absolute Maximum System (IEC 134) SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT V DSS Drain-source voltage T j = 25 ˚C to 150˚C - 500 V VDGR Drain-gate voltage T j = 25 ˚C to 150˚C; RGS = 20 kΩ - 500 V VGS Gate-source voltage - ± 30 V ID Continuous drain current Tmb = 25 ˚C; VGS = 10 V - 8.5 A Tmb = 100 ˚C; VGS = 10 V - 5.4 A IDM Pulsed drain current T mb = 25 ˚C - 34 A PD Total dissipation T mb = 25 ˚C - 147 W Tj, Tstg Operating junction and - 55 150 ˚C storage temperature range d g s 12 3 tab tab 2 31 1 It is not possible to make connection to pin 2 of the SOT404 package. August 1998 1 Rev 1.100

Philips Semiconductors Product specification PowerMOS transistors PHP8ND50E, PHB8ND50E, PHW8ND50E FREDFET, Avalanche energy rated AVALANCHE ENERGY LIMITING VALUES Limiting values in accordance with the Absolute Maximum System (IEC 134) SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT E AS Non-repetitive avalanche Unclamped inductive load, IAS = 6.2 A; - 510 mJ energy t p = 0.18 ms; Tj prior to avalanche = 25˚C; VDD ≤ 50 V; RGS = 50 Ω ; VGS = 10 V; refer to fig:17 EAR Repetitive avalanche energy2 IAR = 8.5 A; tp = 1 µs; Tj prior to - 19 mJ avalanche = 25˚C; RGS = 50 Ω ; VGS = 10 V; refer to fig:18 IAS , IAR Repetitive and non-repetitive - 8.5 A avalanche current THERMAL RESISTANCES SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT R th j-mb Thermal resistance junction - - 0.85 K/W to mounting base R th j-a Thermal resistance junction SOT78 package, in free air - 60 - K/W to ambient SOT429 package, in free air - 45 - K/W SOT404 package, pcb mounted, minimum - 50 - K/W footprint 2 pulse width and repetition rate limited by T j max. August 1998 2 Rev 1.100

Philips Semiconductors Product specification PowerMOS transistors PHP8ND50E, PHB8ND50E, PHW8ND50E FREDFET, Avalanche energy rated

ELECTRICAL CHARACTERISTICS

Tj = 25 ˚C unless otherwise specified SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT V (BR)DSS Drain-source breakdown V GS = 0 V; ID = 0.25 mA 500 - - V voltage ΔV(BR)DSS / Drain-source breakdown V DS = VGS ; ID = 0.25 mA - 0.1 - %/K ΔTj voltage temperature coefficient R DS(ON) Drain-source on resistance VGS = 10 V; ID = 4.8 A - 0.7 0.85 Ω VGS(TO) Gate threshold voltage V DS = VGS ; ID = 0.25 mA 2.0 3.0 4.0 V gfs Forward transconductance VDS = 30 V; ID = 4.8 A 3.5 6 - S IDSS Drain-source leakage current VDS = 500 V; VGS = 0 V - 1 25 µA VDS = 400 V; VGS = 0 V; Tj = 125 ˚C - 40 250 µA IGSS Gate-source leakage current VGS = ±30 V; VDS = 0 V - 10 200 nA Q g(tot) Total gate charge I D = 8.5 A; VDD = 400 V; VGS = 10 V - 88 110 nC Q gs Gate-source charge - 6 7 nC Q gd Gate-drain (Miller) charge - 47 60 nC td(on) Turn-on delay time V DD = 250 V; RD = 30 Ω ; - 18 - ns tr Turn-on rise time R G = 9.1 Ω -5 0-n s td(off) Turn-off delay time - 104 - ns tf Turn-off fall time - 60 - ns Ld Internal drain inductance Measured from tab to centre of die - 3.5 - nH Ld Internal drain inductance Measured from drain lead to centre of die - 4.5 - nH (SOT78 and SOT429 packages only) Ls Internal source inductance Measured from source lead to source - 7.5 - nH bond pad C iss Input capacitance V GS = 0 V; VDS = 25 V; f = 1 MHz - 1060 - pF C oss Output capacitance - 160 - pF C rss Feedback capacitance - 90 - pF SOURCE-DRAIN DIODE RATINGS AND CHARACTERISTICS Tj = 25 ˚C unless otherwise specified SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT I S Continuous source current Tmb = 25˚C - - 8.5 A (body diode) ISM Pulsed source current (body Tmb = 25˚C - - 34 A diode) VSD Diode forward voltage I S = 8.5 A; VGS = 0 V - - 1.5 V trr Reverse recovery time I S = 8.5 A; VGS = 0 V; dI/dt = 100 A/µs - 180 - ns IS = 8.5 A; VGS = 0 V; dI/dt = 100 A/µs; - 220 - ns 125˚C Q rr Reverse recovery charge IS = 8.5 A; VGS = 0 V; dI/dt = 100 A/µs - 0.65 - µC IS = 8.5 A; VGS = 0 V; dI/dt = 100 A/µs; - 2.6 - µC 125˚C Irrm Peak reverse recovery I S = 8.5 A; VGS = 0 V; dI/dt = 100 A/µs; - 15 - A current 125˚C August 1998 3 Rev 1.100

Philips Semiconductors Product specification PowerMOS transistors PHP8ND50E, PHB8ND50E, PHW8ND50E FREDFET, Avalanche energy rated Fig.1. Normalised power dissipation. PD% = 100⋅PD /PD 25 ˚C = f(Tmb ) Fig.2. Normalised continuous drain current. ID% = 100⋅ID /ID 25 ˚C = f(Tmb ); conditions: VGS ≥ 10 V Fig.3. Safe operating area. Tmb = 25 ˚C ID & IDM = f(VDS ); IDM single pulse; parameter tp Fig.4. Transient thermal impedance. Zth j-mb = f(t); parameter D = tp/T Fig.5. Typical output characteristics. ID = f(VDS ); parameter VGS Fig.6. Typical on-state resistance. R DS(ON) = f(ID ); parameter VGS 0 20 40 60 80 100 120 140 Tmb / C PD% Normalised Power Derating120 110 100 1ms 1s0.001 0.01 0.1 PHP6N60Zth j-mb, Transient thermal impedance (K/W) 1us 10us 100us 10ms 100ms tp, pulse width (s) D = tp tp T T P t D D = 0.5 0.2 0.05 0.02 single pulse 0.1 0 20 40 60 80 100 120 140 Tmb / C ID% Normalised Current Derating120 110 100 0 5 10 15 20 25 30 5.5 V 6 V 6.5 V 7 V 10 V PHP8N50 VDS, Drain-Source voltage (Volts) ID, Drain current (Amps) 5 V VGS = 4.5 V Tj = 25 C 1 10 100 1000 VDS / V ID / A100 0.1 BUK457-500B tp = 10 us 100 us 1 ms 10 ms 100 ms DC RDS(ON) = VDS/ID 0 5 10 15 20 25 0.5 1.5

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5 V 5.5 V 10 V ID, Drain current (Amps) RDS(on), Drain-Source on resistance (Ohms)

4.5 V VGS = 6 V Tj = 25 C

6.5 V 7 V August 1998 4 Rev 1.100

Philips Semiconductors Product specification PowerMOS transistors PHP8ND50E, PHB8ND50E, PHW8ND50E FREDFET, Avalanche energy rated Fig.7. Typical transfer characteristics. ID = f(VGS ); parameter Tj Fig.8. Typical transconductance. gfs = f(ID ); parameter Tj Fig.9. Normalised drain-source on-state resistance. a = RDS(ON) /RDS(ON)25 ˚C = f(Tj); ID = 4.25 A; VGS = 10 V Fig.10. Gate threshold voltage. VGS(TO) = f(Tj); conditions: ID = 0.25 mA; VDS = VGS Fig.11. Sub-threshold drain current. ID = f(VGS); conditions: Tj = 25 ˚C; VDS = VGS Fig.12. Typical capacitances, Ciss, Coss, Crss. C = f(VDS ); conditions: VGS = 0 V; f = 1 MHz 02468 1 0 PHP8N50 VGS, Gate-Source voltage (Volts) ID, Drain current (Amps) Tj = 25 C Tj = 150 C VDS > ID x RDS(on)max -60 -40 -20 0 20 40 60 80 100 120 140 Tj / C VGS(TO) / V max. typ. min. 0 5 10 15 20 25

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ID, Drain current (A) gfs, Transconductance (S) Tj = 25 C 150 C VDS > ID x RDS(on)max 0 1 2 3 4 VGS / V ID / A1E-01 1E-02 1E-03 1E-04 1E-05 1E-06 SUB-THRESHOLD CONDUCTION typ2 % 98 % -60 -40 -20 0 20 40 60 80 100 120 140 Tj / C Normalised RDS(ON) = f(Tj) a 1 10 100 100010 100 1000

10000 PHP8N50

VDS, Drain-Source voltage (Volts) Junction capacitances (pF) Ciss Coss Crss August 1998 5 Rev 1.100

Philips Semiconductors Product specification PowerMOS transistors PHP8ND50E, PHB8ND50E, PHW8ND50E FREDFET, Avalanche energy rated Fig.13. Typical turn-on gate-charge characteristics. VGS = f(QG ); parameter VDS Fig.14. Typical switching times; td(on), tr, td(off), tf = f(RG ) Fig.15. Normalised drain-source breakdown voltage; V(BR)DSS /V(BR)DSS 25 ˚C = f(Tj) Fig.16. Source-Drain diode characteristic. IF = f(VSDS ); parameter Tj Fig.17. Maximum permissible non-repetitive avalanche current (IAS ) versus avalanche time (tp); unclamped inductive load Fig.18. Maximum permissible repetitive avalanche current (IAR ) versus avalanche time (tp) 0 50 100 150

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Qg, Gate charge (nC) VGS, Gate-Source voltage (Volts) VDD = 400 V ID = 8.5 A Tj = 25 C 250 V 100 V PHP8N50 VSDS, Source-Drain voltage (Volts) IF, Source-Drain diode current (Amps) VGS = 0 V Tj = 25 C150 C 0 1 02 03 04 05 06 0 100 1000 td(on) PHP8N50 RG, Gate resistance (Ohms) Switching times (ns) Tj = 25 C RD = 30 Ohms VGS = 10 V tf td(off) tr VDD = 250 V PHP8N50E 0.1 1E-06 1E-05 1E-04 1E-03 1E-02 Avalanche time, tp (s) Non-repetitive Avalanche current, IAS (A) 25 C VDS ID tp Tj prior to avalanche = 125 C -100 -50 0 50 100 150 0.85 0.9 0.95 1.05 1.1 1.15 Tj, Junction temperature (C) Normalised Drain-source breakdown voltage V(BR)DSS @ Tj V(BR)DSS @ 25 C PHP8N50E 0.01 0.1 1E-06 1E-05 1E-04 1E-03 1E-02 Avalanche time, tp (s) Maximum Repetitive Avalanche Current, IAR (A) 125 C Tj prior to avalanche = 25 C August 1998 6 Rev 1.100

Philips Semiconductors Product specification PowerMOS transistors PHP8ND50E, PHB8ND50E, PHW8ND50E FREDFET, Avalanche energy rated MECHANICAL DATA Dimensions in mm Net Mass: 2 g Fig.19. SOT78 (TO220AB); pin 2 connected to mounting base. Notes 1. Observe the general handling precautions for electrostatic-discharge sensitive devices (ESDs) to prevent damage to MOS gate oxide. 2. Refer to mounting instructions for SOT78 (TO220) envelopes. 3. Epoxy meets UL94 V0 at 1/8". 10,3 max 3,7 2,8 3,03,0 max not tinned 1,3 max (2x) 123 2,4 0,6 4,5 max 5,9 min 15,8 max 1,3 2,54 2,54 0,9 max (3x) 13,5 min August 1998 7 Rev 1.100

Philips Semiconductors Product specification PowerMOS transistors PHP8ND50E, PHB8ND50E, PHW8ND50E FREDFET, Avalanche energy rated MECHANICAL DATA Dimensions in mm Net Mass: 1.4 g Fig.20. SOT404 : centre pin connected to mounting base. MOUNTING INSTRUCTIONS Dimensions in mm Fig.21. SOT404 : soldering pattern for surface mounting. Notes 1. Observe the general handling precautions for electrostatic-discharge sensitive devices (ESDs) to prevent damage to MOS gate oxide. 2. Epoxy meets UL94 V0 at 1/8". 11 max 4.5 max 1.4 max 10.3 max 0.5 15.4 2.5 0.85 max (x2) 2.54 (x2) 17.5 11.5 9.0 5.08 3.8 2.0 August 1998 8 Rev 1.100

Philips Semiconductors Product specification PowerMOS transistors PHP8ND50E, PHB8ND50E, PHW8ND50E FREDFET, Avalanche energy rated MECHANICAL DATA Dimensions in mm Net Mass: 5 g Fig.22. SOT429; pin 2 connected to mounting base. Notes 1. Observe the general handling precautions for electrostatic-discharge sensitive devices (ESDs) to prevent damage to MOS gate oxide. 2. Refer to mounting instructions for SOT429 envelope. 3. Epoxy meets UL94 V0 at 1/8". 5.3 4.0 max 15.5 min 1 2.2 max 0.4 2.5 0.9 max 5.3 max 3.5 16 max 5.45 seating plane 5.45 M o max 15.5 max 3.2 max 2 3 1.1 3.5 1.8 7.3 max August 1998 9 Rev 1.100

Philips Semiconductors Product specification PowerMOS transistors PHP8ND50E, PHB8ND50E, PHW8ND50E FREDFET, Avalanche energy rated DEFINITIONS Data sheet status Objective specification This data sheet contains target or goal specifications for product development. Preliminary specification This data sheet contains preliminary data; supplementary data may be published later. Product specification This data sheet contains final product specifications. Limiting values Limiting values are given in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of this specification is not implied. Exposure to limiting values for extended periods may affect device reliability.

Application information

Where application information is given, it is advisory and does not form part of the specification.  Philips Electronics N.V. 1998 All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, it is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent or other industrial or intellectual property rights. LIFE SUPPORT APPLICATIONS These products are not designed for use in life support appliances, devices or systems where malfunction of these products can be reasonably expected to result in personal injury. Philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such improper use or sale. August 1998 10 Rev 1.100