PHP52N06T

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N-channel enhancement mode ﬁeld-effect transistor Rev. 01 — 9 January 2002 Product data M3D307 1. Description N-channel enhancement mode ﬁeld-effect power transistor in a plastic package using TrenchMOS™ 1 technology. Product availability: PHP52N06T in SOT78 (TO-220AB). 2. Features ■ Low on-state resistance ■ 175 °C rated. 3. Applications ■ DC to DC converters ■ Uninterruptible power supplies ■ Switched mode power supplies. 4. Pinning information 1. TrenchMOS is a trademark of Koninklijke Philips Electronics N.V. Table 1: Pinning - SOT78, simpliﬁed outline and symbol Pin Description Simpliﬁed outline Symbol 1 gate (g) SOT78 (TO-220AB) 2 drain (d) 3 source (s) mb mounting base; connected to drain (d) MBK106 mb s d g MBB076

Philips Semiconductors PHP52N06T N-channel enhancement mode ﬁeld-effect transistor Product data Rev. 01 — 9 January 2002 2 of 12 9397 750 09121 © Koninklijke Philips Electronics N.V. 2002. All rights reserved. 5. Quick reference data 6. Limiting values Table 2: Quick reference data Symbol Parameter Conditions Typ Max Unit VDS drain-source voltage (DC) - 60 V ID drain current (DC) T mb =2 5°C; VGS =1 0V - 5 2 A Ptot total power dissipation T mb =2 5°C - 118 W Tj junction temperature - 175 °C R DSon drain-source on-state resistance VGS = 10 V; ID =2 5A Tj=2 5°C 1 72 2m Ω Tj= 175°C - 44 m Ω Table 3: Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol Parameter Conditions Min Max Unit VDS drain-source voltage (DC) - 60 V VDGR drain-gate voltage (DC) R GS =2 0kΩ -6 0 V VGS gate-source voltage (DC) - ±20 V ID drain current (DC) T mb =2 5°C; VGS =1 0V ;Figure 2and 3 -5 2 A Tmb = 100°C; VGS =1 0V ;Figure 2 -3 7 A IDM peak drain current T mb =2 5°C; pulsed; tp ≤ 10 µs;Figure 3 - 208 A Ptot total power dissipation T mb =2 5°C; Figure 1 - 120 W Tstg storage temperature −55 +175 °C Tj operating junction temperature −55 +175 °C Source-drain diode I S source (diode forward) current (DC) Tmb =2 5°C - 52 A ISM peak source (diode forward) current Tmb =2 5°C; pulsed; tp ≤ 10 µs - 208 A Avalanche ruggedness E DS(AL) non-repetitive avalanche energy unclamped inductive load; ID =4 8A ; VDS ≤ 55 V; VGS = 10 V; RGS =5 0Ω ; starting Tmb =2 5°C - 115 mJ

Philips Semiconductors PHP52N06T N-channel enhancement mode ﬁeld-effect transistor Product data Rev. 01 — 9 January 2002 3 of 12 9397 750 09121 © Koninklijke Philips Electronics N.V. 2002. All rights reserved. VGS ≥ 4.5 V Fig 1. Normalized total power dissipation as a function of mounting base temperature. Fig 2. Normalized continuous drain current as a function of mounting base temperature. Tmb =2 5°C; IDM single pulse. Fig 3. Safe operating area; continuous and peak drain currents as a function of drain-source voltage. 03aa16 120 0 50 100 150 200 Tmb ( o Pder (%) 03aa24 120 0 50 100 150 200 Tmb ( o Ider (%) P der P tot P tot 25 C°() Ider ID I D2 5C°() 03ag58 102 103 1 10 10 2 VDS (V) ID (A) DC 100 ms R DSon = VDS / ID 10 ms tp = 10 µs 1 ms 100 µs

Philips Semiconductors PHP52N06T N-channel enhancement mode ﬁeld-effect transistor Product data Rev. 01 — 9 January 2002 4 of 12 9397 750 09121 © Koninklijke Philips Electronics N.V. 2002. All rights reserved. 7. Thermal characteristics

7.1 Transient thermal impedance

Table 4: Thermal characteristics Symbol Parameter Conditions Typ Max Unit R th(j-mb) thermal resistance from junction to mounting baseFigure 4 - 1.25 K/W R th(j-a) thermal resistance from junction to ambient vertical in still air 60 - K/W Fig 4. Transient thermal impedance from junction to mounting base as a function of pulse duration. 03ag57 10-2 10-1 10-6 10-5 10-4 10-3 10-2 10-1 1tp (s) Zth(j-mb) (K/W) single pulse δ = 0.5 0.2 0.1 0.05 0.02 tp tp T P t Tδ =

Philips Semiconductors PHP52N06T N-channel enhancement mode ﬁeld-effect transistor Product data Rev. 01 — 9 January 2002 5 of 12 9397 750 09121 © Koninklijke Philips Electronics N.V. 2002. All rights reserved. 8. Characteristics Table 5: Characteristics Tj=2 5°C unless otherwise speciﬁed Symbol Parameter Conditions Min Typ Max Unit Static characteristics V (BR)DSS drain-source breakdown voltage ID = 0.25 mA; VGS =0V Tj=2 5°C 6 0 --V Tj= −55 °C 5 5 --V VGS(th) gate-source threshold voltage ID = 1 mA; VDS =V GS ;Figure 9 Tj=2 5°C 234V Tj= 175°C 1 --V IDSS drain-source leakage current V DS =5 5V ; VGS =0V Tj=2 5°C - 0.05 10 µA Tj= 175°C - - 500 µA IGSS gate-source leakage current V GS = ±20 V; VDS = 0 V - 2 100 nA R DSon drain-source on-state resistance VGS = 10 V; ID =2 5A ;Figure 7and 8 Tj=2 5°C - 17 22 m Ω Tj= 175°C --4 4 m Ω Dynamic characteristics Q g(tot) total gate charge V DD =4 4V ; ID = 40 A; VGS =1 0V ;Figure 13 -3 6 -n C Q gs gate-source charge - 8.4 - nC Q gd gate-drain (Miller) charge - 11.5 - nC C iss input capacitance V GS =0V ; VDS = 25 V; f = 1 MHz;Figure 11 - 1200 1592 pF C oss output capacitance - 290 356 pF C rss reverse transfer capacitance - 179 240 pF td(on) turn-on delay time V DD =3 0V ; RL = 1.2Ω ; VGS =1 0V ;RG =1 0Ω ; -1 5 -n s tr rise time -7 4 -n s td(off) turn-off delay time - 70 - ns tf fall time -4 0 -n s Source-drain diode V SD source-drain (diode forward) voltage IS = 20 A; VGS =0V ;Figure 12 - 0.85 1.2 V trr reverse recovery time I S = 20 A; dIS/dt =−100 A/µs VGS = −10 V; VDS =3 0V -4 5 -n s Q r recovered charge - 110 - nC

Philips Semiconductors PHP52N06T N-channel enhancement mode ﬁeld-effect transistor Product data Rev. 01 — 9 January 2002 6 of 12 9397 750 09121 © Koninklijke Philips Electronics N.V. 2002. All rights reserved. Tj=2 5°C; tp = 300µsT j=2 5°C and 175°C; VDS > ID × R DSon Fig 5. Output characteristics: drain current as a function of drain-source voltage; typical values. Fig 6. Transfer characteristics: drain current as a function of gate-source voltage; typical values. Tj=2 5°C Fig 7. Drain-source on-state resistance as a function of drain current; typical values. Fig 8. Normalized drain-source on-state resistance factor as a function of junction temperature. 03ag59 0 0.4 0.8 1.2 1.6 2 VDS (V) ID (A)

8 VTj = 25 ºC

VGS = 4.5 V 10 V 5.5 V 5 V 6 V 7 V 6.5 V 03ag61

02468 VGS (V)

(A) VDS > ID x RDSon Tj = 25 ºC175 ºC 03ag68 0.005 0.01 0.015 0.02 0 2 04 06 08 0 ID (A) R DSon (Ω ) Tj = 25 ºC 10 V 7 V VGS = 6 V /K30/K33/K61/K61/K32/K38 0.6 1.2 1.8 2.4 -60 0 60 120 180 T j ( o a a R DSon R DSon 25 C°()

Philips Semiconductors PHP52N06T N-channel enhancement mode ﬁeld-effect transistor Product data Rev. 01 — 9 January 2002 7 of 12 9397 750 09121 © Koninklijke Philips Electronics N.V. 2002. All rights reserved. ID = 1 mA; VDS =V GS Tj=2 5°C; VDS =V GS Fig 9. Gate-source threshold voltage as a function of junction temperature. Fig 10. Sub-threshold drain current as a function of gate-source voltage. VGS = 0 V; f = 1 MHz Fig 11. Input, output and reverse transfer capacitances as a function of drain-source voltage; typical values. 03aa32 -60 0 60 120 180 T j ( o VGS(th) (V) max min typ 03aa35 10-6 10-5 10-4 10-3 10-2 10-1 0246 VGS (V) ID (A) maxtypmin 03ag71 102 103 104 10-1 1 10 10 2 VDS (V) C (pF) C iss C oss C rss

Philips Semiconductors PHP52N06T N-channel enhancement mode ﬁeld-effect transistor Product data Rev. 01 — 9 January 2002 8 of 12 9397 750 09121 © Koninklijke Philips Electronics N.V. 2002. All rights reserved. VGS =0V T j=2 5°C; ID =4 0A Fig 12. Source (diode forward) current as a function of source-drain (diode forward) voltage; typical values. Fig 13. Gate-source voltage as a function of turn-on gate charge; typical values. 03ag70 0 0.4 0.8 1.2 V SD (V) IS (A) Tj = 25 ºC175 ºC VGS = 0 V 03ag72 0 2 04 06 08 0 Q G (nC) VGS (V) ID = 25 A Tj = 25 ºC VDD = 14 V 44 V

Philips Semiconductors PHP52N06T N-channel enhancement mode ﬁeld-effect transistor Product data Rev. 01 — 9 January 2002 9 of 12 9397 750 09121 © Koninklijke Philips Electronics N.V. 2002. All rights reserved. 9. Package outline Fig 14. SOT78 (TO-220AB). REFERENCESOUTLINE VERSION EUROPEAN PROJECTION ISSUE DATE IEC JEDEC EIAJ SOT78 SC-46 3-lead TO-220AB D D 1 q p L 123 L1(1) e e b 0 5 10 mm scale Plastic single-ended package; heatsink mounted; 1 mounting hole; 3-lead TO-220AB SOT78 DIMENSIONS (mm are the original dimensions) AE c Note 1. Terminals in this zone are not tinned. Q UNIT A 1 b1 D 1 e p mm 2.54 qQA b Dc L2 max. 3.0 3.8 3.6 15.0 13.5 3.30 2.79 3.0 2.7 2.6 2.2 0.7 0.4 15.8 15.2 0.9 0.7 1.3 1.0 4.5 4.1 1.39 1.27 6.4 5.9 10.3 9.7 L1(1)E L 00-09-07 01-02-16 mounting base

Philips Semiconductors PHP52N06T N-channel enhancement mode ﬁeld-effect transistor Product data Rev. 01 — 9 January 2002 10 of 12 9397 750 09121 © Koninklijke Philips Electronics N.V. 2002. All rights reserved. 10. Revision history Table 6: Revision history Rev Date CPCN Description 01 20020109 - Product data; initial version

Philips Semiconductors PHP52N06T N-channel enhancement mode ﬁeld-effect transistor © Koninklijke Philips Electronics N.V. 2002. All rights reserved. Product data Rev. 01 — 9 January 2002 11 of 12 9397 750 09121 Philips Semiconductors PHP52N06T N-channel enhancement mode ﬁeld-effect transistor © Koninklijke Philips Electronics N.V. 2002. All rights reserved. Product data Rev. 01 — 9 January 2002 11 of 12 Contact information For additional information, please visithttp://www.semiconductors.philips.com. 11. Data sheet status [1] Please consult the most recently issued data sheet before initiating or completing a design. [2] The product status of the device(s) described in this data sheet may have changed since this data sheet was published. The latest information is available on the Internet at URL http://www.semiconductors.philips.com. 12. Deﬁnitions Short-form speciﬁcation —The data in a short-form speciﬁcation is extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook. Limiting values deﬁnition — Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 60134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the speciﬁcation is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information — Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applications will be suitable for the speciﬁed use without further testing or modiﬁcation. 13. Disclaimers Life support —These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application. Right to make changes —Philips Semiconductors reserves the right to make changes, without notice, in the products, including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no licence or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise speciﬁed. Data sheet status[1] Product status[2] Deﬁnition Objective data Development This data sheet contains data from the objective speciﬁcation for product development. Philips Semiconductors reserves the right to change the speciﬁcation in any manner without notice. Preliminary data Qualiﬁcation This data sheet contains data from the preliminary speciﬁcation. Supplementary data will be published at a later date. Philips Semiconductors reserves the right to change the speciﬁcation without notice, in order to improve the design and supply the best possible product. Product data Production This data sheet contains data from the product speciﬁcation. Philips Semiconductors reserves the right to make changes at any time in order to improve the design, manufacturing and supply. Changes will be communicated according to the Customer Product/Process Change Notiﬁcation (CPCN) procedure SNW-SQ-650A.

© Koninklijke Philips Electronics N.V. 2002. Printed in The Netherlands All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights. Date of release: 9 January 2002 Document order number: 9397 750 09121

PHP52N06T specifications and overview.

Summary

N-channel enhancement mode field-effect transistor Rev. 01-9 January 2002

Description

N-channel enhancement mode field-effect power transistor in a plastic package using TrenchMOS™1 technology.

Source title PHP52N06T Datasheet(PDF) - NXP Semiconductors

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