PHP42N03LT PHILIPS | Alldatasheet

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Technical content

Philips Semiconductors Product specification TrenchMOS  transistor PHP42N03LT, PHB42N03LT Logic level FET FEATURES SYMBOL QUICK REFERENCE DATA

  • ’Trench’ technology VDSS = 30 V
  • Very low on-state resistance
  • Fast switching ID = 42 A
  • Stable off-state characteristics
  • High thermal cycling performance R DS(ON) ≤ 26 mΩ (VGS = 5 V)
  • Low thermal resistance R DS(ON) ≤ 23 mΩ (VGS = 10 V) GENERAL DESCRIPTION N-channel enhancement mode logic level field-effect power transistor in a plastic envelope using ’trench’ technology. The device has very low on-state resistance. It is intended for use in dc to dc converters and general purpose switching applications. The PHP42N03LT is supplied in the SOT78 (TO220AB) conventional leaded package. The PHB42N03LT is supplied in the SOT404 surface mounting package. PINNING SOT78 (TO220AB) SOT404 PIN DESCRIPTION 1 gate 2 drain 3 source tab drain LIMITING VALUES Limiting values in accordance with the Absolute Maximum System (IEC 134) SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT VDSS Drain-source voltage T j = 25 ˚C to 175˚C - 30 V VDGR Drain-gate voltage T j = 25 ˚C to 175˚C; RGS = 20 kΩ -3 0 V VGS Gate-source voltage - ± 15 V ID Continuous drain current Tmb = 25 ˚C; VGS = 5 V - 42 A Tmb = 100 ˚C; VGS = 5 V - 30 A IDM Pulsed drain current T mb = 25 ˚C - 168 A PD Total power dissipation T mb = 25 ˚C - 86 W Tj, Tstg Operating junction and - 55 175 ˚C storage temperature d g s tab 12 3 tab November 1998 1 Rev 1.400

Philips Semiconductors Product specification TrenchMOS transistor PHP42N03LT, PHB42N03LT Logic level FET THERMAL RESISTANCES SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT R th j-mb Thermal resistance junction - - 1.75 K/W to mounting base R th j-a Thermal resistance junction SOT78 package, in free air - 60 - K/W to ambient SOT404 package, pcb mounted, minimum - 50 - K/W footprint

ELECTRICAL CHARACTERISTICS

Tj= 25˚C unless otherwise specified SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT V(BR)DSS Drain-source breakdown V GS = 0 V; ID = 0.25 mA; 30 - - V voltage T j = -55˚C 27 - - V VGS(TO) Gate threshold voltage V DS = VGS ; ID = 1 mA 1 1.5 2 V Tj = 175˚C 0.5 - - V R DS(ON) Drain-source on-state V GS = 10 V; ID = 25 A - 16 23 m Ω resistance V GS = 5 V; ID = 25 A - 20 26 m Ω VGS = 5 V; ID = 25 A; Tj = 175˚C - - 48 m Ω gfs Forward transconductance VDS = 25 V; ID = 25 A 8 27 - S IDSS Zero gate voltage drain V DS = 30 V; VGS = 0 V; - 0.05 10 µA current T j = 175˚C - - 500 µA IGSS Gate source leakage current VGS = ±5 V; VDS = 0 V - 10 100 nA Q g(tot) Total gate charge I D = 20 A; VDD = 24 V; VGS = 10 V - 40 - nC Q gs Gate-source charge - 7 - nC Q gd Gate-drain (Miller) charge - 10 - nC td on Turn-on delay time V DD = 15 V; ID = 25 A; - 12 20 ns tr Turn-on rise time V GS = 5 V; RG = 5 Ω - 80 130 ns td off Turn-off delay time Resistive load - 35 60 ns tf Turn-off fall time - 31 45 ns Ld Internal drain inductance Measured tab to centre of die - 3.5 - nH Ld Internal drain inductance Measured from drain lead to centre of die - 4.5 - nH (SOT78 package only) Ls Internal source inductance Measured from source lead to source - 7.5 - nH bond pad C iss Input capacitance V GS = 0 V; VDS = 25 V; f = 1 MHz - 1050 - pF C oss Output capacitance - 270 - pF C rss Feedback capacitance - 140 - pF November 1998 2 Rev 1.400

Philips Semiconductors Product specification TrenchMOS transistor PHP42N03LT, PHB42N03LT Logic level FET REVERSE DIODE LIMITING VALUES AND CHARACTERISTICS Tj = 25˚C unless otherwise specified SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT IS Continuous source current - - 45 A (body diode) ISM Pulsed source current (body - - 180 A diode) VSD Diode forward voltage I F = 25 A; VGS = 0 V - 0.95 1.2 V IF = 40 A; VGS = 0 V - 1.0 - trr Reverse recovery time I F = 40 A; -dIF/dt = 100 A/µs; - 52 - ns Q rr Reverse recovery charge V GS = -10 V; VR = 25 V - 0.08 - µC Fig.1. Normalised power dissipation. PD% = 100⋅PD /PD 25 ˚C = f(Tmb ) Fig.2. Normalised continuous drain current. ID% = 100⋅ID /ID 25 ˚C = f(Tmb ); conditions: VGS ≥ 5 V Fig.3. Safe operating area ID & IDM = f(VDS ); IDM single pulse; parameter tp Fig.4. Transient thermal impedance. Zth j-mb = f(t); parameter D = tp/T 0 20 40 60 80 100 120 140 160 180 Tmb / C PD% Normalised Power Derating120 110 100 1 10 100 100

1000 PHP42N03LT

VDS, Drain-source voltage (Volts) ID, Drain current (Amps) RDS(ON) = VDS/ID 1 ms 100 ms tp = 10us DC 10 ms 100 us Tmb = 25 C 0 20 40 60 80 100 120 140 160 180 Tmb / C ID% Normalised Current Derating 120 110 100 1E-07 1E-05 1E-03 1E-01 1E+010.01 0.1 10 7528-30 t / s Zth j-mb / (K/W) D = tp tp T TP t D D = 0.02 0.05 0.1 0.2 0.5 November 1998 3 Rev 1.400

Philips Semiconductors Product specification TrenchMOS transistor PHP42N03LT, PHB42N03LT Logic level FET Fig.5. Typical output characteristics ID = f(VDS ); parameter VGS Fig.6. Typical on-state resistance R DS(ON) = f(ID ); parameter VGS Fig.7. Typical transfer characteristics. ID = f(VGS ) Fig.8. Typical transconductance gfs = f(ID ) Fig.9. Normalised drain-source on-state resistance. a = RDS(ON) /RDS(ON)25 ˚C = f(Tj) Fig.10. Gate threshold voltage. VGS(TO) = f(Tj); conditions: ID = 1 mA; VDS = VGS 02468 1 0 PHP45N03LT VDS, Drain-Source voltage (Volts) ID, Drain current (Amps) VGS = 2.5 V 3 V 3.5 V 4 V

4.5 V5 V

15 V Tj = 25 C

Drain current, ID (A) Transconductance, gfs (S) Tj = 25 C 175 C VDS = 25 V 0 1 02 03 04 05 06 07 08 0 0.01 0.02 0.03 0.04 0.05 0.06 PHP45N03LT ID, Drain current (Amps) Drain-Source on resistance, RDS(on) (Ohms) VGS = 15 V 10 V 3 V 3.5 V 4 V 4.5 V 5 V Tj = 25 C -100 0 100 2000 0.5 1.5 2 30V TrenchMOS Tj / C a 15050-50 0123456 PHP45N03LT Gate-source voltage, VGS (V) Drain current, ID (A) Tj = 25 C175 C VDS = 25 V BUK959-60 -100 -50 0 50 100 150 2000 0.5 1.5 2.5 Tj / C VGS(TO) / V max. typ. min. November 1998 4 Rev 1.400

Philips Semiconductors Product specification TrenchMOS transistor PHP42N03LT, PHB42N03LT Logic level FET Fig.11. Sub-threshold drain current. ID = f(VGS); VDS = VGS Fig.12. Typical capacitances, Ciss, Coss, Crss. C = f(VDS ); VGS = 0 V; f = 1 MHz Fig.13. Typical turn-on gate-charge characteristics. VGS = f(QG ) Fig.14. Typical reverse diode current. IF = f(VSDS ) 0 0.5 1 1.5 2 2.5 31E-05 1E-05 1E-04 1E-03 1E-02 1E-01 Sub-Threshold Conduction 2% typ 98% 0 1 02 03 04 05 0 PHP50N03LT Qg, Gate charge (nC) VGS, Gate-Source voltage (Volts) VDD=24V ID=20A Tj = 25C 0.1 1 10 100100 1000 10000 9528-30 VDS / V C / pF Ciss Coss Crss 0 0.5 1 1.5 20 9528-30 VSDS / V IF / A Tj / C = 175 25 November 1998 5 Rev 1.400

Philips Semiconductors Product specification TrenchMOS transistor PHP42N03LT, PHB42N03LT Logic level FET MECHANICAL DATA Dimensions in mm Net Mass: 2 g Fig.15. SOT78 (TO220AB); pin 2 connected to mounting base. Notes 1. Observe the general handling precautions for electrostatic-discharge sensitive devices (ESDs) to prevent damage to MOS gate oxide. 2. Refer to mounting instructions for SOT78 (TO220) envelopes. 3. Epoxy meets UL94 V0 at 1/8". 10,3 max 3,7 2,8 3,03,0 max not tinned 1,3 max (2x) 123 2,4 0,6 4,5 max 5,9 min 15,8 max 1,3 2,54 2,54 0,9 max (3x) 13,5 min November 1998 6 Rev 1.400

Philips Semiconductors Product specification TrenchMOS transistor PHP42N03LT, PHB42N03LT Logic level FET MECHANICAL DATA Dimensions in mm Net Mass: 1.4 g Fig.16. SOT404 : centre pin connected to mounting base. MOUNTING INSTRUCTIONS Dimensions in mm Fig.17. SOT404 : soldering pattern for surface mounting. Notes 1. Observe the general handling precautions for electrostatic-discharge sensitive devices (ESDs) to prevent damage to MOS gate oxide. 2. Epoxy meets UL94 V0 at 1/8". 11 max 4.5 max 1.4 max 10.3 max 0.5 15.4 2.5 0.85 max (x2) 2.54 (x2) 17.5 11.5 9.0 5.08 3.8 2.0 November 1998 7 Rev 1.400

Philips Semiconductors Product specification TrenchMOS transistor PHP42N03LT, PHB42N03LT Logic level FET DEFINITIONS Data sheet status Objective specification This data sheet contains target or goal specifications for product development. Preliminary specification This data sheet contains preliminary data; supplementary data may be published later. Product specification This data sheet contains final product specifications. Limiting values Limiting values are given in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of this specification is not implied. Exposure to limiting values for extended periods may affect device reliability.

Application information

Where application information is given, it is advisory and does not form part of the specification.  Philips Electronics N.V. 1998 All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, it is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent or other industrial or intellectual property rights. LIFE SUPPORT APPLICATIONS These products are not designed for use in life support appliances, devices or systems where malfunction of these products can be reasonably expected to result in personal injury. Philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such improper use or sale. November 1998 8 Rev 1.400