PHP21N06LT NEXPERIA | Alldatasheet

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Philips Semiconductors Product specification N-channel TrenchMOS transistor PHP21N06LT, PHB21N06LT Logic level FET PHD21N06LT FEATURES SYMBOL QUICK REFERENCE DATA

  • ’Trench’ technology VDSS = 55 V
  • Low on-state resistance
  • Fast switching ID = 19 A
  • Logic level compatible R DS(ON) ≤ 75 mΩ (VGS = 5 V) R DS(ON) ≤ 70 mΩ (VGS = 10 V) GENERAL DESCRIPTION N-channel enhancement mode, logic level, field-effect power transistor in a plastic envelope using ’trench’ technology. Applications:-
  • d.c. to d.c. converters
  • switched mode power supplies The PHP21N06LT is supplied in the SOT78 (TO220AB) conventional leaded package. The PHB21N06LT is supplied in the SOT404 (D2PAK) surface mounting package. The PHD21N06LT is supplied in the SOT428 (DPAK) surface mounting package. PINNING SOT78 (TO220AB) SOT404 (D 2PAK) SOT428 (DPAK) PIN DESCRIPTION 1 gate 2 drain 1 3 source tab drain LIMITING VALUES Limiting values in accordance with the Absolute Maximum System (IEC 134) SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT VDSS Drain-source voltage T j = 25 ˚C to 175˚C - 55 V VDGR Drain-gate voltage T j = 25 ˚C to 175˚C; RGS = 20 kΩ -5 5 V VGS Gate-source voltage - ± 15 V VGSM Pulsed gate-source voltage Tj ≤ 150˚C - ± 20 V ID Continuous drain current Tmb = 25 ˚C - 19 A Tmb = 100 ˚C - 13 A IDM Pulsed drain current T mb = 25 ˚C - 76 A PD Total power dissipation T mb = 25 ˚C - 56 W Tj, Tstg Operating junction and - 55 175 ˚C storage temperature d g s 12 3 tab tab tab 1 It is not possible to make connection to pin:2 of the SOT404 or SOT428 packages. August 1999 1 Rev 1.500

Philips Semiconductors Product specification N-channel TrenchMOS transistor PHP21N06LT, PHB21N06LT Logic level FET PHD21N06LT AVALANCHE ENERGY LIMITING VALUES Limiting values in accordance with the Absolute Maximum System (IEC 134) SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT EAS Non-repetitive avalanche Unclamped inductive load, IAS = 9.7 A; - 34 mJ energy t p = 100 µs; Tj prior to avalanche = 25˚C; VDD ≤ 25 V; RGS = 50 Ω ; VGS = 5 V; refer to fig:15 IAS Peak non-repetitive - 19 A avalanche current THERMAL RESISTANCES SYMBOL PARAMETER CONDITIONS TYP. MAX. UNIT R th j-mb Thermal resistance junction - 2.7 K/W to mounting base R th j-a Thermal resistance junction SOT78 package, in free air 60 - K/W to ambient SOT428 and SOT404 package, pcb 50 - K/W mounted, minimum footprint

ELECTRICAL CHARACTERISTICS

Tj= 25˚C unless otherwise specified SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT V(BR)DSS Drain-source breakdown V GS = 0 V; ID = 0.25 mA; 55 - - V voltage T j = -55˚C 50 - - V VGS(TO) Gate threshold voltage V DS = VGS ; ID = 1 mA 1.0 1.5 2.0 V Tj = 175˚C 0.5 - - V R DS(ON) Drain-source on-state V GS = 10 V; ID = 10 A - 55 70 m Ω resistance V GS = 5 V; ID = 10 A - 60 75 m Ω Tj = 175˚C - - 158 m Ω gfs Forward transconductance VDS = 25 V; ID = 10 A 5 13 - S IGSS Gate source leakage current VGS = ±5 V; VDS = 0 V - 10 100 nA IDSS Zero gate voltage drain V DS = 55 V; VGS = 0 V; - 0.05 10 µA current T j = 175˚C - - 500 µA Q g(tot) Total gate charge I D = 20 A; VDD = 44 V; VGS = 5 V - 9.4 - nC Q gs Gate-source charge - 2.2 - nC Q gd Gate-drain (Miller) charge - 5.4 - nC td on Turn-on delay time V DD = 30 V; RD = 1.2 Ω ;- 7 1 5 n s tr Turn-on rise time R G = 10 Ω ; VGS = 5 V - 88 120 ns td off Turn-off delay time Resistive load - 25 40 ns tf Turn-off fall time - 25 45 ns Ld Internal drain inductance Measured from tab to centre of die - 3.5 - nH Ld Internal drain inductance Measured from drain lead to centre of die - 4.5 - nH (SOT78 package only) Ls Internal source inductance Measured from source lead to source - 7.5 - nH bond pad C iss Input capacitance V GS = 0 V; VDS = 25 V; f = 1 MHz - 466 650 pF C oss Output capacitance - 95 135 pF C rss Feedback capacitance - 71 85 pF August 1999 2 Rev 1.500

Philips Semiconductors Product specification N-channel TrenchMOS transistor PHP21N06LT, PHB21N06LT Logic level FET PHD21N06LT REVERSE DIODE LIMITING VALUES AND CHARACTERISTICS Tj = 25˚C unless otherwise specified SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT IS Continuous source current - - 19 A (body diode) ISM Pulsed source current (body - - 76 A diode) VSD Diode forward voltage I F = 20 A; VGS = 0 V - 1.2 1.5 V trr Reverse recovery time I F = 20 A; -dIF/dt = 100 A/µs; - 43 - ns Q rr Reverse recovery charge V GS = 0 V; VR = 30 V - 94 - nC Fig.1. Normalised power dissipation. PD% = 100⋅PD /PD 25 ˚C = f(Tmb ) Fig.2. Normalised continuous drain current. ID% = 100⋅ID /ID 25 ˚C = f(Tmb ); conditions: VGS ≥ 5 V Fig.3. Safe operating area. Tmb = 25 ˚C ID & IDM = f(VDS ); IDM single pulse; parameter tp Fig.4. Transient thermal impedance. Zth j-mb = f(t); parameter D = tp/T Normalised Power Derating, PD (%) 100 0 25 50 75 100 125 150 175 Mounting Base temperature, Tmb (C) 0.1 100 1 10 100 Drain-Source Voltage, VDS (V) Peak Pulsed Drain Current, IDM (A) D.C. 100 ms 10 ms RDS(on) = VDS/ ID 1 ms tp = 10 us 100 us Normalised Current Derating, ID (%) 100 0 25 50 75 100 125 150 175 Mounting Base temperature, Tmb (C) 0.01 0.1 1E-06 1E-05 1E-04 1E-03 1E-02 1E-01 1E+00 Pulse width, tp (s) Transient thermal impedance, Zth j-mb (K/W) single pulse D = 0.5 0.2 0.1 0.05 0.02 tp D = tp/TDP T August 1999 3 Rev 1.500

Philips Semiconductors Product specification N-channel TrenchMOS transistor PHP21N06LT, PHB21N06LT Logic level FET PHD21N06LT Fig.5. Typical output characteristics, Tj = 25 ˚C. ID = f(VDS ) Fig.6. Typical on-state resistance, Tj = 25 ˚C. R DS(ON) = f(ID ) Fig.7. Typical transfer characteristics. ID = f(VGS ) Fig.8. Typical transconductance, Tj = 25 ˚C. gfs = f(ID ) Fig.9. Normalised drain-source on-state resistance. R DS(ON) /RDS(ON)25 ˚C = f(Tj) Fig.10. Gate threshold voltage. VGS(TO) = f(Tj); conditions: ID = 1 mA; VDS = VGS Drain-Source Voltage, VDS (V) Drain Current, ID (A) 2.8 V Tj = 25 C VGS = 10V 3 V 3.2 V 3.4 V 2.4 V 5 V 2.6 V 0 2 4 6 8 10 12 14 16 18 20 Drain current, ID (A) Transconductance, gfs (S) Tj = 25 C 175 C VDS > ID X RDS(ON) 0.05 0.1 0.15 0.2 0.25 0.3 0 5 10 15 20 25 30 35 Drain Current, ID (A) Drain-Source On Resistance, RDS(on) (Ohms) VGS = 10V Tj = 25 C 3.2 V 5 V 3.4 V 3 V 2.8V2.6 V 2.4 V Normalised On-state Resistance 0.2 0.4 0.6 0.8 1.2 1.4 1.6 1.8 2.2 2.4 -60 -40 -20 0 20 40 60 80 100 120 140 160 180 Junction temperature, Tj (C) Gate-source voltage, VGS (V) Drain current, ID (A) VDS > ID X RDS(ON) Tj = 25 C 175 C Threshold Voltage, VGS(TO) (V) 0.25 0.5 0.75 1.25 1.5 1.75 2.25 -60 -40 -20 0 20 40 60 80 100 120 140 160 180 Junction Temperature, Tj (C) typical maximum minimum August 1999 4 Rev 1.500

Philips Semiconductors Product specification N-channel TrenchMOS transistor PHP21N06LT, PHB21N06LT Logic level FET PHD21N06LT Fig.11. Sub-threshold drain current. ID = f(VGS); conditions: Tj = 25 ˚C; VDS = VGS Fig.12. Typical capacitances, Ciss, Coss, Crss. C = f(VDS ); conditions: VGS = 0 V; f = 1 MHz Fig.13. Typical turn-on gate-charge characteristics. VGS = f(QG ) Fig.14. Typical reverse diode current. IF = f(VSDS ); conditions: VGS = 0 V; parameter Tj Fig.15. Maximum permissible non-repetitive avalanche current (IAS ) versus avalanche time (tAV ); unclamped inductive load Drain current, ID (A) 1.0E-06 1.0E-05 1.0E-04 1.0E-03 1.0E-02 1.0E-01 0 0.5 1 1.5 2 2.5 3 Gate-source voltage, VGS (V) minimum typical maximum Source-Drain Voltage, VSDS (V) Source-Drain Diode Current, IF (A) Tj = 25 C 175 C VGS = 0 V 100 1000 10000 0.1 1 10 100 Drain-Source Voltage, VDS (V) Capacitances, Ciss, Coss, Crss (pF) Ciss Coss Crss 0.1 100 0.001 0.01 0.1 1 10 Avalanche time, tAV (ms) Maximum Avalanche Current, IAS (A) Tj prior to avalanche = 150 C 25 C 02468 1 0 1 2 1 4 1 6 1 8 2 0 Gate charge, QG (nC) Gate-source voltage, VGS (V) ID = 20A Tj = 25 C VDD = 11 V VDD = 44 V August 1999 5 Rev 1.500

Philips Semiconductors Product specification N-channel TrenchMOS transistor PHP21N06LT, PHB21N06LT Logic level FET PHD21N06LT MECHANICAL DATA Fig.16. SOT78 (TO220AB); pin 2 connected to mounting base (Net mass:2g) Notes 1. This product is supplied in anti-static packaging. The gate-source input must be protected against static discharge during transport or handling. 2. Refer to mounting instructions for SOT78 (TO220AB) package. 3. Epoxy meets UL94 V0 at 1/8". REFERENCESOUTLINE VERSION EUROPEAN PROJECTION ISSUE DATE IEC JEDEC EIAJ SOT78 TO-220 D D 1 q P L 123 (1) e e b 0 5 10 mm scale Plastic single-ended package; heatsink mounted; 1 mounting hole; 3-lead TO-220 SOT78 DIMENSIONS (mm are the original dimensions) AE c Note 1. Terminals in this zone are not tinned. Q UNIT A 1 b1 D 1 e P mm 2.54 qQA b Dc L2 (1) max. 3.0 3.8 3.6 15.0 13.5 3.30 2.79 3.0 2.7 2.6 2.2 0.7 0.4 15.8 15.2 0.9 0.7 1.3 1.0 4.5 4.1 1.39 1.27 6.4 5.9 10.3 9.7 L1E L 97-06-11 August 1999 6 Rev 1.500

Philips Semiconductors Product specification N-channel TrenchMOS transistor PHP21N06LT, PHB21N06LT Logic level FET PHD21N06LT MECHANICAL DATA Fig.17. SOT404 surface mounting package. Centre pin connected to mounting base. Notes 1. This product is supplied in anti-static packaging. The gate-source input must be protected against static discharge during transport or handling. 2. Refer to SMD Footprint Design and Soldering Guidelines, Data Handbook SC18. 3. Epoxy meets UL94 V0 at 1/8". UNIT A REFERENCESOUTLINE VERSION EUROPEAN PROJECTION ISSUE DATE IEC JEDEC EIAJ mm A 1 D 1 D max. E eL p H D Qc 2.54 2.60 2.20 15.40 14.80 2.90 2.1011 1.60 1.20 10.30 9.70 4.50 4.10 1.40 1.27 0.85 0.60 0.64 0.46 b DIMENSIONS (mm are the original dimensions) SOT404 0 2.5 5 mm scale Plastic single-ended surface mounted package (Philips version of D2-PAK); 3 leads (one lead cropped) SOT404 e e E b D 1 H D D Q Lp c A mounting base 98-12-14 99-06-25 August 1999 7 Rev 1.500

Philips Semiconductors Product specification N-channel TrenchMOS transistor PHP21N06LT, PHB21N06LT Logic level FET PHD21N06LT MOUNTING INSTRUCTIONS Dimensions in mm Fig.18. SOT404 : soldering pattern for surface mounting. 17.5 11.5 9.0 5.08 3.8 2.0 August 1999 8 Rev 1.500

Philips Semiconductors Product specification N-channel TrenchMOS transistor PHP21N06LT, PHB21N06LT Logic level FET PHD21N06LT MECHANICAL DATA Fig.19. SOT428 surface mounting package. Centre pin connected to mounting base. Notes 1. This product is supplied in anti-static packaging. The gate-source input must be protected against static discharge during transport or handling. 2. Refer to SMD Footprint Design and Soldering Guidelines, Data Handbook SC18. 3. Epoxy meets UL94 V0 at 1/8". MOUNTING INSTRUCTIONS REFERENCESOUTLINE VERSION EUROPEAN PROJECTION ISSUE DATE IEC JEDEC EIAJ SOT428 98-04-07 0 10 20 mm scale Plastic single-ended surface mounted package (Philips version of D-PAK); 3 leads (one lead cropped) SOT428 E b2 D 1 wA Mbcb1 L1L D H E Note 1. Measured from heatsink back to lead. e A A2 A y seating plane mounting base A 1(1) D max.b D 1 max. E max. H E max. w y max.A 2 b2 max. c min. ee 1 min. L2LA max.UNIT DIMENSIONS (mm are the original dimensions) 0.2 0.2mm 2.38 2.22 0.65 0.45 0.89 0.71 0.89 0.71 1.1 0.9 5.36 5.26 0.4 0.2 6.22 5.98 4.81 4.45 2.285 4.57 10.4 9.6 0.5 0.7 0.5 6.73 6.47 4.0 2.95 2.55 August 1999 9 Rev 1.500

Philips Semiconductors Product specification N-channel TrenchMOS transistor PHP21N06LT, PHB21N06LT Logic level FET PHD21N06LT Dimensions in mm Fig.20. SOT428 : soldering pattern for surface mounting. 7.0 7.0 2.15 2.5 4.57 1.5 August 1999 10 Rev 1.500

Philips Semiconductors Product specification N-channel TrenchMOS transistor PHP21N06LT, PHB21N06LT Logic level FET PHD21N06LT DEFINITIONS Data sheet status Objective specification This data sheet contains target or goal specifications for product development. Preliminary specification This data sheet contains preliminary data; supplementary data may be published later. Product specification This data sheet contains final product specifications. Limiting values Limiting values are given in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of this specification is not implied. Exposure to limiting values for extended periods may affect device reliability.

Application information

Where application information is given, it is advisory and does not form part of the specification.  Philips Electronics N.V. 1999 All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, it is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent or other industrial or intellectual property rights. LIFE SUPPORT APPLICATIONS These products are not designed for use in life support appliances, devices or systems where malfunction of these products can be reasonably expected to result in personal injury. Philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such improper use or sale. August 1999 11 Rev 1.500