PHP14NQ20T PHILIPS | Alldatasheet
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Philips Semiconductors Product specification TrenchMOS transistor PHP14NQ20T, PHB14NQ20T FEATURES SYMBOL QUICK REFERENCE DATA
- ’Trench’ technology
- Low on-state resistance VDSS = 200 V
- Fast switching
- High thermal cycling performance ID = 14 A
- Low thermal resistance R DS(ON) ≤ 230 mΩ GENERAL DESCRIPTION N-channel enhancement mode field-effect power transistor in a plastic envelope using ’trench’ technology. The device has very low on-state resistance. It is intended for use in dc to dc converters and general purpose switching applications. The PHP14NQ20T is supplied in the SOT78 (TO220AB) conventional leaded package. The PHB14NQ20T is supplied in the SOT404 (D2PAK) surface mounting package. PINNING SOT78 (TO220AB) SOT404 (D 2PAK) PIN DESCRIPTION 1 gate 2 drain 1 3 source tab drain LIMITING VALUES Limiting values in accordance with the Absolute Maximum System (IEC 134) SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT VDSS Drain-source voltage T j = 25 ˚C to 175˚C - 200 V VDGR Drain-gate voltage T j = 25 ˚C to 175˚C; RGS = 20 kΩ - 200 V VGS Gate-source voltage - ± 20 V ID Continuous drain current Tmb = 25 ˚C; VGS = 10 V - 14 A Tmb = 100 ˚C; VGS = 10 V - 10 A IDM Pulsed drain current T mb = 25 ˚C - 56 A PD Total power dissipation T mb = 25 ˚C - 125 W Tj, Tstg Operating junction and - 55 175 ˚C storage temperature d g s tab 12 3 tab
1 It is not possible to make connection to pin:2 of the SOT404 package
October 1999 1 Rev 1.000
Philips Semiconductors Product specification TrenchMOS transistor PHP14NQ20T, PHB14NQ20T AVALANCHE ENERGY LIMITING VALUES Limiting values in accordance with the Absolute Maximum System (IEC 134) SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT EAS Non-repetitive avalanche Unclamped inductive load, IAS = 14 A; - 70 mJ energy t p = 20 µs; Tj prior to avalanche = 25˚C; VDD ≤ 25 V; RGS = 50 Ω ; VGS = 10 V IAS Peak non-repetitive - 14 A avalanche current THERMAL RESISTANCES SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT R th j-mb Thermal resistance junction - - 1.2 K/W to mounting base R th j-a Thermal resistance junction SOT78 package, in free air - 60 - K/W to ambient SOT404 package, pcb mounted, minimum - 50 - K/W footprint
ELECTRICAL CHARACTERISTICS
Tj= 25˚C unless otherwise specified SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT V(BR)DSS Drain-source breakdown V GS = 0 V; ID = 0.25 mA; 200 - - V voltage T j = -55˚C 178 - - V VGS(TO) Gate threshold voltage V DS = VGS ; ID = 1 mA 2 3 4 V Tj = 175˚C 1 - - V Tj = -55˚C - - 6 V R DS(ON) Drain-source on-state V GS = 10 V; ID = 7 A - 150 230 m Ω resistance V GS = 10 V; ID = 7 A; Tj = 175˚C - - 633 m Ω gfs Forward transconductance VDS = 25 V; ID = 7 A 6 12.1 - S IGSS Gate source leakage current VGS = ± 10 V; VDS = 0 V - 10 100 nA IDSS Zero gate voltage drain V DS = 200 V; VGS = 0 V; - 0.05 10 µA current T j = 175˚C - - 500 µA Q g(tot) Total gate charge I D = 14 A; VDD = 160 V; VGS = 10 V - 38 - nC Q gs Gate-source charge - 4 - nC Q gd Gate-drain (Miller) charge - 13.3 - nC td on Turn-on delay time V DD = 30 V; ID = 3 A; - 25 - ns tr Turn-on rise time V GS = 10 V; RGS = 50 Ω -4 0-n s td off Turn-off delay time R gen = 50 Ω -8 3-n s tf Turn-off fall time - 31 - ns Ld Internal drain inductance Measured tab to centre of die - 3.5 - nH Ld Internal drain inductance Measured from drain lead to centre of die - 4.5 - nH (SOT78 package only) Ls Internal source inductance Measured from source lead to source - 7.5 - nH bond pad C iss Input capacitance V GS = 0 V; VDS = 25 V; f = 1 MHz - 1500 - pF C oss Output capacitance - 128 - pF C rss Feedback capacitance - 60 - pF October 1999 2 Rev 1.000
Philips Semiconductors Product specification TrenchMOS transistor PHP14NQ20T, PHB14NQ20T REVERSE DIODE LIMITING VALUES AND CHARACTERISTICS Tj = 25˚C unless otherwise specified SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT IS Continuous source current - - 14 A (body diode) ISM Pulsed source current (body - - 56 A diode) VSD Diode forward voltage I F = 14 A; VGS = 0 V - 1.0 1.5 V trr Reverse recovery time I F = 14 A; -dIF/dt = 100 A/µs; - 135 - ns Q rr Reverse recovery charge V GS = 0 V; VR = 30 V - 690 - nC October 1999 3 Rev 1.000
Philips Semiconductors Product specification TrenchMOS transistor PHP14NQ20T, PHB14NQ20T Fig.1. Normalised power dissipation. PD% = 100⋅PD /PD 25 ˚C = f(Tmb ) Fig.2. Normalised continuous drain current. ID% = 100⋅ID /ID 25 ˚C = f(Tmb ); conditions: VGS ≥ 10 V Fig.3. Safe operating area. Tmb = 25 ˚C ID & IDM = f(VDS ); IDM single pulse; parameter tp Fig.4. Transient thermal impedance. Zth j-mb = f(t); parameter D = tp/T Fig.5. Typical output characteristics, Tj = 25 ˚C. ID = f(VDS ); parameter VGS Fig.6. Typical on-state resistance, Tj = 25 ˚C. R DS(ON) = f(ID ); parameter VGS 0 20 40 60 80 100 120 140 160 180 Tmb / C PD% Normalised Power Derating120 110 100 0.01 0.1 1E-06 1E-05 1E-04 1E-03 1E-02 1E-01 1E+00 1E+01 Pulse width, tp (s) Transient thermal impedance, Zth j-a (K/W) single pulse D = 0.5 0.2 0.1 0.05 0.02 0 20 40 60 80 100 120 140 160 180 Tmb / C ID% Normalised Current Derating 120 110 100 0123456789 1 0 Drain-Source Voltage, VDS (V) Drain Current, ID (A) VGS=4.5 5 V 5.5 6 V 10V 6.5V 15V 0.1 100 1000 1 10 100 1000 Drain-Source Voltage, VDS (V) Peak Pulsed Drain Current, IDM (A) D.C. 100 ms 10 ms RDS(on) = VDS/ ID 1 ms tp = 1 us 100us 10us 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 01 0 2 0 Drain Current, ID (A) D rain-Source O n R esistance, RDS( on) (Ohms ) VGS =20 V 5.5V 6.5V 6V 4.5V 10V October 1999 4 Rev 1.000
Philips Semiconductors Product specification TrenchMOS transistor PHP14NQ20T, PHB14NQ20T Fig.7. Typical transfer characteristics. ID = f(VGS ) ; conditions: VDS = 25 V; parameter Tj Fig.8. Typical transconductance, Tj = 25 ˚C. gfs = f(ID ); conditions: VDS = 25 V Fig.9. Normalised drain-source on-state resistance. a = RDS(ON) /RDS(ON)25 ˚C = f(Tj); ID = 7 A; VGS = 10 V Fig.10. Gate threshold voltage. VGS(TO) = f(Tj); conditions: ID = 1 mA; VDS = VGS Fig.11. Sub-threshold drain current. ID = f(VGS); conditions: Tj = 25 ˚C; VDS = VGS Fig.12. Typical capacitances, Ciss, Coss, Crss. C = f(VDS ); conditions: VGS = 0 V; f = 1 MHz 02468 1 0 Gate-source voltage, VGS (V) Drain current, ID (A) Tj = 25 C175 C BUK759-60 -100 -50 0 50 100 150 2000 Tj / C VGS(TO) / V max. typ. min. 0 4 8 12 16 20 24 28 ID / (A) Transconductance, gfs (S) 0123451E-06 1E-05 1E-04 1E-03 1E-02 1E-01 Sub-Threshold Conduction typ2% 98% 0.5 1.5 2.5 -100 -50 0 50 100 150 200 Tmb / degC a Rds(on) normalised to 25degC 100 1000 10000 0 1 02 03 04 0 Drain-Source Voltage, VDS (V) Capacitances, Ciss, Coss, Crss (pF) Ciss Coss Crss October 1999 5 Rev 1.000
Philips Semiconductors Product specification TrenchMOS transistor PHP14NQ20T, PHB14NQ20T Fig.13. Typical turn-on gate-charge characteristics. VGS = f(QG ); conditions: ID = 14 A; parameter VDS Fig.14. Typical reverse diode current. IF = f(VSDS ); conditions: VGS = 0 V; parameter Tj Fig.15. Maximum permissible non-repetitive avalanche current (IAS ) versus.avalanche time (tAV ); unclamped inductive load 0 1 02 03 04 0 Gate charge, QG (nC) Gate-source voltage, VGS (V) VDD = 160 V VDD = 40 V 0.1 100 0.001 0.01 0.1 1 10 Avalanche time, tAV (ms) Maximum Avalanche Current, IAS (A) Tj prior to avalanche = 150 C 25 C Source-Drain Voltage, VSDS (V) Source-Drain Diode Current, IF (A) Tj = 25 C 175 C VGS = 0 V October 1999 6 Rev 1.000
Philips Semiconductors Product specification TrenchMOS transistor PHP14NQ20T, PHB14NQ20T MECHANICAL DATA Fig.16. SOT78 (TO220AB); pin 2 connected to mounting base (Net mass:2g) Notes 1. This product is supplied in anti-static packaging. The gate-source input must be protected against static discharge during transport or handling. 2. Refer to mounting instructions for SOT78 (TO220AB) package. 3. Epoxy meets UL94 V0 at 1/8". REFERENCESOUTLINE VERSION EUROPEAN PROJECTION ISSUE DATE IEC JEDEC EIAJ SOT78 TO-220 D D 1 q P L 123 (1) e e b 0 5 10 mm scale Plastic single-ended package; heatsink mounted; 1 mounting hole; 3-lead TO-220 SOT78 DIMENSIONS (mm are the original dimensions) AE c Note 1. Terminals in this zone are not tinned. Q UNIT A 1 b1 D 1 e P mm 2.54 qQA b Dc L2 (1) max. 3.0 3.8 3.6 15.0 13.5 3.30 2.79 3.0 2.7 2.6 2.2 0.7 0.4 15.8 15.2 0.9 0.7 1.3 1.0 4.5 4.1 1.39 1.27 6.4 5.9 10.3 9.7 L1E L 97-06-11 October 1999 7 Rev 1.000
Philips Semiconductors Product specification TrenchMOS transistor PHP14NQ20T, PHB14NQ20T MECHANICAL DATA Fig.17. SOT404 surface mounting package. Centre pin connected to mounting base. Notes 1. This product is supplied in anti-static packaging. The gate-source input must be protected against static discharge during transport or handling. 2. Refer to SMD Footprint Design and Soldering Guidelines, Data Handbook SC18. 3. Epoxy meets UL94 V0 at 1/8". UNIT A REFERENCESOUTLINE VERSION EUROPEAN PROJECTION ISSUE DATE IEC JEDEC EIAJ mm A 1 D 1 D max. E eL p H D Qc 2.54 2.60 2.20 15.40 14.80 2.90 2.1011 1.60 1.20 10.30 9.70 4.50 4.10 1.40 1.27 0.85 0.60 0.64 0.46 b DIMENSIONS (mm are the original dimensions) SOT404 0 2.5 5 mm scale Plastic single-ended surface mounted package (Philips version of D2-PAK); 3 leads (one lead cropped) SOT404 e e E b D 1 H D D Q Lp c A mounting base 98-12-14 99-06-25 October 1999 8 Rev 1.000
Philips Semiconductors Product specification TrenchMOS transistor PHP14NQ20T, PHB14NQ20T MOUNTING INSTRUCTIONS Dimensions in mm Fig.18. SOT404 : soldering pattern for surface mounting. 17.5 11.5 9.0 5.08 3.8 2.0 October 1999 9 Rev 1.000
Philips Semiconductors Product specification TrenchMOS transistor PHP14NQ20T, PHB14NQ20T DEFINITIONS Data sheet status Objective specification This data sheet contains target or goal specifications for product development. Preliminary specification This data sheet contains preliminary data; supplementary data may be published later. Product specification This data sheet contains final product specifications. Limiting values Limiting values are given in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of this specification is not implied. Exposure to limiting values for extended periods may affect device reliability.
Application information
Where application information is given, it is advisory and does not form part of the specification. Philips Electronics N.V. 1999 All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, it is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent or other industrial or intellectual property rights. LIFE SUPPORT APPLICATIONS These products are not designed for use in life support appliances, devices or systems where malfunction of these products can be reasonably expected to result in personal injury. Philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such improper use or sale. October 1999 10 Rev 1.000