PHP130N03LT PHILIPS | Alldatasheet

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Philips Semiconductors Product specification TrenchMOS  transistor PHP130N03LT, PHB130N03LT Logic level FET FEATURES SYMBOL QUICK REFERENCE DATA

  • ’Trench’ technology VDSS = 30 V
  • Very low on-state resistance
  • Fast switching ID = 75 A
  • Stable off-state characteristics
  • High thermal cycling performance R DS(ON) ≤ 6 mΩ (VGS = 5 V)
  • Low thermal resistance R DS(ON) ≤ 5 mΩ (VGS = 10 V) GENERAL DESCRIPTION N-channel enhancement mode logic level field-effect power transistor in a plastic envelope using ’trench’ technology. The device has very low on-state resistance. It is intended for use in dc to dc converters and general purpose switching applications. The PHP130N03LT is supplied in the SOT78 (TO220AB) conventional leaded package. The PHB130N03LT is supplied in the SOT404 surface mounting package. PINNING SOT78 (TO220AB) SOT404 PIN DESCRIPTION 1 gate 2 drain 3 source tab drain LIMITING VALUES Limiting values in accordance with the Absolute Maximum System (IEC 134) SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT VDSS Drain-source voltage T j = 25 ˚C to 175˚C - 30 V VDGR Drain-gate voltage T j = 25 ˚C to 175˚C; RGS = 20 kΩ -3 0 V VGS Gate-source voltage - ± 13 V ID Continuous drain current Tmb = 25 ˚C; VGS = 5 V - 75 A Tmb = 100 ˚C; VGS = 5 V - 75 A IDM Pulsed drain current T mb = 25 ˚C - 240 A PD Total power dissipation T mb = 25 ˚C - 187 W Tj, Tstg Operating junction and - 55 175 ˚C storage temperature d g s tab 12 3 tab 1 It is not possible to make connection to pin 2 of the SOT404 package. January 1998 1 Rev 1.300

Philips Semiconductors Product specification TrenchMOS transistor PHP130N03LT, PHB130N03LT Logic level FET ESD LIMITING VALUE SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT VC Electrostatic discharge Human body model (100 pF, 1.5 kΩ )- 2 k V capacitor voltage, all pins THERMAL RESISTANCES SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT R th j-mb Thermal resistance junction - - 0.8 K/W to mounting base R th j-a Thermal resistance junction SOT78 package, in free air - 60 - K/W to ambient SOT404 package, pcb mounted, minimum - 50 - K/W footprint

ELECTRICAL CHARACTERISTICS

Tj= 25˚C unless otherwise specified SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT V(BR)DSS Drain-source breakdown V GS = 0 V; ID = 0.25 mA; 30 - - V voltage T j = -55˚C 27 - - V V(BR)GSS Gate-source breakdown I G = 1 mA 10 - - V voltage VGS(TO) Gate threshold voltage V DS = VGS ; ID = 1 mA 1 1.5 2 V Tj = 175˚C 0.5 - - V R DS(ON) Drain-source on-state V GS = 5 V; ID = 25 A - 5 6 m Ω resistance V GS = 10 V; ID = 25 A - 4.5 5 m Ω VGS = 5 V; ID = 25 A; Tj = 175˚C - - 11 m Ω gfs Forward transconductance VDS = 25 V; ID = 25 A 20 40 - S IGSS Gate-source leakage current VGS = ±5 V; VDS = 0 V; - 0.02 1 µA Tj = 175˚C - - 10 µA IDSS Zero gate voltage drain V DS = 30 V; VGS = 0 V; - 0.05 10 µA current T j = 175˚C - - 500 µA Q g(tot) Total gate charge I D = 75 A; VDD = 24 V; VGS = 5 V - 92 - nC Q gs Gate-source charge - 10 - nC Q gd Gate-drain (Miller) charge - 36 - nC td on Turn-on delay time V DD = 15 V; ID = 25 A; - 45 60 ns tr Turn-on rise time V GS = 5 V; RG = 5 Ω - 120 170 ns td off Turn-off delay time Resistive load - 225 300 ns tf Turn-off fall time - 100 135 ns Ld Internal drain inductance Measured tab to centre of die - 3.5 - nH Ld Internal drain inductance Measured from drain lead to centre of die - 4.5 - nH (SOT78 package only) Ls Internal source inductance Measured from source lead to source - 7.5 - nH bond pad C iss Input capacitance V GS = 0 V; VDS = 25 V; f = 1 MHz - 5000 - pF C oss Output capacitance - 1150 - pF C rss Feedback capacitance - 500 - pF January 1998 2 Rev 1.300

Philips Semiconductors Product specification TrenchMOS transistor PHP130N03LT, PHB130N03LT Logic level FET REVERSE DIODE LIMITING VALUES AND CHARACTERISTICS Tj = 25˚C unless otherwise specified SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT IS Continuous source current - - 75 A (body diode) ISM Pulsed source current (body - - 240 A diode) VSD Diode forward voltage I F = 25 A; VGS = 0 V - 0.85 1.2 V IF = 75 A; VGS = 0 V - 1.0 - trr Reverse recovery time I F = 75 A; -dIF/dt = 100 A/µs; - 100 - ns Q rr Reverse recovery charge V GS = -10 V; VR = 25 V - 0.6 - µC AVALANCHE LIMITING VALUE SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT W DSS Drain-source non-repetitive ID = 75 A; VDD ≤ 15 V; - 500 mJ unclamped inductive turn-off VGS = 5 V; RGS = 50 Ω ; Tmb = 25 ˚C energy Fig.1. Normalised power dissipation. PD% = 100⋅PD /PD 25 ˚C = f(Tmb ) Fig.2. Normalised continuous drain current. ID% = 100⋅ID /ID 25 ˚C = f(Tmb ); conditions: VGS ≥ 5 V 0 20 40 60 80 100 120 140 160 180 Tmb / C PD% Normalised Power Derating120 110 100 Tmb / C 0 20 40 60 80 100 120 140 160 1800 100 120 140 ID (A) Current Derating Limited by package January 1998 3 Rev 1.300

Philips Semiconductors Product specification TrenchMOS transistor PHP130N03LT, PHB130N03LT Logic level FET Fig.3. Safe operating area. Tmb = 25 ˚C ID & IDM = f(VDS ); IDM single pulse; parameter tp Fig.4. Transient thermal impedance. Zth j-mb = f(t); parameter D = tp/T Fig.5. Typical output characteristics, Tj = 25 ˚C. ID = f(VDS ); parameter VGS Fig.6. Typical on-state resistance, Tj = 25 ˚C. R DS(ON) = f(ID ); parameter VGS Fig.7. Typical transfer characteristics. ID = f(VGS ) ; conditions: VDS = 25 V; parameter Tj Fig.8. Typical transconductance, Tj = 25 ˚C. gfs = f(ID ); conditions: VDS = 25 V 1 10 1001 100 1000 7506-30 Drain-source voltage, VDS (V) Drain current, ID (A) RDS(ON) = VDS / ID tp = 10 us 100 us 10 ms 100 ms DC 1 ms 0 2 04 06 08 0 1 0 00 9506-30 ID / A RDS(ON) / mOhm 3.5 1E-07 1E-05 1E-03 1E-01 1E+01 t / s Zth / (K/W) 1E+00 1E-01 1E-02 1E-03 0.5 0.2 0.1 0.05

0.02 D = tp tp

T TP t D 0123450 100 9506-30 VGS / V ID / A Tj / C = 175 25 02468 1 00 100 BUK9506-30 VDS / V ID / A VGS / V = 2.2 2.4 2.6 2.8 3.56 0 2 04 06 08 0 1 0 00 100 9506-30 ID / A gfs / S Tj / C = 25 175 January 1998 4 Rev 1.300

Philips Semiconductors Product specification TrenchMOS transistor PHP130N03LT, PHB130N03LT Logic level FET Fig.9. Normalised drain-source on-state resistance. a = RDS(ON) /RDS(ON)25 ˚C = f(Tj); ID = 25 A; VGS = 5 V Fig.10. Gate threshold voltage. VGS(TO) = f(Tj); conditions: ID = 1 mA; VDS = VGS Fig.11. Sub-threshold drain current. ID = f(VGS); conditions: Tj = 25 ˚C; VDS = VGS Fig.12. Typical capacitances, Ciss, Coss, Crss. C = f(VDS ); conditions: VGS = 0 V; f = 1 MHz Fig.13. Typical turn-on gate-charge characteristics. VGS = f(QG ); conditions: ID = 75 A; parameter VDS Fig.14. Typical reverse diode current. IF = f(VSDS ); conditions: VGS = 0 V; parameter Tj -100 0 100 2000 0.5 1.5 2 30V TrenchMOS Tj / C a 15050-50 0.1 1 10 100100 1000 10000 9506-30 VDS / V C / pF Ciss Coss Crss BUK959-60 -100 -50 0 50 100 150 2000 0.5 1.5 2.5 Tj / C VGS(TO) / V max. typ. min. 0 2 04 06 08 0 1 0 00 9506-30 QG / nC VGS / V VDS / V = 6 24 0 0.5 1 1.5 2 2.5 31E-05 1E-05 1E-04 1E-03 1E-02 1E-01 Sub-Threshold Conduction 2% typ 98% 0 0.5 1 1.5 20 100 9506-30 VSDS / V IF / A Tj / C = 175 25 January 1998 5 Rev 1.300

Philips Semiconductors Product specification TrenchMOS transistor PHP130N03LT, PHB130N03LT Logic level FET Fig.15. Normalised avalanche energy rating. W DSS % = f(Tmb ); conditions: ID = 75 A Fig.16. Avalanche energy test circuit. 20 40 60 80 100 120 140 160 180 Tmb / C 120 110 100 WDSS% L T.U.T. VDD RGS R 01 VDS -ID/100 shunt VGS W DSS = 0.5⋅LID 2 ⋅BV DSS /(BV DSS − VDD ) January 1998 6 Rev 1.300