PHN210

PHN210 NEXPERIA | Alldatasheet

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Philips Semiconductors Product specification Dual N-channel enhancement mode PHN210 TrenchMOS TM transistor FEATURES SYMBOL QUICK REFERENCE DATA  Dual device VDS = 30 V  Low threshold voltage  Fast switching ID = 3.4 A  Logic level compatible  Surface mount package R DS(ON) ≤ 100 mΩ (VGS = 10 V) R DS(ON) ≤ 200 mΩ (VGS = 4.5 V) GENERAL DESCRIPTION PINNING SOT96-1 Dual N-channel enhancement PIN DESCRIPTION mode field-effect transistor in a plastic envelope using ’trench’ 1 source 1 technology. 2 gate 1 Applications:-  Motor and relay drivers 3 source 2  d.c. to d.c. converters  Logic level translator 4 gate 2 The PHN210 is supplied in the 5,6 drain 2 SOT96-1 (SO8) surface mounting package. 7,8 drain 1 LIMITING VALUES Limiting values in accordance with the Absolute Maximum System (IEC 134) SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT VDS Repetitive peak drain-source T j = 25 ˚C to 150˚C - 30 V voltage VDS Continuous drain-source voltage - 30 V VDGR Drain-gate voltage R GS = 20 kΩ -3 0V VGS Gate-source voltage - ± 20 V ID Drain current per MOSFET1 Ta = 25 ˚C - 3.4 A Ta = 70 ˚C - 2.8 A ID Drain current per MOSFET (both Ta = 25 ˚C - 2.4 A MOSFETs conducting)1 Ta = 70 ˚C - 1.9 A IDM Drain current per MOSFET (pulse Ta = 25 ˚C - 14 A peak value) Ptot Total power dissipation (either or Ta = 25 ˚C - 2 W both MOSFETs conducting)1 Ta = 70 ˚C - 1.3 W Tstg, Tj Storage & operating temperature - 65 150 ˚C g1s1 d1 d2 12 34 5678 pin 1 index

1 Surface mounted on FR4 board, t ≤ 10 sec

January 2002 1 Rev 1.100

Philips Semiconductors Product specification Dual N-channel enhancement mode PHN210 TrenchMOS TM transistor THERMAL RESISTANCES SYMBOL PARAMETER CONDITIONS TYP. MAX. UNIT R th j-a Thermal resistance junction Surface mounted, FR4 board, t ≤ 10 sec - 62.5 K/W to ambient R th j-a Thermal resistance junction Surface mounted, FR4 board 150 - K/W to ambient AVALANCHE ENERGY LIMITING VALUES Limiting values in accordance with the Absolute Maximum System (IEC 134) SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT EAS Non-repetitive avalanche Unclamped inductive load, IAS = 3.4 A; - 13 mJ energy (per MOSFET) t p = 0.2 ms; Tj prior to avalanche = 25˚C; VDD ≤ 15 V; RGS = 50 Ω ; VGS = 10 V IAS Non-repetitive avalanche - 3.4 A current (per MOSFET)

ELECTRICAL CHARACTERISTICS

Tj= 25˚C, per MOSFET unless otherwise specified SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT V(BR)DSS Drain-source breakdown V GS = 0 V; ID = 10 µA; 30 - - V voltage T j = -55˚C 27 - - V VGS(TO) Gate threshold voltage V DS = VGS ; ID = 1 mA 1 2 2.8 V Tj = 150˚C 0.4 - - V Tj = -55˚C - 3.2 V R DS(ON) Drain-source on-state V GS = 10 V; ID = 2.2 A - 80 100 m Ω resistance V GS = 4.5 V; ID = 1 A - 120 200 m Ω VGS = 10 V; ID = 2.2 A; Tj = 150˚C - - 170 m Ω gfs Forward transconductance VDS = 20 V; ID = 2.2 A 2 4.5 - S ID(ON) On-state drain current V GS = 10 V; VDS = 1 V; 3.5 - - A VGS = 4.5 V; VDS = 5 V 2 - - A IDSS Zero gate voltage drain V DS = 24 V; VGS = 0 V; - 10 100 nA current V DS = 24 V; VGS = 0 V; Tj = 150˚C - 0.6 10 µA IGSS Gate source leakage current VGS = ±20 V; VDS = 0 V - 10 100 nA Q g(tot) Total gate charge I D = 2.3 A; VDD = 15 V; VGS = 10 V - 6 - nC Q gs Gate-source charge - 0.7 - nC Q gd Gate-drain (Miller) charge - 0.7 - nC td on Turn-on delay time V DD = 20 V; RD = 18 Ω ;- 6 - n s tr Turn-on rise time V GS = 10 V; RG = 6 Ω -8- n s td off Turn-off delay time Resistive load - 21 - ns tf Turn-off fall time - 15 - ns Ld Internal drain inductance Measured from drain lead to centre of die - 2.5 - nH Ls Internal source inductance Measured from source lead to source - 5 - nH bond pad C iss Input capacitance V GS = 0 V; VDS = 20 V; f = 1 MHz - 250 - pF C oss Output capacitance - 88 - pF C rss Feedback capacitance - 54 - pF January 2002 2 Rev 1.100

Philips Semiconductors Product specification Dual N-channel enhancement mode PHN210 TrenchMOS TM transistor REVERSE DIODE LIMITING VALUES AND CHARACTERISTICS Tj = 25˚C, per MOSFET unless otherwise specified SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT IS Continuous source diode T a = 25 ˚C - - 2.2 A current (per MOSFET) ISM Pulsed source diode current - - 14 A (per MOSFET) VSD Diode forward voltage I F = 1.25 A; VGS = 0 V - 0.82 1.2 V trr Reverse recovery time I F = 1.25 A; -dIF/dt = 100 A/µs; - 69 - ns Q rr Reverse recovery charge V GS = 0 V; VR = 25 V - 55 - nC Fig.1. Normalised power dissipation. PD% = 100⋅PD /PD 25 ˚C = f(Ta) Fig.2. Normalised continuous drain current. ID% = 100⋅ID /ID 25 ˚C = f(Ta); conditions: VGS ≥ 10 V Fig.3. Safe operating area. Ta = 25 ˚C ID & IDM = f(VDS ); IDM single pulse; parameter tp Fig.4. Transient thermal impedance. Zth j-a = f(t); parameter D = tp/T 0 20 40 60 80 100 120 140 Tamb / C PD% Normalised Power Derating120 110 100 PHN210 0.01 0.1 100 0.1 1 10 100 Drain-Source Voltage, VDS (V) Peak Pulsed Drain Current, IDM (A) 10 s 100 ms 10 ms RDS(on) = VDS/ ID 1 ms tp = 10 us 100 us 0 20 40 60 80 100 120 140 Ambient temperature, Tamb (C) ID% Normalised Current Derating 120 110 100 PHN210 0.01 0.1 100 1E-06 1E-05 1E-04 1E-03 1E-02 1E-01 1E+00 1E+01 Pulse width, tp (s) Zth j-a (K/W) single pulse D = 0.5 0.2 0.1 0.05 0.02 tp D = tp/TDP T January 2002 3 Rev 1.100

Philips Semiconductors Product specification Dual N-channel enhancement mode PHN210 TrenchMOS TM transistor Fig.5. Typical output characteristics, Tj = 25 ˚C. ID = f(VDS ); parameter VGS Fig.6. Typical on-state resistance, Tj = 25 ˚C. R DS(ON) = f(ID ); parameter VGS Fig.7. Typical transfer characteristics. ID = f(VGS ); parameter Tj Fig.8. Typical transconductance, Tj = 25 ˚C. gfs = f(ID ) ; parameter Tj Fig.9. Normalised drain-source on-state resistance. a = RDS(ON) /RDS(ON)25 ˚C = f(Tj) Fig.10. Gate threshold voltage. VGS(TO) = f(Tj); conditions: ID = 1 mA; VDS = VGS Drain-Source Voltage, VDS (V) Drain Current, ID (A) 3.2 V 3.4 V 4 V Tj = 25 C VGS = 20 V 3.6 V 3.8 V 5V10 V 4.2 V 0123456789 1 0 Drain current, ID (A) Transconductance, gfs (S) Tj = 25 C 150 C 0.1 0.2 0.3 0.4 0.5 0123456789 1 0 Drain Current, ID (A) Drain-Source On Resistance, RDS(on) (Ohms) VGS =5 V 4.2 V 20V Tj = 25 C3.8V 4 V3.6 V 10V 3.2 V 3.4 V -50 0 50 100 1500 0.5 1.5

2 SOT223 30V Trench

a Normalised RDS(ON) = f(Tj) Gate-source voltage, VGS (V) Drain current, ID (A) VDS > ID X RDS(ON) Tj = 25 C 150 C -60 -40 -20 0 20 40 60 80 100 120 140 Tj / C VGS(TO) / V max. typ. min. January 2002 4 Rev 1.100

Philips Semiconductors Product specification Dual N-channel enhancement mode PHN210 TrenchMOS TM transistor Fig.11. Sub-threshold drain current. ID = f(VGS); conditions: Tj = 25 ˚C; VDS = VGS Fig.12. Typical capacitances, Ciss, Coss, Crss. C = f(VDS ); conditions: VGS = 0 V; f = 1 MHz Fig.13. Typical turn-on gate-charge characteristics. VGS = f(QG ); parameter VDS Fig.14. Typical reverse diode current. IF = f(VSDS ); conditions: VGS = 0 V; parameter Tj Fig.15. Maximum permissible non-repetitive avalanche current (IAS ) versus avalanche time (tp); unclamped inductive load 0123451E-06 1E-05 1E-04 1E-03 1E-02 1E-01 Sub-Threshold Conduction typmin max Drain-Source Voltage, VSDS (V) Source-Drain Diode Current, IF (A) Tj = 25 C 150 C VGS = 0 V 100 1000 0.1 1 10 100 Drain-Source Voltage, VDS (V) Capacitances, Ciss, Coss, Crss (pF) Ciss Coss Crss PHN210 0.1 1E-06 1E-05 1E-04 1E-03 1E-02 Avalanche time, tp (s) Non-repetitive Avalanche current, IAS (A) 25 C VDS ID tp Tj prior to avalanche =125 C 0123456789 1 0 Gate charge, QG (nC) Gate-source voltage, VGS (V) ID = 2.3A Tj = 25 C VDD = 15 V January 2002 5 Rev 1.100

Philips Semiconductors Product specification Dual N-channel enhancement mode PHN210 TrenchMOS TM transistor MECHANICAL DATA Fig.16. SOT96 surface mounting package. Notes 1. This product is supplied in anti-static packaging. The gate-source input must be protected against static discharge during transport or handling. 2. Refer to Integrated Circuit Packages, Data Handbook IC26. 3. Epoxy meets UL94 V0 at 1/8". UNIT A max. A 1 A 2 A 3 bp cD (1) E (2) (1)eH E LL p QZ ywv θ REFERENCESOUTLINE VERSION EUROPEAN PROJECTION ISSUE DATE IEC JEDEC EIAJ mm inches 1.75 0.25 0.10 1.45 1.25 0.25 0.49 0.36 0.25 0.19 5.0 4.8 4.0 3.8 1.27 6.2 5.8 1.05 0.7 0.6 0.7 0.3 8 o o 0.25 0.10.25 DIMENSIONS (inch dimensions are derived from the original mm dimensions) Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic or metal protrusions of 0.25 mm maximum per side are not included. 1.0 0.4 SOT96-1 X w M θ AA 1 A 2 bp D H E Lp Q detail X E Z e c L v M A (A )3 A pin 1 index y 076E03S MS-012AA 0.069 0.010 0.004 0.057 0.049 0.01 0.019 0.014 0.0100 0.0075 0.20 0.19 0.16 0.15 0.050 0.244 0.228 0.028 0.024 0.028 0.016 0 2.5 5 mm scale SO8: plastic small outline package; 8 leads; body width 3.9 mm SOT96-1 95-02-04 97-05-22 January 2002 6 Rev 1.100

Philips Semiconductors Product specification Dual N-channel enhancement mode PHN210 TrenchMOS TM transistor DEFINITIONS DATA SHEET STATUS DATA SHEET PRODUCT DEFINITIONS STATUS 2 STATUS 3 Objective data Development This data sheet contains data from the objective specification for product development. Philips Semiconductors reserves the right to change the specification in any manner without notice Preliminary data Qualification This data sheet contains data from the preliminary specification. Supplementary data will be published at a later date. Philips Semiconductors reserves the right to change the specification without notice, in order to improve the design and supply the best possible product Product data Production This data sheet contains data from the product specification. Philips Semiconductors reserves the right to make changes at any time in order to improve the design, manufacturing and supply. Changes will be communicated according to the Customer Product/Process Change Notification (CPCN) procedure SNW-SQ-650A Limiting values Limiting values are given in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of this specification is not implied. Exposure to limiting values for extended periods may affect device reliability.

Application information

Where application information is given, it is advisory and does not form part of the specification.  Philips Electronics N.V. 2002 All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, it is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent or other industrial or intellectual property rights. LIFE SUPPORT APPLICATIONS These products are not designed for use in life support appliances, devices or systems where malfunction of these products can be reasonably expected to result in personal injury. Philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such improper use or sale. 2 Please consult the most recently issued datasheet before initiating or completing a design. 3 The product status of the device(s) described in this datasheet may have changed since this datasheet was January 2002 7 Rev 1.100