PHKD3NQ10T

PHKD3NQ10T PHILIPS

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Technical content

Philips Semiconductors Product specification Dual N-channel TrenchMOSTM transistor PHKD3NQ10T FEATURES SYMBOL QUICK REFERENCE DATA

• Dual device
• Low on-state resistance VDS = 100 V
• Fast switching
• Low profile surface mount ID = 3 A package R DS(ON) ≤ 90 mΩ (VGS = 10 V) GENERAL DESCRIPTION PINNING SOT96-1 Dual N-channel enhancement PIN DESCRIPTION mode field-effect transistor in a plastic envelope using ’trench’ 1 source 1 technology. 2 gate 1 Applications:-
• Motor and relay drivers 3 source 2
• d.c. to d.c. converters 4 gate 2 The PHKD3NQ10T is supplied in the SOT96-1 (SO8) surface 5,6 drain 2 mounting package. 7,8 drain 1 LIMITING VALUES Limiting values in accordance with the Absolute Maximum System (IEC 134) SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT VDS Continuous drain-source voltage Tj = 25 ˚C to 150˚C - 100 V VDGR Drain-gate voltage T j = 25 ˚C to 150˚C; - 100 V R GS = 20 kΩ VGS Gate-source voltage - ± 20 V ID Drain current per MOSFET T a = 25 ˚C, t ≤ 10 s - 3 A Ta = 70 ˚C, t ≤ 10 s - 2.4 A ID Drain current per MOSFET (both Ta = 25 ˚C, t ≤ 10 s - 2.2 A MOSFETs conducting) T a = 70 ˚C, t ≤ 10 s - 1.7 A IDM Drain current (pulse peak value per Ta = 25 ˚C - 12 A MOSFET) Ptot Total power dissipation T a = 25 ˚C, t ≤ 10 s - 2 W Ta = 70 ˚C, t ≤ 10 s - 1.3 W Tstg, Tj Storage & operating temperature - 65 150 ˚C THERMAL RESISTANCES SYMBOL PARAMETER CONDITIONS TYP. MAX. UNIT R th j-a Thermal resistance junction Surface mounted on FR4 board, t ≤ 10 - 62.5 K/W to ambient sec; either or both MOSFETs conducting R th j-a Thermal resistance junction Surface mounted on FR4 board; either or 150 - K/W to ambient both MOSFETs conducting 12 34 5678 pin 1 index August 1999 1 Rev 1.000

Philips Semiconductors Product specification Dual N-channel TrenchMOSTM transistor PHKD3NQ10T

ELECTRICAL CHARACTERISTICS

Tj= 25˚C, per MOSFET unless otherwise specified SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT V(BR)DSS Drain-source breakdown V GS = 0 V; ID = 250 µA; 100 - - V voltage T j = -55˚C 89 - - V VGS(TO) Gate threshold voltage V DS = VGS ; ID = 1 mA 2 3 4 V Tj = 150˚C 1.1 - - V Tj = -55˚C - 6 V R DS(ON) Drain-source on-state V GS = 10 V; ID = 1.5 A - 70 90 m Ω resistance T j = 150˚C - - 216 m Ω IGSS Gate source leakage current VGS = ±20 V; VDS = 0 V - 10 100 nA IDSS Zero gate voltage drain V DS = 100 V; VGS = 0 V; - 0.05 10 µA current T j = 150˚C - - 100 µA Q g(tot) Total gate charge I D = 3 A; VDD = 80 V; VGS = 10 V - 21 - nC Q gs Gate-source charge - 2.5 - nC Q gd Gate-drain (Miller) charge - 8 - nC td on Turn-on delay time V DD = 50 V; RD = 15 Ω ;- 6 - n s tr Turn-on rise time V GS = 10 V; RG = 5.6 Ω -1 2-n s td off Turn-off delay time Resistive load - 20 - ns tf Turn-off fall time - 10 - ns Ld Internal drain inductance Measured from drain lead to centre of die - 2.5 - nH Ls Internal source inductance Measured from source lead to source - 5 - nH bond pad C iss Input capacitance V GS = 0 V; VDS = 20 V; f = 1 MHz - 633 - pF C oss Output capacitance - 103 - pF C rss Feedback capacitance - 61 - pF REVERSE DIODE LIMITING VALUES AND CHARACTERISTICS Tj = 25˚C, per MOSFET unless otherwise specified SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT IS Continuous source diode T a = 25 ˚C, t ≤ 10 s - - 2 A current ISM Pulsed source diode current - - 12 A VSD Diode forward voltage I F = 2 A; VGS = 0 V - 0.8 1.2 V trr Reverse recovery time I F = 2 A; -dIF/dt = 100 A/µs; - 55 - ns Q rr Reverse recovery charge V GS = 0 V; VR = 25 V - 135 - nC August 1999 2 Rev 1.000

Philips Semiconductors Product specification Dual N-channel TrenchMOSTM transistor PHKD3NQ10T Fig.1. Normalised power dissipation. PD% = 100⋅PD /PD 25 ˚C = f(Ta) Fig.2. Normalised continuous drain current. ID% = 100⋅ID /ID 25 ˚C = f(Ta); VGS ≥ 10 V Fig.3. Safe operating area ID & IDM = f(VDS ); IDM single pulse; parameter tp Fig.4. Transient thermal impedance. Zth j-a = f(t); parameter D = tp/T Fig.5. Typical output characteristics, Tj = 25 ˚C. ID = f(VDS ) Fig.6. Typical on-state resistance, Tj = 25 ˚C. R DS(ON) = f(ID ) Normalised Power Derating, PD (%) 100 0 25 50 75 100 125 150 Ambient temperature, Ta (C) 0.01 0.1 100 1E-06 1E-05 1E-04 1E-03 1E-02 1E-01 1E+00 1E+01 Pulse width, tp (s) Transient thermal impedance, Zth j-a (K/W) single pulse D = 0.5 0.2 0.1 0.05 0.02 tp D = tp/TDP T Normalised Current Derating, ID (%) 100 0 25 50 75 100 125 150 Ambient temperature, Ta (C) Drain-Source Voltage, VDS (V) Drain Current, ID (A) 4.6 V Tj = 25 C VGS = 10V 4.8 V 5 V 5.2 V 8 V 4.4 V 5.4 V 6 V 0.01 0.1 100 0.1 1 10 100 1000 Drain-Source Voltage, VDS (V) Peak Pulsed Drain Current, IDM (A) D.C. 100 ms 10 ms RDS(on) = VDS/ ID 1 ms tp = 10 us 100 us 0.02 0.04 0.06 0.08 0.1 0.12 0.14 0.16 0.18 0.2 0123456 Drain Current, ID (A) Drain-Source On Resistance, RDS(on) (Ohms) VGS = 10V Tj = 25 C 8 V 5.2 V 5.4 V 5 V4.8V4.6V August 1999 3 Rev 1.000

Philips Semiconductors Product specification Dual N-channel TrenchMOSTM transistor PHKD3NQ10T Fig.7. Typical transfer characteristics. ID = f(VGS ) Fig.8. Typical transconductance, Tj = 25 ˚C. gfs = f(ID ) Fig.9. Normalised drain-source on-state resistance. R DS(ON) /RDS(ON)25 ˚C = f(Tj) Fig.10. Gate threshold voltage. VGS(TO) = f(Tj); conditions: ID = 1 mA; VDS = VGS Fig.11. Sub-threshold drain current. ID = f(VGS); conditions: Tj = 25 ˚C; VDS = VGS Fig.12. Typical capacitances, Ciss, Coss, Crss. C = f(VDS ); conditions: VGS = 0 V; f = 1 MHz 0123456 Gate-source voltage, VGS (V) Drain current, ID (A) VDS > ID X RDS(ON) Tj = 25 C 150 C Threshold Voltage, VGS(TO) (V) 0.5 1.5 2.5 3.5 4.5 -60 -40 -20 0 20 40 60 80 100 120 140 160 180 Junction Temperature, Tj (C) typical maximum minimum 0123456 Drain current, ID (A) Transconductance, gfs (S) Tj = 25 C 150 C VDS > ID X RDS(ON) Drain current, ID (A) 1.0E-06 1.0E-05 1.0E-04 1.0E-03 1.0E-02 1.0E-01 Gate-source voltage, VGS (V) minimum typical maximum Normalised On-state Resistance 0.5 0.7 0.9 1.1 1.3 1.5 1.7 1.9 2.1 2.3 2.5 2.7 2.9 -60 -40 -20 0 20 40 60 80 100 120 140 160 180 Junction temperature, Tj (C) 100 1000 10000 0.1 1 10 100 Drain-Source Voltage, VDS (V) Capacitances, Ciss, Coss, Crss (pF) Ciss Coss Crss August 1999 4 Rev 1.000

Philips Semiconductors Product specification Dual N-channel TrenchMOSTM transistor PHKD3NQ10T Fig.13. Typical turn-on gate-charge characteristics. VGS = f(QG ) Fig.14. Typical reverse diode current. IF = f(VSDS ); conditions: VGS = 0 V; parameter Tj 0 2 4 6 8 1 01 21 41 61 82 02 22 42 62 83 0 Gate charge, QG (nC) Gate-source voltage, VGS (V) ID = 3A Tj = 25 C VDD = 20 V VDD = 80 V Source-Drain Voltage, VSDS (V) Source-Drain Diode Current, IF (A) Tj = 25 C 150 C VGS = 0 V August 1999 5 Rev 1.000

Philips Semiconductors Product specification Dual N-channel TrenchMOSTM transistor PHKD3NQ10T MECHANICAL DATA Fig.15. SOT96 surface mounting package. Notes 1. This product is supplied in anti-static packaging. The gate-source input must be protected against static discharge during transport or handling. 2. Refer to Integrated Circuit Packages, Data Handbook IC26. 3. Epoxy meets UL94 V0 at 1/8". UNIT A max. A 1 A 2 A 3 bp cD (1) E (2) (1)eH E LL p QZ ywv θ REFERENCESOUTLINE VERSION EUROPEAN PROJECTION ISSUE DATE IEC JEDEC EIAJ mm inches 1.75 0.25 0.10 1.45 1.25 0.25 0.49 0.36 0.25 0.19 5.0 4.8 4.0 3.8 1.27 6.2 5.8 1.05 0.7 0.6 0.7 0.3 8 o o 0.25 0.10.25 DIMENSIONS (inch dimensions are derived from the original mm dimensions) Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic or metal protrusions of 0.25 mm maximum per side are not included. 1.0 0.4 SOT96-1 X w M θ AA 1 A 2 bp D H E Lp Q detail X E Z e c L v M A (A )3 A pin 1 index y 076E03S MS-012AA 0.069 0.010 0.004 0.057 0.049 0.01 0.019 0.014 0.0100 0.0075 0.20 0.19 0.16 0.15 0.050 0.244 0.228 0.028 0.024 0.028 0.016 0 2.5 5 mm scale SO8: plastic small outline package; 8 leads; body width 3.9 mm SOT96-1 95-02-04 97-05-22 August 1999 6 Rev 1.000

Philips Semiconductors Product specification Dual N-channel TrenchMOSTM transistor PHKD3NQ10T DEFINITIONS Data sheet status Objective specification This data sheet contains target or goal specifications for product development. Preliminary specification This data sheet contains preliminary data; supplementary data may be published later. Product specification This data sheet contains final product specifications. Limiting values Limiting values are given in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of this specification is not implied. Exposure to limiting values for extended periods may affect device reliability.

Application information

Where application information is given, it is advisory and does not form part of the specification.  Philips Electronics N.V. 1999 All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, it is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent or other industrial or intellectual property rights. LIFE SUPPORT APPLICATIONS These products are not designed for use in life support appliances, devices or systems where malfunction of these products can be reasonably expected to result in personal injury. Philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such improper use or sale. August 1999 7 Rev 1.000