PHD3N20L

PHD3N20L PHILIPS | Alldatasheet

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Philips Semiconductors Product specification PowerMOS transistor PHD3N20L Logic level FET GENERAL DESCRIPTION QUICK REFERENCE DATA N-channel enhancement mode logic SYMBOL PARAMETER MAX. UNIT level field-effect power transistor in a plastic envelope suitable for surface VDS Drain-source voltage 200 V mounting featuring high avalanche ID Drain current (DC) 3.5 A energy capability, stable blocking Ptot Total power dissipation 50 W voltage, fast switching and high R DS(ON) Drain-source on-state resistance 1.5 Ω thermal cycling performance with low thermal resistance. Intended for use in Switched Mode Power Supplies (SMPS), motor control circuits and general purpose switching applications. PINNING - SOT428 PIN CONFIGURATION SYMBOL PIN DESCRIPTION 1 gate 2 drain 3 source tab drain LIMITING VALUES Limiting values in accordance with the Absolute Maximum System (IEC 134) SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT I D Continuous drain current Tmb = 25 ˚C; VGS = 10 V - 3.5 A Tmb = 100 ˚C; VGS = 10 V - 2.5 A IDM Pulsed drain current T mb = 25 ˚C - 14 A PD Total dissipation T mb = 25 ˚C - 50 W ΔPD /ΔTmb Linear derating factor T mb > 25 ˚C - 0.33 W/K VGS Gate-source voltage - ± 15 V VGSM Non-repetitive gate-source tp ≤ 50 µs- ± 20 V voltage EAS Single pulse avalanche V DD ≤ 50 V; starting Tj = 25˚C; RGS = 50 Ω ; - 25 mJ energy V GS = 5 V IAS Peak avalanche current V DD ≤ 50 V; starting Tj = 25˚C; RGS = 50 Ω ; - 3.5 A VGS = 5 V Tj, Tstg Operating junction and - 55 175 ˚C storage temperature range THERMAL RESISTANCES SYMBOL PARAMETER CONDITIONS TYP. MAX. UNIT R th j-mb Thermal resistance junction to - 3 K/W mounting base R th j-a Thermal resistance junction to pcb mounted, minimum 50 - K/W ambient footprint tab d g s September 1997 1 Rev 1.000

Philips Semiconductors Product specification PowerMOS transistor PHD3N20L Logic level FET

ELECTRICAL CHARACTERISTICS

Tj = 25 ˚C unless otherwise specified SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT V (BR)DSS Drain-source breakdown V GS = 0 V; ID = 0.25 mA 200 - - V voltage ΔV(BR)DSS / Drain-source breakdown V DS = VGS ; ID = 0.25 mA - 0.25 - V/K ΔTj voltage temperature coefficient R DS(ON) Drain-source on resistance VGS = 5 V; ID = 2 A - 0.77 1.5 Ω VGS(TO) Gate threshold voltage V DS = VGS ; ID = 0.25 mA 1.0 1.5 2.0 V gfs Forward transconductance V DS = 50 V; ID = 2 A 0.8 3.0 - S IDSS Drain-source leakage current VDS = 200 V; VGS = 0 V - 0.1 25 µA VDS = 160 V; VGS = 0 V; Tj = 150 ˚C - 1 250 µA IGSS Gate-source leakage current VGS = ±15 V; VDS = 0 V - 10 100 nA Q g(tot) Total gate charge I D = 3.3 A; VDD = 160 V; VGS = 5 V - 7.5 9 nC Q gs Gate-source charge - 1 3 nC Q gd Gate-drain (Miller) charge - 4 6 nC td(on) Turn-on delay time V DD = 100 V; ID = 3.3 A; - 8 - ns tr Turn-on rise time R G = 24 Ω ; RD = 30 Ω -3 3-n s td(off) Turn-off delay time - 40 - ns tf Turn-off fall time - 36 - ns Ld Internal drain inductance Measured from tab to centre of die - 3.5 - nH Ls Internal source inductance Measured from source lead solder - 7.5 - nH point to source bond pad C iss Input capacitance V GS = 0 V; VDS = 25 V; f = 1 MHz - 270 - pF C oss Output capacitance - 48 - pF C rss Feedback capacitance - 17 - pF SOURCE-DRAIN DIODE RATINGS AND CHARACTERISTICS Tj = 25 ˚C unless otherwise specified SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT I S Continuous source current T mb = 25˚C - - 3.5 A (body diode) ISM Pulsed source current (body Tmb = 25˚C - - 14 A diode) VSD Diode forward voltage I S = 3.3 A; VGS = 0 V - - 1.5 V trr Reverse recovery time I S = 3.3 A; VGS = 0 V; - 90 - ns dI/dt = 100 A/µs Q rr Reverse recovery charge - 0.5 - µC September 1997 2 Rev 1.000

Philips Semiconductors Product specification PowerMOS transistor PHD3N20L Logic level FET Fig.1. Normalised power dissipation. PD% = 100⋅PD /PD 25 ˚C = f(Tmb ) Fig.2. Normalised continuous drain current. ID% = 100⋅ID /ID 25 ˚C = f(Tmb ); conditions: VGS ≥ 5 V Fig.3. Safe operating area. Tmb = 25 ˚C ID & IDM = f(VDS ); IDM single pulse; parameter tp Fig.4. Transient thermal impedance. Zth j-mb = f(t); parameter D = tp/T Fig.5. Typical output characteristics. ID = f(VDS ); parameter VGS Fig.6. Typical on-state resistance. R DS(ON) = f(ID ); parameter VGS 0 20 40 60 80 100 120 140 160 180 Tmb / C PD% Normalised Power Derating120 110 100 0.5 0.2 0.1 0.05 0.02 D = tp tp T TP t D 1us 10us 1ms 0.1s 10s tp, pulse widtht (s) Zth j-mb, Transient Thermal Impedance (K/W) 0.1 0.01 1s10ms100us 0 20 40 60 80 100 120 140 160 180 Tmb / C ID% Normalised Current Derating 120 110 100 0 5 10 15 20 25 30 PHP2N20L VDS, Drain-Source voltage (Volts) ID, Drain current (Amps) Tj = 25 C VGS = 2.5 V 3 V 3.5 V 4 V

5 V 10 V

0.1

100 PHP2N20E

tp = 10 us DC RDS(ON) = VDS/ID VDS, Drain-source voltage (Volts) ID, Drain current (Amps) 012345678

4 PHP2N20L

ID, Drain current (Amps) RDS(on), Drain-Source on resistance (Ohms) VGS = 10 V Tj = 25 C 2.5 V 3 V 3.5 V 4 V 5 V September 1997 3 Rev 1.000

Philips Semiconductors Product specification PowerMOS transistor PHD3N20L Logic level FET Fig.7. Typical transfer characteristics. ID = f(VGS ); parameter Tj Fig.8. Typical transconductance. gfs = f(ID ); parameter Tj Fig.9. Normalised drain-source on-state resistance. a = RDS(ON) /RDS(ON)25 ˚C = f(Tj); ID = 3.3 A; VGS = 5 V Fig.10. Gate threshold voltage. VGS(TO) = f(Tj); conditions: ID = 0.25 mA; VDS = VGS Fig.11. Sub-threshold drain current. ID = f(VGS); conditions: Tj = 25 ˚C; VDS = VGS Fig.12. Typical capacitances, Ciss, Coss, Crss. C = f(VDS ); conditions: VGS = 0 V; f = 1 MHz 0123456 PHP2N20L VGS, Gate-source voltage (Volts) ID, Drain current (Amps) VDS = 30 V Tj = 175 C Tj = 25 C -60 -20 20 60 100 140 180 Tj / C VGS(TO) / V max. typ. min. 02468 1 0 PHP2N20L ID, Drain current (Amps) gfs, Transconductance (S) VDD = 30 V Tj = 25 C Tj = 175 C VGS / V ID / A1E-01 1E-02 1E-03 1E-04 1E-05 1E-06 SUB-THRESHOLD CONDUCTION 2 % typ 98 % -60 -20 20 60 100 140 180 Tj / C Normalised RDS(ON) = f(Tj) 2.8 2.6 2.4 2.2 2.0 1.8 1.6 1.4 1.2 1.0 0.8 0.6 0.4 0.2 a 1 10 100 1000 100

1000 PHP2N20L

VDS, Drain-source voltage (Volts) Ciss, Coss, Crss, Junction capacitances (pF) Crss Coss Ciss September 1997 4 Rev 1.000

Philips Semiconductors Product specification PowerMOS transistor PHD3N20L Logic level FET Fig.13. Typical turn-on gate-charge characteristics. VGS = f(QG ); parameter VDS Fig.14. Typical switching times. td(on), tr, td(off), tf = f(RG ) Fig.15. Normalised drain-source breakdown voltage. V(BR)DSS /V(BR)DSS 25 ˚C = f(Tj) Fig.16. Source-Drain diode characteristic. IF = f(VSDS ); parameter Tj Fig.17. Normalised unclamped inductive energy. EAS % = f(Tj) Fig.18. Unclamped inductive test circuit. 0 5 10 15

10 PHP2N20L

Qg, Gate charge (nC) VGS, Gate-Source voltage (Volts) VDS = 40 V 100 V 160 V ID = 3.3 A Tj = 25 C 0 0.5 1 1.5 2

20 PHP2N20L

VSDS, Source-drain voltage (Volts) IF, Source-drain diode current (Amps) Tj = 25 CTj = 175 C VGS = 0 V 0 2 04 06 08 0 1 0 0 100 td(off)tf td(on) Tj = 25 C VDD = 100 V RD = 30 Ohms VGS = 5 V ID = 3.3 A RG, Gate resistance (Ohms) Switching times (ns) 20 40 60 80 100 120 140 160 180 120 110 100 Starting Tj ( C) EAS, Normalised unclamped inductive energy (%) -100 -50 0 50 100 150 0.85 0.9 0.95 1.05 1.1 1.15 Tj, Junction temperature (C) Normalised Drain-source breakdown voltage V(BR)DSS @ Tj V(BR)DSS @ 25 C L T.U.T. VDD RGS R 01 VDS -ID/100 shunt VGS EAS = 0.5⋅LID 2 ⋅V(BR )DSS /(V(BR )DSS − VDD ) September 1997 5 Rev 1.000

Philips Semiconductors Product specification PowerMOS transistor PHD3N20L Logic level FET MECHANICAL DATA Dimensions in mm : Net Mass: 1.4 g Fig.19. SOT428 : centre pin connected to mounting base. MOUNTING INSTRUCTIONS Dimensions in mm Fig.20. SOT428 : soldering pattern for surface mounting. Notes 1. Observe the general handling precautions for electrostatic-discharge sensitive devices (ESDs) to prevent damage to MOS gate oxide. 2. Epoxy meets UL94 V0 at 1/8". 6.22 max 2.38 max 0.93 max 6.73 max 0.3 10.4 max 0.5 0.8 max (x2) 2.285 (x2) 0.5 seating plane 1.1 0.5 min 5.4 4 min 4.6 tab 7.0 7.0 2.15 2.5 4.57 1.5 September 1997 6 Rev 1.000

Philips Semiconductors Product specification PowerMOS transistor PHD3N20L Logic level FET DEFINITIONS Data sheet status Objective specification This data sheet contains target or goal specifications for product development. Preliminary specification This data sheet contains preliminary data; supplementary data may be published later. Product specification This data sheet contains final product specifications. Limiting values Limiting values are given in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of this specification is not implied. Exposure to limiting values for extended periods may affect device reliability.

Application information

Where application information is given, it is advisory and does not form part of the specification.  Philips Electronics N.V. 1997 All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, it is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent or other industrial or intellectual property rights. LIFE SUPPORT APPLICATIONS These products are not designed for use in life support appliances, devices or systems where malfunction of these products can be reasonably expected to result in personal injury. Philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such improper use or sale. September 1997 7 Rev 1.000