PHB42N03LT PHILIPS | Alldatasheet

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Philips Semiconductors Product specification TrenchMOS  transistor PHB42N03LT Logic level FET FEATURES SYMBOL QUICK REFERENCE DATA

  • ’Trench’ technology VDSS = 30 V
  • Very low on-state resistance
  • Fast switching ID = 42 A
  • Stable off-state characteristics
  • High thermal cycling performance R DS(ON) ≤ 26 mΩ (VGS = 5 V)
  • Low thermal resistance
  • Surface mounting package R DS(ON) ≤ 23 mΩ (VGS = 10 V) GENERAL DESCRIPTION PINNING SOT404 N-channel enhancement mode PIN DESCRIPTION logic level field-effect power transistor in a plastic envelope 1 gate using ’trench’ technology. The device has very low on-state 2 drain (no connection resistance. It is intended for use in possible) dc to dc converters and general purpose switching applications. 3 source The PHB42N03LT is supplied in the tab drain SOT404 surface mounting package. LIMITING VALUES Limiting values in accordance with the Absolute Maximum System (IEC 134) SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT VDS Drain-source voltage - - 30 V VDGR Drain-gate voltage R GS = 20 kΩ -3 0V ±VGS Gate-source voltage - - 15 V ID Drain current (DC) T mb = 25 ˚C - 42 A ID Drain current (DC) T mb = 100 ˚C - 33 A IDM Drain current (pulse peak value) Tmb = 25 ˚C - 168 A Ptot Total power dissipation T mb = 25 ˚C - 86 W Tstg, Tj Storage & operating temperature - - 55 175 ˚C THERMAL RESISTANCES SYMBOL PARAMETER CONDITIONS TYP. MAX. UNIT R th j-mb Thermal resistance junction to - - 1.75 K/W mounting base R th j-a Thermal resistance junction to pcb mounted, minimum 50 - K/W ambient footprint d g s mb December 1997 1 Rev 1.300

Philips Semiconductors Product specification TrenchMOS transistor PHB42N03LT Logic level FET STATIC CHARACTERISTICS Tj= 25˚C unless otherwise specified SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT V(BR)DSS Drain-source breakdown V GS = 0 V; ID = 0.25 mA; 30 - - V voltage T j = -55˚C 27 - - V VGS(TO) Gate threshold voltage V DS = VGS ; ID = 1 mA 1 1.5 2 V Tj = 175˚C 0.5 - - V Tj = -55˚C - - 2.3 IDSS Zero gate voltage drain current VDS = 30 V; VGS = 0 V; - 0.05 10 µA Tj = 175˚C - - 500 µA IGSS Gate source leakage current VGS = ±5 V; VDS = 0 V - 10 100 nA R DS(ON) Drain-source on-state V GS = 5 V; ID = 25 A - 20 26 m Ω resistance V GS = 10 V; ID = 25 A - 16 23 m Ω VGS = 5 V; ID = 25 A; Tj = 175˚C - - 48 m Ω DYNAMIC CHARACTERISTICS Tj = 25˚C unless otherwise specified SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT gfs Forward transconductance V DS = 25 V; ID = 25 A 8 16 - S Q g(tot) Total gate charge I D = 40 A; VDD = 24 V; VGS = 5 V - 23 - nC Q gs Gate-source charge - 3 - nC Q gd Gate-drain (Miller) charge - 9 - nC C iss Input capacitance V GS = 0 V; VDS = 25 V; f = 1 MHz - 1050 - pF C oss Output capacitance - 270 - pF C rss Feedback capacitance - 140 - pF td on Turn-on delay time V DD = 15 V; ID = 25 A; - 30 45 ns tr Turn-on rise time V GS = 5 V; RG = 5 Ω - 80 130 ns td off Turn-off delay time Resistive load - 95 135 ns tf Turn-off fall time - 40 55 ns Ld Internal drain inductance Measured from tab to centre of die - 3.5 - nH Ld Internal drain inductance Measured from drain lead solder - 4.5 - nH point to centre of die Ls Internal source inductance Measured from source lead solder - 7.5 - nH point to source bond pad REVERSE DIODE LIMITING VALUES AND CHARACTERISTICS Tj = 25˚C unless otherwise specified SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT IDR Continuous reverse drain - - 42 A current IDRM Pulsed reverse drain current - - 168 A VSD Diode forward voltage I F = 25 A; VGS = 0 V - 0.95 1.2 V IF = 40 A; VGS = 0 V - 1.0 - trr Reverse recovery time I F = 40 A; -dIF/dt = 100 A/µs; - 52 - ns Q rr Reverse recovery charge V GS = -10 V; VR = 25 V - 0.08 - µC December 1997 2 Rev 1.300

Philips Semiconductors Product specification TrenchMOS transistor PHB42N03LT Logic level FET AVALANCHE LIMITING VALUE SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT W DSS Drain-source non-repetitive ID = 25 A; VDD ≤ 25 V; - - 60 mJ unclamped inductive turn-off VGS = 10 V; RGS = 50 Ω ; Tmb = 25 ˚C energy December 1997 3 Rev 1.300

Philips Semiconductors Product specification TrenchMOS transistor PHB42N03LT Logic level FET Fig.1. Normalised power dissipation. PD% = 100⋅PD /PD 25 ˚C = f(Tmb ) Fig.2. Normalised continuous drain current. ID% = 100⋅ID /ID 25 ˚C = f(Tmb ); conditions: VGS ≥ 5 V Fig.3. Safe operating area. Tmb = 25 ˚C ID & IDM = f(VDS ); IDM single pulse; parameter tp Fig.4. Transient thermal impedance. Zth j-mb = f(t); parameter D = tp/T Fig.5. Typical output characteristics, Tj = 25 ˚C. ID = f(VDS ); parameter VGS Fig.6. Typical on-state resistance, Tj = 25 ˚C. R DS(ON) = f(ID ); parameter VGS 0 20 40 60 80 100 120 140 160 180 Tmb / C PD% Normalised Power Derating120 110 100 1E-07 1E-05 1E-03 1E-01 1E+010.01 0.1 10 7528-30 t / s Zth j-mb / (K/W) D = tp tp T TP t D D = 0.02 0.05 0.1 0.2 0.5 0 20 40 60 80 100 120 140 160 180 Tmb / C ID% Normalised Current Derating 120 110 100 02468 1 00 9528-30 VDS / V ID / A 2.5 3.5 4.5510 VGS / V = 1 10 1001 100 1000 7528-30 VDS / V ID / A tp = 10 us 100 us 1 ms 10 ms RDS(ON) = VDS / ID DC 0 2 04 06 08 00 9528-30 ID / A RDS(ON) / mOhm VGS / V = 4.54 December 1997 4 Rev 1.300

Philips Semiconductors Product specification TrenchMOS transistor PHB42N03LT Logic level FET Fig.7. Typical transfer characteristics. ID = f(VGS ) ; conditions: VDS = 25 V; parameter Tj Fig.8. Typical transconductance, Tj = 25 ˚C. gfs = f(ID ); conditions: VDS = 25 V Fig.9. Normalised drain-source on-state resistance. a = RDS(ON) /RDS(ON)25 ˚C = f(Tj); ID = 25 A; VGS = 5 V Fig.10. Gate threshold voltage. VGS(TO) = f(Tj); conditions: ID = 1 mA; VDS = VGS Fig.11. Sub-threshold drain current. ID = f(VGS); conditions: Tj = 25 ˚C; VDS = VGS Fig.12. Typical capacitances, Ciss, Coss, Crss. C = f(VDS ); conditions: VGS = 0 V; f = 1 MHz 01234560 9528-30 VGS / V ID / A Tj / C = 25 175 BUK959-60 -100 -50 0 50 100 150 2000 0.5 1.5 2.5 Tj / C VGS(TO) / V max. typ. min. 0 1 02 03 04 05 06 00 9528-30 ID / A gfs / S Tj / C = 25 175 0 0.5 1 1.5 2 2.5 31E-05 1E-05 1E-04 1E-03 1E-02 1E-01 Sub-Threshold Conduction 2% typ 98% -100 0 100 2000 0.5 1.5 2 30V TrenchMOS Tj / C a 15050-50 0.1 1 10 100100 1000 10000 9528-30 VDS / V C / pF Ciss Coss Crss December 1997 5 Rev 1.300

Philips Semiconductors Product specification TrenchMOS transistor PHB42N03LT Logic level FET Fig.13. Typical turn-on gate-charge characteristics. VGS = f(QG ); conditions: ID = 40 A; parameter VDS Fig.14. Typical reverse diode current. IF = f(VSDS ); conditions: VGS = 0 V; parameter Tj Fig.15. Normalised avalanche energy rating. W DSS % = f(Tmb ); conditions: ID = 25 A Fig.16. Avalanche energy test circuit. Fig.17. Switching test circuit. 0 5 10 15 20 250 9528-30 QG / nC VGS / V VDS / V = 6 24 20 40 60 80 100 120 140 160 180 Tmb / C 120 110 100 WDSS% 0 0.5 1 1.5 20 9528-30 VSDS / V IF / A Tj / C = 175 25 L T.U.T. VDD RGS R 01 VDS -ID/100 shunt VGS W DSS = 0.5⋅LID 2 ⋅BV DSS /(BV DSS − VDD ) RD T.U.T. VDD RG VDS VGS December 1997 6 Rev 1.300

Philips Semiconductors Product specification TrenchMOS transistor PHB42N03LT Logic level FET MECHANICAL DATA Dimensions in mm Net Mass: 1.4 g Fig.18. SOT404 : centre pin connected to mounting base. MOUNTING INSTRUCTIONS Dimensions in mm Fig.19. SOT404 : soldering pattern for surface mounting. Notes 1. Observe the general handling precautions for electrostatic-discharge sensitive devices (ESDs) to prevent damage to MOS gate oxide. 2. Epoxy meets UL94 V0 at 1/8". 11 max 4.5 max 1.4 max 10.3 max 0.5 15.4 2.5 0.85 max (x2) 2.54 (x2) 17.5 11.5 9.0 5.08 3.8 2.0 December 1997 7 Rev 1.300

Philips Semiconductors Product specification TrenchMOS transistor PHB42N03LT Logic level FET DEFINITIONS Data sheet status Objective specification This data sheet contains target or goal specifications for product development. Preliminary specification This data sheet contains preliminary data; supplementary data may be published later. Product specification This data sheet contains final product specifications. Limiting values Limiting values are given in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of this specification is not implied. Exposure to limiting values for extended periods may affect device reliability.

Application information

Where application information is given, it is advisory and does not form part of the specification.  Philips Electronics N.V. 1997 All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, it is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent or other industrial or intellectual property rights. LIFE SUPPORT APPLICATIONS These products are not designed for use in life support appliances, devices or systems where malfunction of these products can be reasonably expected to result in personal injury. Philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such improper use or sale. December 1997 8 Rev 1.300