PHB36N06E

PHB36N06E PHILIPS | Alldatasheet

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Philips Semiconductors Product specification PowerMOS transistor PHB36N06E GENERAL DESCRIPTION QUICK REFERENCE DATA N-channel enhancement mode SYMBOL PARAMETER MAX. UNIT field-effect power transistor in a plastic envelope suitable for surface VDS Drain-source voltage 60 V mount applications. I D Drain current (DC) 41 A The device is intended for use in Ptot Total power dissipation 125 W automotive and general purpose T j Junction temperature 175 ˚C switching applications. R DS(ON) Drain-source on-state 38 m Ω resistance PINNING - SOT404 PIN CONFIGURATION SYMBOL PIN DESCRIPTION 1 gate 2 drain 3 source mb drain LIMITING VALUES Limiting values in accordance with the Absolute Maximum System (IEC 134) SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT V DS Drain-source voltage - - 60 V VDGR Drain-gate voltage R GS = 20 kΩ -6 0 V ±VGS Gate-source voltage - - 30 V ID Drain current (DC) T mb = 25 ˚C - 41 A ID Drain current (DC) T mb = 100 ˚C - 29 A IDM Drain current (pulse peak value) Tmb = 25 ˚C - 164 A Ptot Total power dissipation T mb = 25 ˚C - 125 W Tstg Storage temperature - - 55 175 ˚C Tj Junction temperature - - 175 ˚C THERMAL RESISTANCES SYMBOL PARAMETER CONDITIONS TYP. MAX. UNIT R th j-mb Thermal resistance junction to - - 1.2 K/W mounting base R th j-a Thermal resistance junction to minimum footprint, 50 - K/W ambient FR4 board (see Fig. 18). mb d g s August 1996 1 Rev 1.000

Philips Semiconductors Product specification PowerMOS transistor PHB36N06E STATIC CHARACTERISTICS Tmb = 25 ˚C unless otherwise specified SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT V (BR)DSS Drain-source breakdown V GS = 0 V; ID = 0.25 mA 60 - - V voltage VGS(TO) Gate threshold voltage V DS = VGS ; ID = 1 mA 2.1 3.0 4.0 V IDSS Zero gate voltage drain current VDS = 60 V; VGS = 0 V; Tj = 25 ˚C - 1 10 µA IDSS Zero gate voltage drain current VDS = 60 V; VGS = 0 V; Tj = 125 ˚C - 0.1 1.0 mA IGSS Gate source leakage current VGS = ±30 V; VDS = 0 V - 10 100 nA R DS(ON) Drain-source on-state V GS = 10 V; ID = 20 A - 30 38 m Ω resistance DYNAMIC CHARACTERISTICS Tmb = 25 ˚C unless otherwise specified SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT g fs Forward transconductance V DS = 25 V; ID = 20 A 7 14 - S C iss Input capacitance V GS = 0 V; VDS = 25 V; f = 1 MHz - 900 1600 pF C oss Output capacitance - 420 600 pF C rss Feedback capacitance - 160 275 pF td on Turn-on delay time V DD = 30 V; ID = 3 A; - 15 30 ns tr Turn-on rise time V GS = 10 V; RGS = 50 Ω ; - 55 90 ns td off Turn-off delay time R gen = 50 Ω - 75 125 ns tf Turn-off fall time - 60 100 ns Ld Internal drain inductance Measured from upper edge of drain - 2.5 - nH tab to centre of die Ls Internal source inductance Measured from source lead - 7.5 - nH soldering point to source bond pad REVERSE DIODE LIMITING VALUES AND CHARACTERISTICS Tmb = 25 ˚C unless otherwise specified SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT IDR Continuous reverse drain - - - 41 A current IDRM Pulsed reverse drain current - - - 164 A VSD Diode forward voltage I F = 41 A ; VGS = 0 V - 0.95 2.0 V trr Reverse recovery time I F = 41 A; -dIF/dt = 100 A/µs; - 60 - ns Q rr Reverse recovery charge V GS = 0 V; VR = 30 V - 0.30 - µC AVALANCHE LIMITING VALUE Tmb = 25 ˚C unless otherwise specified SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT W DSS Drain-source non-repetitive ID = 41 A ; VDD ≤ 25 V ; - - 100 mJ unclamped inductive turn-off VGS = 10 V ; RGS = 50 Ω energy August 1996 2 Rev 1.000

Philips Semiconductors Product specification PowerMOS transistor PHB36N06E Fig.1. Normalised power dissipation. PD% = 100⋅PD /PD 25 ˚C = f(Tmb ) Fig.2. Normalised continuous drain current. ID% = 100⋅ID /ID 25 ˚C = f(Tmb ); conditions: VGS ≥ 10 V Fig.3. Safe operating area. Tmb = 25 ˚C ID & IDM = f(VDS ); IDM single pulse; parameter tp Fig.4. Transient thermal impedance. Zth j-mb = f(t); parameter D = tp/T Fig.5. Typical output characteristics, Tj = 25 ˚C. ID = f(VDS ); parameter VGS Fig.6. Typical on-state resistance, Tj = 25 ˚C. R DS(ON) = f(ID ); parameter VGS 0 20 40 60 80 100 120 140 Tmb / C PD% Normalised Power Derating120 110 100 0 1E-07 1E-05 1E-03 1E-01 1E+01 0.001 0.01 0.1

10 BUK464-60H

Zth(j-mb) K/W D = tp tp T TP t D 0.2 0.1 0.05 0.02 0.5 D = 0 20 40 60 80 100 120 140 Tmb / C ID% Normalised Current Derating120 110 100 02468 1 00 101520 BUK474-60H VDS / V ID / A VGS / V = 9 VDS / V ID / A BUK464-60H 10 100 1000 100 1000 RDS(ON) = VDS/ID DC 10 us 100 us 1 ms 10 ms 100 ms tp = 0 1 02 03 04 05 06 07 08 00 0.05 0.1 0.15 0.2 BUK474-60H ID / A RDS(ON) / Ohm VGS / V = August 1996 3 Rev 1.000

Philips Semiconductors Product specification PowerMOS transistor PHB36N06E Fig.7. Typical transfer characteristics. ID = f(VGS ) ; conditions: VDS = 15 V; parameter Tj Fig.8. Typical transconductance, Tj = 25 ˚C. gfs = f(ID ); conditions: VDS = 15 V Fig.9. Normalised drain-source on-state resistance. a = RDS(ON) /RDS(ON)25 ˚C = f(Tj); ID = 20 A; VGS = 10 V Fig.10. Gate threshold voltage. VGS(TO) = f(Tj); conditions: ID = 1 mA; VDS = VGS Fig.11. Sub-threshold drain current. ID = f(VGS); conditions: Tj = 25 ˚C; VDS = VGS Fig.12. Typical capacitances, Ciss, Coss, Crss. C = f(VDS ); conditions: VGS = 0 V; f = 1 MHz 02468 1 0 1 20 BUK474-60H VGS / V ID / A Tj / C = -40 150 -60 -40 -20 0 20 40 60 80 100 120 140 Tj / C VGS(TO) / V max. typ. min. 0 1 02 03 04 05 06 07 08 00 BUK474-60H ID / A gfs / S Tj / C = -40 150 0 1 2 3 4 VGS / V ID / A1E-01 1E-02 1E-03 1E-04 1E-05 1E-06 SUB-THRESHOLD CONDUCTION typ2 % 98 % -60 -40 -20 0 20 40 60 80 100 120 140 Tj / C a Normalised RDS(ON) = f(Tj) 1.5 1.0 0.5 0.01 0.1 1 10 100 100 1000

10000 BUK474-60H

August 1996 4 Rev 1.000

Philips Semiconductors Product specification PowerMOS transistor PHB36N06E Fig.13. Typical turn-on gate-charge characteristics. VGS = f(QG ); conditions: ID = 41 A; parameter VDS Fig.14. Typical reverse diode current. IF = f(VSDS ); conditions: VGS = 0 V; parameter Tj Fig.15. Normalised avalanche energy rating. W DSS % = f(Tmb ); conditions: ID = 41 A Fig.16. Avalanche energy test circuit. 0 1 02 03 04 0 BUK474-60H QG / nC VGS / V VDS / V = 12 20 40 60 80 100 120 140 Tmb / C 120 110 100 WDSS% 0 0.5 1 1.5 20 BUK474-60H VSDS / V IF / A Tj / C = -40 150 L T.U.T. VDD RGS R 01 VDS -ID/100 shunt VGS W DSS = 0.5⋅LID 2 ⋅BV DSS /(BV DSS − VDD ) August 1996 5 Rev 1.000

Philips Semiconductors Product specification PowerMOS transistor PHB36N06E MECHANICAL DATA Dimensions in mm Net Mass: 1.4 g Fig.17. SOT404 : centre pin connected to mounting base. MOUNTING INSTRUCTIONS Dimensions in mm Fig.18. SOT404 : soldering pattern for surface mounting. Notes 1. Observe the general handling precautions for electrostatic-discharge sensitive devices (ESDs) to prevent damage to MOS gate oxide. 2. Epoxy meets UL94 V0 at 1/8". 11 max 4.5 max 1.4 max 10.3 max 0.5 15.4 2.5 0.85 max (x2) 2.54 (x2) 17.5 11.5 9.0 5.08 3.8 2.0 August 1996 6 Rev 1.000

Philips Semiconductors Product specification PowerMOS transistor PHB36N06E DEFINITIONS Data sheet status Objective specification This data sheet contains target or goal specifications for product development. Preliminary specification This data sheet contains preliminary data; supplementary data may be published later. Product specification This data sheet contains final product specifications. Limiting values Limiting values are given in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of this specification is not implied. Exposure to limiting values for extended periods may affect device reliability.

Application information

Where application information is given, it is advisory and does not form part of the specification.  Philips Electronics N.V. 1996 All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, it is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent or other industrial or intellectual property rights. LIFE SUPPORT APPLICATIONS These products are not designed for use in life support appliances, devices or systems where malfunction of these products can be reasonably expected to result in personal injury. Philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such improper use or sale. August 1996 7 Rev 1.000