PHP152NQ03LTA PHILIPS | Alldatasheet
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Technical content
N-channel TrenchMOS™ logic level FET Rev. 01 — 05 March 2004 Product data 1. Product profile
1.1 Description
Logic level N-channel enhancement mode field-effect transistor in a plastic package using TrenchMOS™ technology.
1.2 Features
1.3 Applications
1.4 Quick reference data
- Pinning information [1] It is not possible to make connection to pin 2 of the SOT404 package. ■ Logic level threshold ■ Low on-state resistance ■ Low gate charge ■ Low thermal resistance. ■ DC-to-DC converters ■ Switched-mode power supplies. ■ VDS ≤ 25 V ■ ID ≤ 75 A ■ Ptot≤ 150 W ■ R DSon ≤ 4m Ω . Table 1: Pinning - SOT78 (TO-220AB) and SOT404 (D2-PAK), simplified outlines and symbol Pin Description Simplified outline Symbol 1 gate (g) SOT78 (TO-220AB) SOT404 (D2-PAK) 2 drain (d) [1] 3 source (s) mb mounting base; connected to drain (d) MBK106 mb MBK116 mb s d g MBB076
Philips Semiconductors PHP/B152NQ03LTA N-channel TrenchMOS™ logic level FET Product data Rev. 01 — 05 March 2004 2 of 13 9397 750 12829 © Koninklijke Philips Electronics N.V. 2004. All rights reserved. 3. Ordering information 4. Limiting values Table 2: Ordering information Type number Package Name Description Version PHP152NQ03LTA TO-220AB Plastic single-ended package; heatsink mounted; 1 mounting hole; 3 leads SOT78 PHB152NQ03LTA D 2-PAK Plastic single-ended surface mounted package; 3 leads (one lead cropped) SOT404 Table 3: Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol Parameter Conditions Min Max Unit VDS drain-source voltage (DC) 25 °C ≤ Tj≤ 175 °C - 25 V VDGR drain-gate voltage (DC) 25 °C ≤ Tj≤ 175 °C; RGS =2 0kΩ -2 5 V VGS gate-source voltage - ±20 V ID drain current (DC) T mb =2 5°C; VGS =1 0V ;Figure 2and 3 -7 5 A Tmb = 100°C; VGS =1 0V ;Figure 2 -7 5 A IDM peak drain current T mb =2 5°C; pulsed; tp ≤ 10 µs;Figure 3 - 240 A Ptot total power dissipation T mb =2 5°C; Figure 1 - 150 W Tstg storage temperature −55 +175 °C Tj junction temperature −55 +175 °C Source-drain diode I S source (diode forward) current (DC) Tmb =2 5°C - 75 A ISM peak source (diode forward) current Tmb =2 5°C; pulsed; tp ≤ 10 µs - 240 A Avalanche ruggedness E DS(AL)S non-repetitive drain-source avalanche energy unclamped inductive load; ID =7 5A ; tp = 0.46 ms; VDD ≤ 25 V; RGS =5 0Ω ; VGS = 10 V; starting Tj=2 5°C - 560 mJ
Philips Semiconductors PHP/B152NQ03LTA N-channel TrenchMOS™ logic level FET Product data Rev. 01 — 05 March 2004 3 of 13 9397 750 12829 © Koninklijke Philips Electronics N.V. 2004. All rights reserved. Fig 1. Normalized total power dissipation as a function of mounting base temperature. Fig 2. Normalized continuous drain current as a function of mounting base temperature. Tmb =2 5°C; IDM is single pulse; VGS =1 0V Fig 3. Safe operating area; continuous and peak drain currents as a function of drain-source voltage. 03aa16 120 0 50 100 150 200 Tmb (°C) Pder (%) 120 05 0 100 150 200 Tmb (°C) Ider (%) 003aaa630 P der P tot P tot 25 C°() ID I D2 5C°() 003aaa517 102 103 10-1 1 10 10 2 VDS (V) ID (A) DC 100 ms 10 ms 1 ms LImit RDSon = VDS / ID tp = 10 µs 100 µs
Philips Semiconductors PHP/B152NQ03LTA N-channel TrenchMOS™ logic level FET Product data Rev. 01 — 05 March 2004 4 of 13 9397 750 12829 © Koninklijke Philips Electronics N.V. 2004. All rights reserved. 5. Thermal characteristics
5.1 Transient thermal impedance
Table 4: Thermal characteristics Symbol Parameter Conditions Min Typ Max Unit R th(j-mb) thermal resistance from junction to mounting baseFigure 4 --1 K / W R th(j-a) thermal resistance from junction to ambient SOT78 vertical in still air - 60 - K/W SOT404 mounted on a printed-circuit board; minimum footprint - 50 - K/W Fig 4. Transient thermal impedance from junction to mounting base as a function of pulse duration. 003aaa518 10-2 10-1 10-5 10-4 10-3 10-2 10-1 1tp (s) Zth(j-mb) (K/W) single pulse 0.2 0.1 0.05 δ = 0.5 0.02 tp tp T P t Tδ =
Philips Semiconductors PHP/B152NQ03LTA N-channel TrenchMOS™ logic level FET Product data Rev. 01 — 05 March 2004 5 of 13 9397 750 12829 © Koninklijke Philips Electronics N.V. 2004. All rights reserved. 6. Characteristics Table 5: Characteristics Tj=2 5°C unless otherwise specified. Symbol Parameter Conditions Min Typ Max Unit Static characteristics V (BR)DSS drain-source breakdown voltage ID = 250µA; VGS =0V Tj=2 5°C 2 5 --V Tj= −55 °C 2 2 --V VGS(th) gate-source threshold voltage ID = 1 mA; VDS =V GS ;Figure 9 Tj=2 5°C 1 1.5 2 V IDSS drain-source leakage current V DS =2 5V ; VGS =0V Tj=2 5°C --1 µA Tj= 175°C - - 500 µA IGSS gate-source leakage current V GS = ±15 V; VDS = 0 V - 10 100 nA R DSon drain-source on-state resistance VGS =5V ; ID =2 5A ;Figure 7and 8 Tj=2 5°C - 4.2 5 m Ω Tj= 175°C - 6.8 8.7 m Ω VGS = 10 V; ID =2 5A ;Figure 7and 8 Tj=2 5°C - 3.4 4 m Ω Tj= 175°C - 5.5 6.9 m Ω Dynamic characteristics Q g(tot) total gate charge I D =5 0A ;VDD =1 5V ;VGS =5V ;Figure 13 -3 6 -n C Q gs gate-source charge - 13 - nC Q gd gate-drain (Miller) charge - 12 - nC C iss input capacitance V GS =0V ; VDS = 25 V; f = 1 MHz; Figure 11 -3 1 4 0 -p F C oss output capacitance - 1040 - pF C rss reverse transfer capacitance - 354 - pF td(on) turn-on delay time V DD =1 5V ; ID =2 5A ; VGS =5V ;R G = 5.6Ω -3 7 -n s tr rise time -8 7 -n s td(off) turn-off delay time - 71 - ns tf fall time -4 6 -n s Source-drain diode V SD source-drain (diode forward) voltage IS = 25 A; VGS =0V ;Figure 12 - 0.85 1.2 V trr reverse recovery time I S = 10 A; dIS/dt =−100 A/µs; VGS =0V ;V R =2 5V -5 0 -n s Q r recovered charge - 24 - nC
Philips Semiconductors PHP/B152NQ03LTA N-channel TrenchMOS™ logic level FET Product data Rev. 01 — 05 March 2004 6 of 13 9397 750 12829 © Koninklijke Philips Electronics N.V. 2004. All rights reserved. Tj=2 5°CT j=2 5°C and 175°C; VDS > ID xR DSon Fig 5. Output characteristics: drain current as a function of drain-source voltage; typical values. Fig 6. Transfer characteristics: drain current as a function of gate-source voltage; typical values. Tj=2 5°C Fig 7. Drain-source on-state resistance as a function of drain current; typical values. Fig 8. Normalized drain-source on-state resistance factor as a function of junction temperature. 003aaa519 0 0.2 0.4 0.6 0.8 1 VDS (V) ID (A) 2.4 V 2.5 V 2.1 V 2.8 V 2 .3 V
3 V5 V10 V
VGS = 2.7 V 2.6 V 003aaa520 0123 VGS (V) ID (A) 25 °C Tj = 175 °C 003aaa521 0 1 02 03 04 0 ID (A) R DSon (mΩ ) 10 V 5 V VGS = 3 V 003aaa627 0.5 1.5 -60 0 60 120 180 Tj (°C) a a R DSon R DSon 25 C°()
Philips Semiconductors PHP/B152NQ03LTA N-channel TrenchMOS™ logic level FET Product data Rev. 01 — 05 March 2004 7 of 13 9397 750 12829 © Koninklijke Philips Electronics N.V. 2004. All rights reserved. ID = 1 mA; VDS =V GS Tj=2 5°C; VDS =5V Fig 9. Gate-source threshold voltage as a function of junction temperature. Fig 10. Sub-threshold drain current as a function of gate-source voltage. VGS = 0 V; f = 1 MHz Fig 11. Input, output and reverse transfer capacitances as a function of drain-source voltage; typical values. 03aa33 0.5 1.5 2.5 -60 0 60 120 180 Tj (°C) VGS(th) (V) max typ min 03aa36 10-6 10-5 10-4 10-3 10-2 10-1 0123 VGS (V) ID (A) maxtypmin 003aaa522 102 103 104 10-1 1 10 10 2 VDS (V) C (pF) C iss C oss C rss
Philips Semiconductors PHP/B152NQ03LTA N-channel TrenchMOS™ logic level FET Product data Rev. 01 — 05 March 2004 8 of 13 9397 750 12829 © Koninklijke Philips Electronics N.V. 2004. All rights reserved. Tj=2 5°C and 175°C; VGS =0V I D = 50 A; VDD =1 5V Fig 12. Source (diode forward) current as a function of source-drain (diode forward) voltage; typical values. Fig 13. Gate-source voltage as a function of gate charge; typical values. 003aaa523 0.2 0.4 0.6 0.8 1 VSD (V) IS (A) 25 °C Tj = 175 °C 003aaa524 0 2 04 06 08 0 Q G (nC) VGS (V)
Philips Semiconductors PHP/B152NQ03LTA N-channel TrenchMOS™ logic level FET Product data Rev. 01 — 05 March 2004 9 of 13 9397 750 12829 © Koninklijke Philips Electronics N.V. 2004. All rights reserved. 7. Package outline Fig 14. SOT78 (TO-220AB). REFERENCESOUTLINE VERSION EUROPEAN PROJECTION ISSUE DATE IEC JEDEC EIAJ SOT78 SC-46 3-lead TO-220AB D D 1 q p L 123 L1(1) e e b 0 5 10 mm scale Plastic single-ended package; heatsink mounted; 1 mounting hole; 3-lead TO-220AB SOT78 DIMENSIONS (mm are the original dimensions) AE c Note 1. Terminals in this zone are not tinned. Q UNIT A 1 b1 D 1 e p mm 2.54 qQA b Dc L2 max. 3.0 3.8 3.6 15.0 13.5 3.30 2.79 3.0 2.7 2.6 2.2 0.7 0.4 15.8 15.2 0.9 0.7 1.3 1.0 4.5 4.1 1.39 1.27 6.4 5.9 10.3 9.7 L1(1)E L 00-09-07 01-02-16 mounting base
Philips Semiconductors PHP/B152NQ03LTA N-channel TrenchMOS™ logic level FET Product data Rev. 01 — 05 March 2004 10 of 13 9397 750 12829 © Koninklijke Philips Electronics N.V. 2004. All rights reserved. Fig 15. SOT404 (D2-PAK). UNIT A REFERENCESOUTLINE VERSION EUROPEAN PROJECTION ISSUE DATE IEC JEDEC EIAJ mm A 1 D 1 D max. E eL p H D Qc 2.54 2.60 2.20 15.80 14.80 2.90 2.1011 1.60 1.20 10.30 9.70 4.50 4.10 1.40 1.27 0.85 0.60 0.64 0.46 b DIMENSIONS (mm are the original dimensions) SOT404 0 2.5 5 mm scale Plastic single-ended surface mounted package (Philips version of D2-PAK); 3 leads (one lead cropped) SOT404 e e E b D 1 H D D Q Lp c A mounting base 99-06-25 01-02-12
Philips Semiconductors PHP/B152NQ03LTA N-channel TrenchMOS™ logic level FET Product data Rev. 01 — 05 March 2004 11 of 13 9397 750 12829 © Koninklijke Philips Electronics N.V. 2004. All rights reserved. 8. Revision history Table 6: Revision history Rev Date CPCN Description 01 20040305 - Product data. (9397 750 12829)
Philips Semiconductors PHP/B152NQ03LTA N-channel TrenchMOS™ logic level FET © Koninklijke Philips Electronics N.V. 2004. All rights reserved. Product data Rev. 01 — 05 March 2004 12 of 13 9397 750 12829 Philips Semiconductors PHP/B152NQ03LTA N-channel TrenchMOS™ logic level FET © Koninklijke Philips Electronics N.V. 2004. All rights reserved. Product data Rev. 01 — 05 March 2004 12 of 13 Contact information For additional information, please visithttp://www.semiconductors.philips.com. 9. Data sheet status [1] Please consult the most recently issued data sheet before initiating or completing a design. [2] The product status of the device(s) described in this data sheet may have changed since this data sheet was published. The latest information is available on the Internet at URL http://www.semiconductors.philips.com. [3] For data sheets describing multiple type numbers, the highest-level product status determines the data sheet status. 10. Definitions Short-form specification —The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook. Limiting values definition — Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 60134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information — Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification. 11. Disclaimers Life support —These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application. Right to make changes —Philips Semiconductors reserves the right to make changes in the products - including circuits, standard cells, and/or software - described or contained herein in order to improve design and/or performance. When the product is in full production (status ‘Production’), relevant changes will be communicated via a Customer Product/Process Change Notification (CPCN). Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no licence or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified. 12. Trademarks TrenchMOS — is a trademark of Koninklijke Philips Electronics N.V. Level Data sheet status[1] Product status[2][3] Definition I Objective data Development This data sheet contains data from the objective specification for product development. Philips Semiconductors reserves the right to change the specification in any manner without notice. II Preliminary data Qualification This data sheet contains data from the preliminary specification. Supplementary data will be published at a later date. Philips Semiconductors reserves the right to change the specification without notice, in order to improve the design and supply the best possible product. III Product data Production This data sheet contains data from the product specification. Philips Semiconductors reserves the right to make changes at any time in order to improve the design, manufacturing and supply. Relevant changes will be communicated via a Customer Product/Process Change Notification (CPCN).
© Koninklijke Philips Electronics N.V. 2004. Printed in The Netherlands All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights. Date of release: 05 March 2004 Document order number: 9397 750 12829
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Philips Semiconductors PHP/B152NQ03LTA N-channel TrenchMOS™ logic level FET