PHB130N03LT

PHB130N03LT PHILIPS | Alldatasheet

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Philips Semiconductors Product specification TrenchMOS  transistor PHB130N03LT Logic level FET GENERAL DESCRIPTION QUICK REFERENCE DATA N-channel enhancement mode logic SYMBOL PARAMETER MAX. UNIT level field-effect power transistor in a plastic envelope suitable for surface VDS Drain-source voltage 30 V mounting using ’trench’ technology. ID Drain current (DC)1 75 A Thedevice features verylow on-state Ptot Total power dissipation 187 W resistance and has integral zener Tj Junction temperature 175 ˚C diodes giving ESD protection up to RDS(ON) Drain-source on-state 6 m Ω 2kV. It is intended for use in DC-DC resistance V GS = 5 V converters and general purpose switching applications. PINNING - SOT404 PIN CONFIGURATION SYMBOL PIN DESCRIPTION 1 gate 2 drain 3 source mb drain LIMITING VALUES Limiting values in accordance with the Absolute Maximum System (IEC 134) SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT VDS Drain-source voltage - - 30 V VDGR Drain-gate voltage R GS = 20 kΩ -3 0V ±VGS Gate-source voltage - - 10 V ID Drain current (DC)1 Tmb = 25 ˚C - 75 A ID Drain current (DC)1 Tmb = 100 ˚C - 75 A IDM Drain current (pulse peak value) Tmb = 25 ˚C - 240 A Ptot Total power dissipation T mb = 25 ˚C - 187 W Tstg, Tj Storage & operating temperature - - 55 175 ˚C THERMAL RESISTANCES SYMBOL PARAMETER CONDITIONS TYP. MAX. UNIT R th j-mb Thermal resistance junction to - - 0.8 K/W mounting base R th j-a Thermal resistance junction to minimum footprint, FR4 50 - K/W ambient board d g s13 mb 1 Current limited by package to 75A from a theoretical value of 130A. December 1997 1 Rev 1.200

Philips Semiconductors Product specification TrenchMOS transistor PHB130N03LT Logic level FET ESD LIMITING VALUE SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT VC Electrostatic discharge capacitor Human body model - 2 kV voltage, all pins (100 pF, 1.5 k Ω ) STATIC CHARACTERISTICS Tj= 25˚C unless otherwise specified SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT V(BR)DSS Drain-source breakdown V GS = 0 V; ID = 0.25 mA; 30 - - V voltage T j = -55˚C 27 - - V VGS(TO) Gate threshold voltage V DS = VGS ; ID = 1 mA 1.0 1.5 2.0 V Tj = 175˚C 0.5 - - V IDSS Zero gate voltage drain current VDS = 30 V; VGS = 0 V; - 0.05 10 µA Tj = 175˚C - - 500 µA IGSS Gate source leakage current VGS = ±5 V; VDS = 0 V - 0.02 1 µA Tj = 175˚C - - 10 µA ±V(BR)GSS Gate-source breakdown I G = ±1 mA; 10 - - V voltage R DS(ON) Drain-source on-state V GS = 5 V; ID = 25 A - 5 6 m Ω resistance T j = 175˚C - - 11 m Ω DYNAMIC CHARACTERISTICS Tmb = 25˚C unless otherwise specified SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT gfs Forward transconductance V DS = 25 V; ID = 25 A 20 40 - S Q g(tot) Total gate charge I D = 75 A; VDD = 24 V; VGS = 5 V - 92 - nC Q gs Gate-source charge - 10 - nC Q gd Gate-drain (Miller) charge - 36 - nC C iss Input capacitance V GS = 0 V; VDS = 25 V; f = 1 MHz - 5000 - pF C oss Output capacitance - 1150 - pF C rss Feedback capacitance - 500 - pF td on Turn-on delay time V DD = 15 V; ID = 25 A; - 45 60 ns tr Turn-on rise time V GS = 5 V; RG = 5 Ω - 120 170 ns td off Turn-off delay time Resistive load - 225 300 ns tf Turn-off fall time - 100 135 ns Ld Internal drain inductance Measured from tab to centre of die - 3.5 - nH Ld Internal drain inductance Measured from drain lead solder - 4.5 - nH point to centre of die Ls Internal source inductance Measured from source lead solder - 7.5 - nH point to source bond pad December 1997 2 Rev 1.200

Philips Semiconductors Product specification TrenchMOS transistor PHB130N03LT Logic level FET REVERSE DIODE LIMITING VALUES AND CHARACTERISTICS Tj = 25˚C unless otherwise specified SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT IDR Continuous reverse drain - - 75 A current IDRM Pulsed reverse drain current - - 240 A VSD Diode forward voltage I F = 25 A; VGS = 0 V - 0.85 1.2 V IF = 75 A; VGS = 0 V - 1.0 - V trr Reverse recovery time I F = 75 A; -dIF/dt = 100 A/µs; - 100 - ns Q rr Reverse recovery charge V GS = -10 V; VR = 25 V - 0.6 - µC AVALANCHE LIMITING VALUE SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT W DSS Drain-source non-repetitive ID = 75 A; VDD ≤ 15 V; - - 500 mJ unclamped inductive turn-off VGS = 5 V; RGS = 50 Ω ; Tmb = 25 ˚C energy December 1997 3 Rev 1.200

Philips Semiconductors Product specification TrenchMOS transistor PHB130N03LT Logic level FET Fig.1. Normalised power dissipation. PD% = 100⋅PD /PD 25 ˚C = f(Tmb ) Fig.2. Normalised continuous drain current. ID% = 100⋅ID /ID 25 ˚C = f(Tmb ); conditions: VGS ≥ 5 V Fig.3. Safe operating area. Tmb = 25 ˚C ID & IDM = f(VDS ); IDM single pulse; parameter tp Fig.4. Transient thermal impedance. Zth j-mb = f(t); parameter D = tp/T Fig.5. Typical output characteristics, Tj = 25 ˚C. ID = f(VDS ); parameter VGS Fig.6. Typical on-state resistance, Tj = 25 ˚C. R DS(ON) = f(ID ); parameter VGS 0 20 40 60 80 100 120 140 160 180 Tmb / C PD% Normalised Power Derating120 110 100 1E-07 1E-05 1E-03 1E-01 1E+01 t / s Zth / (K/W) 1E+00 1E-01 1E-02 1E-03 0.5 0.2 0.1 0.05

0.02 D = tp tp

T TP t D Tmb / C 0 20 40 60 80 100 120 140 160 1800 100 120 140 ID (A) Current Derating Limited by package 02468 1 00 100 BUK9506-30 VDS / V ID / A VGS / V = 2.2 2.4 2.6 2.8 3.56 1 10 1001 100 1000 7506-30 VDS / V ID / A RDS(ON) = VDS / ID tp = 10 us 100 us 1 ms 10 ms 100 ms DC 0 2 04 06 08 0 1 0 00 9506-30 ID / A RDS(ON) / mOhm 3.5 December 1997 4 Rev 1.200

Philips Semiconductors Product specification TrenchMOS transistor PHB130N03LT Logic level FET Fig.7. Typical transfer characteristics. ID = f(VGS ) ; conditions: VDS = 25 V; parameter Tj Fig.8. Typical transconductance, Tj = 25 ˚C. gfs = f(ID ); conditions: VDS = 25 V Fig.9. Normalised drain-source on-state resistance. a = RDS(ON) /RDS(ON)25 ˚C = f(Tj); ID = 25 A; VGS = 5 V Fig.10. Gate threshold voltage. VGS(TO) = f(Tj); conditions: ID = 1 mA; VDS = VGS Fig.11. Sub-threshold drain current. ID = f(VGS); conditions: Tj = 25 ˚C; VDS = VGS Fig.12. Typical capacitances, Ciss, Coss, Crss. C = f(VDS ); conditions: VGS = 0 V; f = 1 MHz 0123450 100 9506-30 VGS / V ID / A Tj / C = 175 25 BUK959-60 -100 -50 0 50 100 150 2000 0.5 1.5 2.5 Tj / C VGS(TO) / V max. typ. min. 0 2 04 06 08 0 1 0 00 100 9506-30 ID / A gfs / S Tj / C = 25 175 0 0.5 1 1.5 2 2.5 31E-05 1E-05 1E-04 1E-03 1E-02 1E-01 Sub-Threshold Conduction 2% typ 98% -100 0 100 2000 0.5 1.5 2 30V TrenchMOS Tj / C a 15050-50 0.1 1 10 100100 1000 10000 9506-30 VDS / V C / pF Ciss Coss Crss December 1997 5 Rev 1.200

Philips Semiconductors Product specification TrenchMOS transistor PHB130N03LT Logic level FET Fig.13. Typical turn-on gate-charge characteristics. VGS = f(QG ); conditions: ID = 75 A; parameter VDS Fig.14. Typical reverse diode current. IF = f(VSDS ); conditions: VGS = 0 V; parameter Tj Fig.15. Normalised avalanche energy rating. W DSS % = f(Tmb ); conditions: ID = 75 A Fig.16. Avalanche energy test circuit. Fig.17. Switching test circuit. 0 2 04 06 08 0 1 0 00 9506-30 QG / nC VGS / V VDS / V = 6 24 20 40 60 80 100 120 140 160 180 Tmb / C 120 110 100 WDSS% 0 0.5 1 1.5 20 100 9506-30 VSDS / V IF / A Tj / C = 175 25 L T.U.T. VDD RGS R 01 VDS -ID/100 shunt VGS W DSS = 0.5⋅LID 2 ⋅BV DSS /(BV DSS − VDD ) RD T.U.T. VDD RG VDS VGS December 1997 6 Rev 1.200

Philips Semiconductors Product specification TrenchMOS transistor PHB130N03LT Logic level FET MECHANICAL DATA Dimensions in mm Net Mass: 1.4 g Fig.18. SOT404 : centre pin connected to mounting base. MOUNTING INSTRUCTIONS Dimensions in mm Fig.19. SOT404 : soldering pattern for surface mounting. Notes 1. Observe the general handling precautions for electrostatic-discharge sensitive devices (ESDs) to prevent damage to MOS gate oxide. 2. Epoxy meets UL94 V0 at 1/8". 11 max 4.5 max 1.4 max 10.3 max 0.5 15.4 2.5 0.85 max (x2) 2.54 (x2) 17.5 11.5 9.0 5.08 3.8 2.0 December 1997 7 Rev 1.200

Philips Semiconductors Product specification TrenchMOS transistor PHB130N03LT Logic level FET DEFINITIONS Data sheet status Objective specification This data sheet contains target or goal specifications for product development. Preliminary specification This data sheet contains preliminary data; supplementary data may be published later. Product specification This data sheet contains final product specifications. Limiting values Limiting values are given in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of this specification is not implied. Exposure to limiting values for extended periods may affect device reliability.

Application information

Where application information is given, it is advisory and does not form part of the specification.  Philips Electronics N.V. 1997 All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, it is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent or other industrial or intellectual property rights. LIFE SUPPORT APPLICATIONS These products are not designed for use in life support appliances, devices or systems where malfunction of these products can be reasonably expected to result in personal injury. Philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such improper use or sale. December 1997 8 Rev 1.200