PH5525L

PH5525L PHILIPS | Alldatasheet

Document overview

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Technical content

1.1 General description

package using TrenchMOS technology.

1.2 Features

1.3 Applications

1.4 Quick reference data

Table 1. Pinning

PH5525L_2 © NXP B.V. 2006. All rights reserved. Table 2. Ordering information Table 3. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134).

PH5525L_2 © NXP B.V. 2006. All rights reserved. Product data sheet Rev. 02 — 5 December 2006 3 of 12 NXP Semiconductors PH5525L N-channel TrenchMOS logic level FET Fig 1. Normalized total power dissipation as a function of mounting base temperature Fig 2. Normalized continuous drain current as a function of mounting base temperature Tmb =2 5°C; IDM is single pulse Fig 3. Safe operating area; continuous and peak drain currents as a function of drain-source voltage 03aa15 120 0 50 100 150 200 Tmb Pder (%) (°C) 03aa23 120 0 50 100 150 200 (%) Ider Tmb (°C) P der P tot P tot 25°C() ID ID2 5 °C() 003aab437 102 103 10-1 1 10 10 2 VDS (V) ID (A) DC 1 ms 100 µ s Limit RDSon = VDS / ID 10 ms 100 ms 10 µ stp =

PH5525L_2 © NXP B.V. 2006. All rights reserved. Table 4. Thermal characteristics

PH5525L_2 © NXP B.V. 2006. All rights reserved. Table 5. Characteristics Tj=2 5°C unless otherwise specified.

PH5525L_2 © NXP B.V. 2006. All rights reserved. Product data sheet Rev. 02 — 5 December 2006 6 of 12 NXP Semiconductors PH5525L N-channel TrenchMOS logic level FET Tj=2 5°CT j=2 5°C Fig 5. Output characteristics: drain current as a function of drain-source voltage; typical values Fig 6. Drain-source on-state resistance as a function of drain current; typical values Tj=2 5°C and 150°C; VDS >ID × R DSon Fig 7. Transfer characteristics: drain current as a function of gate-source voltage; typical values Fig 8. Normalized drain-source on-state resistance factor as a function of junction temperature 003aab439 100 0 0.2 0.4 0.6 0.8 1 V DS (V) ID (A) 3.8 3.6 3.4 10 4.5 VGS (V) = 2.8 3.2 003aab440 0 2 04 06 08 0 1 0 0 I D (A) R DSon (mΩ ) 3.6 3.4 3.8 4.5 VGS (V) = 3.2 003aab441 012345 V GS (V) ID (A) Tj = 150 °C 25 °C 003aab467 0.4 0.8 1.2 1.6 -60 0 60 120 180 T j (°C) a a R DSon R DSon 25 °C()

PH5525L_2 © NXP B.V. 2006. All rights reserved. Product data sheet Rev. 02 — 5 December 2006 7 of 12 NXP Semiconductors PH5525L N-channel TrenchMOS logic level FET ID = 1 mA; VDS =V GS Tj=2 5°C; VDS =5V Fig 9. Gate-source threshold voltage as a function of junction temperature Fig 10. Sub-threshold drain current as a function of gate-source voltage ID = 25 A; VDS = 12 V and 19 V Fig 11. Gate-source voltage as a function of gate charge; typical values Fig 12. Gate charge waveform definitions 003aab272 0.5 1.5 2.5 -60 0 60 120 180 Tj (°C) VGS(th) (V) max typ min 003aab271 10-6 10-5 10-4 10-3 00 . 511 . 522 . 5 VGS (V) ID (A) maxtypmin 003aab442 0 1 02 03 04 0 Q G (nC) VGS (V) ID = 25 A Tj = 25 °C VDS = 19 V12 V 003aaa508 VGS VGS(th) Q GS1 Q GS2 Q GD VDS Q G(tot) ID Q GS VGS(pl)

PH5525L_2 © NXP B.V. 2006. All rights reserved. Product data sheet Rev. 02 — 5 December 2006 8 of 12 NXP Semiconductors PH5525L N-channel TrenchMOS logic level FET Tj=2 5°C and 150°C; VGS =0V V GS = 0 V; f = 1 MHz Fig 13. Source current as a function of source-drain voltage; typical values Fig 14. Input, output and reverse transfer capacitances as a function of drain-source voltage; typical values 003aab443 0.2 0.4 0.6 0.8 1 V SD (V) IS (A) Tj = 25 °C150 °C 003aab444 102 103 104 10-1 1 10 10 2 VDS (V) C (pF) C iss C rss C oss

PH5525L_2 © NXP B.V. 2006. All rights reserved. Product data sheet Rev. 02 — 5 December 2006 9 of 12 NXP Semiconductors PH5525L N-channel TrenchMOS logic level FET 7. Package outline Fig 15. Package outline SOT669 (LFPAK) REFERENCESOUTLINE VERSION EUROPEAN PROJECTION ISSUE DATE IEC JEDEC JEITA SOT669 MO-235 04-10-13 06-03-16 0 2.5 5 mm scale e b A 2 bcA eUNIT DIMENSIONS (mm are the original dimensions) mm 1.10 0.95 A 3A 1 0.15 0.00 1.20 1.01 0.50 0.35 4.41 3.62 2.2 2.0 0.9 0.7 0.25 0.19 0.30 0.24 4.10 3.80 6.2 5.8 H 1.3 0.8 0.85 0.40 L 1.3 0.8 wyD (1) 5.0 4.8 E(1) 3.3 3.1 (1)D 1(1) max 1 23 4 mounting base D 1 c Plastic single-ended surface-mounted package (LFPAK); 4 leads SOT669 E H D A Aw M C C X 1/2 e yC q q (A )3 L A detail X Note 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.

PH5525L_2 © NXP B.V. 2006. All rights reserved. Table 6. Revision history

• Section1.2: updated the list PH5525L_1 20061010 Product data sheet - -

PH5525L_2 © NXP B.V. 2006. All rights reserved. Product data sheet Rev. 02 — 5 December 2006 11 of 12 NXP Semiconductors PH5525L N-channel TrenchMOS logic level FET 9. Legal information

9.1 Data sheet status

[1] Please consult the most recently issued document before initiating or completing a design. [2] The term ‘short data sheet’ is explained in section “Definitions”. [3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com.

9.2 Definitions

Draft —The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet —A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail.

9.3 Disclaimers

General — Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. Right to make changes —NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use —NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in medical, military, aircraft, space or life support equipment, nor in applications where failure or malfunction of a NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer’s own risk. Applications —Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Limiting values —Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) may cause permanent damage to the device. Limiting values are stress ratings only and operation of the device at these or any other conditions above those given in the Characteristics sections of this document is not implied. Exposure to limiting values for extended periods may affect device reliability. Terms and conditions of sale —NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms , including those pertaining to warranty, intellectual property rights infringement and limitation of liability, unless explicitly otherwise agreed to in writing by NXP Semiconductors. In case of any inconsistency or conflict between information in this document and such terms and conditions, the latter will prevail. No offer to sell or license —Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights.

9.4 Trademarks

Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. TrenchMOS — is a trademark of NXP B.V. 10. Contact information For additional information, please visit:http://www.nxp.com For sales office addresses, send an email to:salesaddresses@nxp.com Document status[1][2] Product status[3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification.

NXP Semiconductors PH5525L N-channel TrenchMOS logic level FET © NXP B.V. 2006. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com Date of release: 5 December 2006 Document identifier: PH5525L_2 Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. 11. Contents