PGA5807

PGA5807 TI1 | Alldatasheet

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www.ti.com SBAS617B –MAY 2013–REVISED JUNE 2013 8-Channel,High-Bandwidth,AnalogFront-End Check forSamples: PGA5807 1FEATURES APPLICATIONS 2• 8-ChannelComplete AFE: • Data AcquisitionFrontEnds – LNA, PGA, and LPF • UltrasoundImaging – Full-ChannelGain:12 dB to30 dB DESCRIPTION– Input-ReferredNoise:2.1nV/√Hz The PGA5807 is an 8-channel,high-bandwidth,• LNA: analog front-end(AFE).The devicefunctionson a – Gain:12 dB single3.3-Vanalogsupply.The devicesupportshigh- bandwidthinputfrequencieswitha totalpower of60– FullyDifferential mW per channel.The PGA5807 consistsof a low-– Wide InputCommon-Mode Support: noiseamplifier(LNA),a programmable gainamplifier2.1± 200 mV (PGA), and a programmable low-passfilter(LPF). – Maximum LinearInputRange: 500 mV PP The LNA has a fixed12-dB gain (thedifferential amplifiersupportsboth directand capacitiveinput• PGA: Gain 0 dB to18 dB coupling)and supportsa maximum linearinputrange– With 3-dB Gain Steps of500 mV PP . – Programmable viaEitherSerialInterfaceor The deviceprovidesgainoptionsfrom0 dB to18 dB,ExternalPins in 3-dB gain steps.This 18-dB PGA gain can be• Maximum TotalChannel Gain:30 dB programmed using eitherthe serialinterfaceor

• Programmable LPF: external pins. The PGA5807 integrates an antialiasingfilterin the form of an LPF to reduce– Corner Frequency:75 MHz, 60 MHz noise.The deviceisavailableina verysmall,9-mm ו Power (Full-Chain): 9-mm QFN-64 package and isspecifiedforoperation – 60 mW per Channel overthe–40°C to+85°C temperaturerange.
• Fastand ConsistentOverload Recovery
• Small Package: 9-mm × 9-mm QFN-64 Pleasebe aware thatan importantnoticeconcerningavailability,standardwarranty,and use incriticalapplicationsof Texas Instrumentssemiconductorproductsand disclaimerstheretoappearsattheend ofthisdatasheet. 2Alltrademarksarethepropertyoftheirrespectiveowners. PRODUCTION DATA informationiscurrentas ofpublicationdate. Copyright© 2013,Texas InstrumentsIncorporatedProductsconform to specificationsper the terms of the Texas Instrumentsstandardwarranty.Productionprocessingdoes not necessarilyincludetestingofallparameters.

SBAS617B –MAY 2013–REVISED JUNE 2013 www.ti.com This integratedcircuitcan be damaged by ESD. Texas Instrumentsrecommends thatallintegratedcircuitsbe handled with appropriateprecautions.Failuretoobserveproperhandlingand installationprocedurescan cause damage. ESD damage can rangefromsubtleperformancedegradationtocompletedevicefailure.Precisionintegratedcircuitsmay be more susceptibletodamage because verysmallparametricchanges couldcause thedevicenottomeet itspublishedspecifications. ORDERING INFORMATION (1) PRODUCT PACKAGE-LEAD PACKAGE DESIGNATOR PGA5807 QFN-64 RGC (1) Forthemost currentpackage and orderinginformation,see thePackage OptionAddendum attheend ofthisdocument,orvisitthe deviceproductfolderatwww.ti.com. ABSOLUTE MAXIMUM RATINGS Over operatingfree-airtemperaturerange,unlessotherwisenoted.(1) VALUE UNIT Supplyvoltagerange AVDD –0.3to3.9 V Voltageatanaloginputand digitalinput –0.3tominimum (3.6,AVDD + 0.3) V Operating,TA –40 to+85 °C Temperaturerange Storage,Tstg –55 to+150 °C Electrostaticdischarge(ESD) ratings Human body model (HBM) 1 kV (1) Stressesbeyond thoselistedunderAbsoluteMaximum Ratingsmay cause permanentdamage tothedevice.These arestressratings only,and do notimplyfunctionaloperationofthedeviceattheseorany otherconditionsbeyond thoseindicatedunderRecommended OperatingConditions.Exposuretoabsolute-maximum-ratedconditionsforextendedperiodsmay affectdevicereliability. RECOMMENDED OPERATING CONDITIONS MIN NOM MAX UNIT AVDD Analogvoltagesupply 3.15 3.6 V TA Operatingtemperature –40 +85 °C Inputcommon-mode voltagerange 1.9 2.3 V THERMAL INFORMATION PGA5807 THERMAL METRIC (1) RGC (QFN) UNITS

64 PINS

θJA Junction-to-ambientthermalresistance 22.8 θJCtop Junction-to-case(top)thermalresistance 6.9 θJB Junction-to-boardthermalresistance 2.4 °C/W ψJT Junction-to-topcharacterizationparameter 0.1 ψJB Junction-to-boardcharacterizationparameter 2.4 θJCbot Junction-to-case(bottom)thermalresistance 0.2 (1) Formore informationabouttraditionaland new thermalmetrics,see theIC Package ThermalMetricsapplicationreport,SPRA953 .

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ELECTRICAL CHARACTERISTICS

TypicalvaluesareatTA = +25°C, AVDD = 3.3V,inputdc-coupledwitha 2.1-Vcommon-mode voltage,LNA gain= 12 dB, PGA gain= 18 dB,totalchannelgain= 30 dB,bandwidth= high,and VOUT = –1 dBFS, unlessotherwisespecified. Minimum and maximum valuesarespecifiedacrossthefulltemperaturerangeofTMIN = –40°C toTMAX = +85°C withAVDD = 3.3V. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Input-referrednoise f= 25 MHz, totalchannelgain= 30 dB 2.1 nV/√Hz Noisefigure R S = 100 Ω,differential 6.4 dB Maximum linearinputvoltage Totalchannelgain= 12 dB,differential 500 mV PP Maximum linearoutputswing 2 VPP G LNA LNA gain 12 dB Maximum channelgain 29 30 31 dB PGA gainrange 0 18 dB Gain step 3 dB Totaloutput-referrednoise Totalchannelgain= 30 dB 450 µV Inputresistance 5 kΩ C i Inputcapacitance 3 pF LPF –3-dB cutofffrequency 75 MHz Acrossdevices,TA = +25°C –1 1 dB Gain matching Acrosschannelsinthesame device ±0.25 dB VICR Inputcommon-mode voltagerange 1.9 2.3 V Outputoffset –50 50 mV VOCR Outputcommon-mode voltage 950 mV HD2 Second f= 25 MHz, VOUT = –1 dBFS –55 dBc HarmonicHD3 Third f= 25 MHz, VOUT = –1 dBFS –50 dBcdistortion THD Total f= 25 MHz, VOUT = –1 dBFS –48 dBc f1 = 25 MHz at–7 dBFS, f2 = 25 MHz,IMD3 Intermodulationdistortion –45 dBc1 MHz at–7 dBFS, forallPGA gains Fundamentalcrosstalk f= 25 Mz, VOUT = –1 dBFS –50 dBc Total,perchannel 60 69 mW/ch PD Power dissipation Partialpower-down 4.2 mW/ch Power-down mode Completepower-down 2.5 mW/ch AVDD current(3.3V) 145 mA Settlingtimeforoverloadrecovery For12-dB highersignalthanlinearinput –30 ns Partialpower-down 1 µs Power-upresponsetime Fullpower-down 1 ms f= 10 kHz,gain= 30 dB –40 dBc PSRR Power-supplyrejectionratio f= 10 kHz,gain= 12 dB –38 dBc Copyright© 2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 3 ProductFolderLinks:PGA5807

AVDD AVDD AVDD AVSS RESET SCLK SDATA SEN GAIN2 SDOUT AVSS PDN GAIN1 GAIN0 AVSS AVDD AVDDVBIASAVSS AVSS NC NC NC AVSS NC NC AVSSAVDDAVSS NC AVDD NC 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 Thermal Pad PGA5807 SBAS617B –MAY 2013–REVISED JUNE 2013 www.ti.com DIGITAL CHARACTERISTICS TypicalvaluesareatTA = +25°C and AVDD = 3.3V,unlessotherwisespecified.Minimum and maximum valuesarespecified acrossthefulltemperaturerangeofTMIN = –40°C toTMAX = +85°C. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT DIGITAL INPUTS/OUTPUTS VIH Logichighinputvoltage 2 V VIL Logiclowinputvoltage 0 V IIH Logichighinputcurrent 200 µA IIL Logiclowinputcurrent 200 µA C i Inputcapacitance 5 pF VOH Logichighoutputvoltage SDOUT pin AVDD V VOL Logiclowoutputvoltage SDOUT pin 0 V PIN CONFIGURATION RGC PACKAGE QFN-64 (TOP VIEW)

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www.ti.com SBAS617B –MAY 2013–REVISED JUNE 2013 Table1.PIN FUNCTIONS NAME NO. FUNCTION DESCRIPTION AVDD 17,28,31,49,62-64 Supply Analogsupplypin,3.3V AVSS 19,20,24,27,29,50,54,61 Ground Analogground When RESET ishigh,thispinisused toprogramthePGA gain.GAIN0 51 Digitalinput RefertoTable2 formore details.Note:Use 3.3-Vlogic. When RESET ishigh,thispinisused toprogramthePGA gain.GAIN1 52 Digitalinput RefertoTable2 formore details.Note:Use 3.3-Vlogic. When RESET ishigh,thispinisused toprogramthePGA gain.GAIN2 56 Digitalinput RefertoTable2 formore details.Note:Use 3.3-Vlogic. INM1 to Complimentaryanaloginputsforchannels1 to8.2,4,6,8,10,12,14,16 InputINM8 The dc inputcommon-mode can be 2.1V ± 200 mV. Analoginputsforchannels1 to8.INP1 toINP8 1,3,5,7,9,11,13,15 Input The dc inputcommon-mode can be 2.1V ± 200 mV. NC 21-23,25,26,30,32 — Unused pins;do notconnect OUTM1 to 33,35,37,39,41,43,45,47 Output Complimentaryoutputpinswitha 0.95-Vcommon-mode voltageOUTM8 OUTP1 to 34,36,38,40,42,44,46,48 Output Outputpinswitha 0.95-Vcommon-mode voltageOUTP8 Partialpower-down controlpinfortheentiredevicewithan internal20-kΩPDN 53 Digitalinput pull-downresistor;activehigh.Note:Use 3.3-Vlogic. RESET 60 Digitalinput Logichardwareresetpin.Note:Use 3.3-Vlogic. Serialinterfaceclockpinwithan internal20-kΩ pull-downresistor.Note:UseSCLK 59 Digitalinput 3.3-Vlogic. Serialinterfacedatainputwithan internal20-kΩ pull-downresistor.When RESET ishigh,thecornerfrequencyfortheantialiasfiltercan beSDATA 58 Digitalinput programmed toa lowerfrequency(60MHz) by settingthispinhigh.Note: Use 3.3-Vlogic. SDOUT 55 Digitaloutput Serialinterfacereadoutpin Serialinterfaceenabledforchannels1 to8 withan internal20-kΩ pull-upSEN 57 Digitalinput resistor;activelow.Note:Use 3.3-Vlogic. VBIAS 18 Decap Biasvoltage;bypasstogroundwitha 1-μF capacitororgreater Table2.PGA Gain Control GAIN[2:0] PGA_GAIN (dB) 000 18 001 15 010 12 011 9 100 6 101 3 110 0 Copyright© 2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 5 ProductFolderLinks:PGA5807

(1 of 8 Channels) SPI Logic LNA (12-dB Fixed) SPI IN Input PGA (0 dB to 18 dB) Antialias Low-Pass Filter GAIN[2:0] Output SDATA PGA5807 SBAS617B –MAY 2013–REVISED JUNE 2013 www.ti.com FUNCTIONAL BLOCK DIAGRAM

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Frequency (Hz) Differential Impedance Magnitude (Ω ) G005 500 1000 1500 2000 2500 -40 -35 -30 -25 -20 -15 -10 -5 0 5 10 15 20 25 30 35 40 Number of Occurrences Output (mV) C004 0 1 2 3 4 5 6 GAIN[2:0] Gain (dB) −40 °C +25 °C +80 °C G001 500 1000 1500 2000 2500 3000 3500 29.1 29.2 29.3 29.4 29.5 29.6 29.7 29.8 29.9 30.1 30.2 30.3 30.4 30.5 30.6 30.7 30.8 30.9 Number of Occurrences Gain (dB) C002 PGA5807 www.ti.com SBAS617B –MAY 2013–REVISED JUNE 2013 TYPICAL CHARACTERISTICS AtTA = +25°C, AVDD = 3.3V,inputdc-coupledwith2.1-Vinputcommon-mode, LNA gain= 12 dB,PGA gain= 18 dB,total channelgain= 30 dB,GAIN[2:0]= 000,fIN = 5 MHz, defaultLPF filtercorner,and VOUT = –1 dBFS, unlessotherwisenoted. Figure1.GAIN vs GAIN[2:0]ACROSS TEMPERATURE Figure2.GAIN-MATCHING HISTOGRAM (Gain= 30 dB) Figure3.OUTPUT OFFSET HISTOGRAM Figure4.INPUT IMPEDANCE MAGNITUDE (Gain= 30 dB) Copyright© 2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 7 ProductFolderLinks:PGA5807

Gain (dB) Input Referred Noise (nVHz) Default setting Low BW setting G008 1 6 11 16 21 26 30 Frequency (MHz) Noise (nV Hz) G009 −100 −90 −80 −70 −60 −50 −40 −30 −20 −10 5M 25M 45M 65M 85M 100M Frequency (Hz) Differential Impedance Phase (Degree) G006 1M 10M 100M 300M Frequency (Hz) Gain (dB) Default Low BW G007 PGA5807 SBAS617B –MAY 2013–REVISED JUNE 2013 www.ti.com TYPICAL CHARACTERISTICS (continued) AtTA = +25°C, AVDD = 3.3V,inputdc-coupledwith2.1-Vinputcommon-mode, LNA gain= 12 dB,PGA gain= 18 dB,total channelgain= 30 dB,GAIN[2:0]= 000,fIN = 5 MHz, defaultLPF filtercorner,and VOUT = –1 dBFS, unlessotherwisenoted. Figure5.INPUT IMPEDANCE PHASE Figure6.LOW-PASS FILTER RESPONSE Figure7.INPUT-REFERRED NOISE vs GAIN Figure8.INPUT-REFERRED NOISE vs FREQUENCY (Gain= 30 dB)

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−80 −78 −76 −74 −72 −70 −68 −66 −64 −62 −60 2 6 10 14 18 22 25 Frequency (MHz) HD2 (dBc) Gain = 12 dB Gain = 30 dB G012 −80 −78 −76 −74 −72 −70 −68 −66 −64 −62 −60 12 15 18 21 24 27 30 Gain (dB) HD2 (dBc) fIN = 5 MHz fIN = 10 MHz fIN = 25 MHz G013 1 6 11 16 21 26 30 Frequency (MHz) Noise (nVHz) G010 12 15 18 21 24 27 30 Gain (dB) SNR (dBFS) Default Low BW G011 PGA5807 www.ti.com SBAS617B –MAY 2013–REVISED JUNE 2013 TYPICAL CHARACTERISTICS (continued) AtTA = +25°C, AVDD = 3.3V,inputdc-coupledwith2.1-Vinputcommon-mode, LNA gain= 12 dB,PGA gain= 18 dB,total channelgain= 30 dB,GAIN[2:0]= 000,fIN = 5 MHz, defaultLPF filtercorner,and VOUT = –1 dBFS, unlessotherwisenoted. Figure9.OUTPUT-REFERRED NOISE vs FREQUENCY (Gain Figure10.SIGNAL-TO-NOISE RATIO vs = 30 dB) GAIN ACROSS BANDWIDTH MODE Figure11.SECOND-HARMONIC DISTORTION vs Figure12.SECOND-HARMONIC DISTORTION vs GAIN FREQUENCY Copyright© 2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 9 ProductFolderLinks:PGA5807

−15 −10 −5 0 5 10 15 20 25 30 −0.3 −0.2 −0.1 0.1 0.2 0.3 −1.2 −0.8 −0.4 0.4 0.8 1.2 Time (ns) Differential Input Voltage (V) Differential Output Voltage (V) Input Output G016 −15 −10 −5 0 5 10 15 20 25 30 −40m −30m −20m −10m 10m 20m 30m 40m −1.2 −0.9 −0.6 −0.3 0.3 0.6 0.9 1.2 Time (ns) Differential Input Voltage (V) Differential Output Voltage (V) Input Output G017 −70 −65 −60 −55 −50 −45 −40 2 6 10 14 18 22 25 Frequency (MHz) HD3 (dBc) Gain = 12 dB Gain = 30 dB G014 −70 −66 −62 −58 −54 −50 −46 −42 −40 12 15 18 21 24 27 30 Gain (dB) HD3 (dBc) fIN = 5 MHz fIN = 10 MHz fIN = 25 MHz G015 PGA5807 SBAS617B –MAY 2013–REVISED JUNE 2013 www.ti.com TYPICAL CHARACTERISTICS (continued) AtTA = +25°C, AVDD = 3.3V,inputdc-coupledwith2.1-Vinputcommon-mode, LNA gain= 12 dB,PGA gain= 18 dB,total channelgain= 30 dB,GAIN[2:0]= 000,fIN = 5 MHz, defaultLPF filtercorner,and VOUT = –1 dBFS, unlessotherwisenoted. Figure13.THIRD-HARMONIC DISTORTION vs FREQUENCY Figure14.THIRD-HARMONIC DISTORTION vs GAIN Figure15.DIFFERENTIAL OUTPUT RESPONSE FOR AN Figure16.DIFFERENTIAL OUTPUT RESPONSE FOR AN INPUT STEP (12-dBTotalChannel Gain) INPUT STEP (30-dBTotalChannel Gain)

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−90 −80 −70 −60 −50 −40 −30 1k 10k 100k 1M Frequency (Hz) PSRR (dB) Gain = 30 dB Gain = 12 dB G018 PGA5807 www.ti.com SBAS617B –MAY 2013–REVISED JUNE 2013 TYPICAL CHARACTERISTICS (continued) AtTA = +25°C, AVDD = 3.3V,inputdc-coupledwith2.1-Vinputcommon-mode, LNA gain= 12 dB,PGA gain= 18 dB,total channelgain= 30 dB,GAIN[2:0]= 000,fIN = 5 MHz, defaultLPF filtercorner,and VOUT = –1 dBFS, unlessotherwisenoted. Figure17.POWER-SUPPLY REJECTION RATIO (100-mVPP Supply Noise withDifferentFrequencies) Copyright© 2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 11 ProductFolderLinks:PGA5807

tSEN_SU tSEN_HO RESET SCLK SEN Data Latched On SCLK Rising Edge SDATA A7 A6 A5 A4 A3 A2 A1 A0 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D 1 D0 tSCLK tDSU tDH tSCLK_H tSCLK_L PGA5807 SBAS617B –MAY 2013–REVISED JUNE 2013 www.ti.com SERIAL REGISTER TIMING SERIAL REGISTER WRITE DESCRIPTION Programming differentmodes can be accomplishedthroughthe serialinterfaceformed by the SEN (serial interfaceenable),SCLK (serialinterfaceclock),SDATA (serialinterfacedata),and RESET pins.Each ofthese pinshas a 20-kΩ pull-downresistortoGND. Seriallyshiftingbitsintothedeviceisenabledwhen SEN islow. SDATA serialdataarelatchedateverySCLK risingedge when SEN isactive(low).Serialdataareloadedinto theregisteratevery24thSCLK risingedge when SEN islow.Iftheword lengthexceeds a multipleof24 bits, theexcessbitsareignored.Data can be loadedinmultiplesof24-bitwords withina singleactiveSEN pulse(an internalcountercountsgroupsof24 clocksaftertheSEN fallingedge).The interfacecan functionwithSCLK frequenciesfrom20 MHz down tolow speeds (ofa few Hertz)and even witha non-50% dutycycleSCLK. Data aredividedintotwo main portionstoloadon theaddressedregister:a registeraddress(eightbits)and theactual data (16 bits).When writingto a registerwithunused bits,thesebitsshouldbe setto '0'.Figure18 shows a timingdiagramofthewriteoperation.Table3 liststheserialinterfacetimingcharacteristics. Figure18. SerialInterfaceTiming Diagram Table3.SerialInterfaceTiming Characteristics(1) PARAMETER MIN TYP MAX UNIT tSCLK SCLK period 50 ns tSCLK_H SCLK hightime 20 ns tSCLK_L SCLK lowtime 20 ns tDSU Data setuptime 5 ns tDHO Data holdtime 5 ns tSEN_SU SEN fallingedge toSCLK risingedge 8 ns tSEN_HO Time between lastSCLK risingedge toSEN risingedge 8 ns tOUT_DV (2) DelayfromSCLK fallingedge toSDOUT valid 12 20 28 ns (1) Minimum valuesareacrossthefulltemperaturerangeofTMIN = –40°C toTMAX = +85°C and AVDD = 3.3V. (2) See Figure19.

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SDOUT D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 tOUT_DV SDATA A7 A6 A5 A4 A3 A2 A1 A0 X X X X X X X X X X X X X X X X PGA5807 www.ti.com SBAS617B –MAY 2013–REVISED JUNE 2013 REGISTER READOUT The deviceincludesan optionwhere thecontentsoftheinternalregisterscan be read back.Thisreadoutmay be usefulas a diagnostictesttoverifytheserialinterfacecommunicationbetween theexternalcontrollerand the AFE. First,theREGISTER READOUT ENABLE bit(bit1,register00h)must be setto'1'.Then,initiatea serial interfacecyclespecifyingthe registeraddress (A[7:0])to be read.The data bitsare don’t care. The device outputsthe contents(D[15:0])of the selectedregisteron the SDOUT pin.SDOUT has a typical20-ns delay (tOUT_DV )fromtheSCLK fallingedge.For a lowerspeed SCLK, SDOUT can be latchedon theSCLK risingedge. For a higherspeed SCLK (forexample,withan SCLK periodlessthan60 ns),latchingSDOUT atthenextSCLK fallingedge ispreferable.Figure19 shows the read operationtimingdiagram (timingspecificationsfollowthe same informationprovidedinTable3).Inreadoutmode, REGISTER READOUT ENABLE can stillbe accessed throughSDATA, SCLK, and SEN. To enableserialregisterwrites,settheREGISTER READOUT ENABLE bit back to'0'. Figure19. SerialInterfaceRegisterRead Timing Diagram Copyright© 2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 13 ProductFolderLinks:PGA5807

SBAS617B –MAY 2013–REVISED JUNE 2013 www.ti.com REGISTER MAP A resetprocessisrequiredatthedeviceinitializationstage.Initializationcan be accomplishedinone oftwo ways: 1. Througha hardwarereset,by applyinga positivepulseon theRESET pin,or 2. Through a softwarereset(usingthe serialinterface),by settingthe SW_RESET bithigh.Settingthisbitinitializesthe internalregistersto the respectivedefaultvalues(all'0's)and thenself-resetstheSW_RESET bitlow.Inthiscase,theRESET pincan remainlow(inactive). Afterreset,allPGA registersaresetto‘0’(default).Duringregisterprogramming,allreservedorunlistedregisterbitsmust be setto‘0’.Registersettings aremaintainedwhen thedeviceisineitherpartialorcompletepower-down mode. Table4 liststhePGA registermap. Table4.PGA RegisterMap REGISTER DECIMAL BIT BIT BIT BIT (Hex) VALUE Bit15 BIT 14 13 12 11 10 BIT 9 BIT 8 BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 REGISTER 00 0 X (1) X X X X X X X X X X X X X READOUT SW_RESET ENABLE (2) COMPLETE PARTIAL35 53 X X X X X X X X X X X X X XPDN PDN LOW _3B 59 X X X X X X X X PGA_GAIN X X X XFILTER_BW (1) X = don'tcare. (2) Shaded cellsindicateused bits.

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www.ti.com SBAS617B –MAY 2013–REVISED JUNE 2013 RegisterDescriptions Table5.Register00h 15 14 13 12 11 10 9 8 X X X X X X X X 7 6 5 4 3 2 1 0 REGISTER X X X X X X READOUT SW_RESET ENABLE Bits15:2 Don'tcare Default= 0. Bit1 REGISTER READOUT ENABLE 0 = Readout disabled(default) 1 = RegisterreadoutenabledatSDOUT pin Bit0 SW_RESET 0 = Normal operation(default) 1 = Resetsthedeviceand self-clearsthebitto'0' Table6.Register35h 15 14 13 12 11 10 9 8 COMPLETE PARTIAL PDN X X X X X XPDN 7 6 5 4 3 2 1 0 X X X X X X X X Bit15 COMPLETE PDN Bit14 PARTIAL PDN 0 = Normal operation(default) 1 = LNA and PGA powered down Bits13:0 Don'tcare Default= 0. Copyright© 2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 15 ProductFolderLinks:PGA5807

SBAS617B –MAY 2013–REVISED JUNE 2013 www.ti.com Table7.Register3Bh 15 14 13 12 11 10 9 8 X X X X X X X X 7 6 5 4 3 2 1 0 LOW_FILTER_ PGA_GAIN X X X XBW Bits15:8 Don'tcare Default= 0. Bit7 LOW_FILTER_BW 0 = 75-MHz bandwidth(default) 1 = 60-MHz bandwidth Bits6:4 PGA_GAIN 000 = 18-dB PGA gain(default) 001 = 15-dB PGA gain 010 = 12-dB PGA gain 011 = 9-dB PGA gain 100 = 6-dB PGA gain 101 = 3-dB PGA gain 110 = 0-dB PGA gain Bits3:0 Don'tcare Default= 0.

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APPLICATION INFORMATION

The PGA5807 isa programmablegainamplifier(PGA) forapplicationswithinputfrequenciesup to25 MHz. The deviceincludesa low-noiseamplifier(LNA) witha fixedgain,followedby a PGA and an antialiasingfilterto reduce noise.The LNA isa fully-differentialamplifierwitha 12-dB fixedgain and can supporta 500-mV PP maximum lineardifferentialinputswing.The PGA isimplementedas an attenuatorfollowedby a fixed-gain amplifierwith18-dB gain.The attenuatorcan provideattenuationfrom 0 dB to –18 dB in 3-dB steps.The attenuatorcan be controlledby theGAIN[2:0]pinsorby usingregister3Bh (bits6 to4).The antialiasingfilteris combined withthe fixed-gainamplifier.The filterhas one activepole and a passivepole fora combined bandwidthof75 MHz. For low-frequencyapplications,bandwidthcan be reducedto60 MHz where betternoise can be achieved.The devicecan be programmed inthismode eitherby usingtheSDATA pinwhileRESET is highorby usingbit7 ofregister3Bh.Thisdevicecan directlydriveADCs such as theADS5296 . Low-Noise Amplifier(LNA) In most data-acquisitionsystems,an LNA isrequiredat the front-endto obtaingood noiseperformance.The PGA5807 has a fully-differentialLNA witha 12-dB fixedgain.The LNA input-referrednoiseis1.9nV/√Hz, and supportsa differential500-mV PP inputswing.The LNA inputcan be appliedeitherdirectlyor throughan ac- couplingcapacitor.Internally,theLNA inputisconnectedtoa 2.1-Vcommon-mode voltageviaa largeresistor(8 kΩ).For directinputcoupling,theLNA supportsan inputcommon-mode range from 1.9V to2.3V. The LNA inputcircuitsareshown inFigure20. Figure20. INP and INM EquivalentCircuitsofLNA Inputs Copyright© 2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 17 ProductFolderLinks:PGA5807

SBAS617B –MAY 2013–REVISED JUNE 2013 www.ti.com Programmable Gain Amplifier(PGA) and Filter The LNA outputistransmittedtoa PGA witha programmablegainfrom0 dB to18 dB in3-dB steps.Thisgain can eitherbe controlledthrougha serialinterfaceor throughpins,as explainedin the SerialRegisterWrite Descriptionsection.The PGA isimplementedas a programmableattenuatorand as a fixed-gainamplifierwithan 18-dB gain.Thisarchitecturehelpsachievethesame bandwidthacrossdifferentgainsettings.The attenuator providesprogrammableattenuationfrom0 dB to18 dB. The attenuatorarchitectureisshown in Figure21. There are sixshunt resistorsthatcan be connectedor disconnectedto achieveprogrammable attenuation.The network provides0-dB attenuationwhen no shunt resistorsareconnected.When thefirstshuntresistor(RS1)isturnedon,an attenuationof3 dB isobtained.For achieving6-dB attenuation,bothRS 1 and RS 2 areturnedon.Similarly,by turningon additionalresistors,greater attenuationcan be achieved;by turningon allresistors,an effective18-dB attenuationisachieved. Figure21. Programmable Attenuator

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INX_p INX_n OUTX_p OUTX_n OUTP OUTM R F R F gm V-to-I Converter I-to-V Converter C F C F PGA5807 www.ti.com SBAS617B –MAY 2013–REVISED JUNE 2013 The attenuatorisfollowedby a 18-dB fixed-gainamplifier.The amplifierisimplementedas a voltage-to-current (V-to-I)converterfollowedby a current-to-voltage(I-to-V)converter.The I-to-Vbandwidthislimitedso thatit functionsas an LPF and isfollowedby a passivefilter,as shown inFigure22.Both theactiveand passivefilters providean antialiasingfilteraction,whichhelpsreducenoisewhen thePGA outputissampled by an ADC. The architectureofthepassivefilterisselectedtoreducetheglitchesthatcan occurwhen thePGA5807 outputis sampled by an ADC. For example, the PGA5807 can be directlyconnected to ADC devices(such as the ADS5295 orADS5296 )withoutany externalcomponents between theADC and PGA5807. Figure23 shows an example ofthePGA5807 connecteddirectlytotheADS5296. Figure22. AntialiasFilter Figure23. PGA Connected toan ADC DEVICE CONFIGURATION USING SERIAL INTERFACE OR PARALLEL PINS Differentdevicemodes (suchas channelgainand bandwidth)can be programmed by eitherusingthe serial interfaceorexternalpins.The devicecan be configuredviatheserialinterfaceonlywhen thedeviceRESET pin ispulsedand remainslow.Inthisconfiguration,devicegaincan be programmed throughregister3Bh (bits6 to 4)and bandwidthcan be programmed by register3Bh (bit7).When theRESET pinisconnectedto3.3V oris pulledhigh,theserialinterfaceisunabletocontrolthedevice.Inthisconfiguration,theGAIN[2:0]pinscan be used tocontrolgainand theSDATA pincan be used tocontrolbandwidth. Copyright© 2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 19 ProductFolderLinks:PGA5807

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REVISION HISTORY

NOTE: Page numbers forpreviousrevisionsmay differfrompage numbers inthecurrentversion. Changes from RevisionA (June 2013)toRevisionB Page Changes from Original(May 2013)toRevisionA Page

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www.ti.com 14-Jun-2013 Addendum-Page 1 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3) Op Temp (°C) Device Marking (4/5) Samples PGA5807RGCR ACTIVE VQFN RGC 64 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR -40 to 85 PGA5807 PGA5807RGCT ACTIVE VQFN RGC 64 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR -40 to 85 PGA5807 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

*All dimensions are nominal Device Package Type Package Drawing Pins SPQ Reel Diameter (mm) Reel Width W1 (mm) (mm) (mm) (mm) (mm) W (mm) Pin1 Quadrant PACKAGE MATERIALS INFORMATION www.ti.com 14-Jun-2013 Pack Materials-Page 1

*All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) PGA5807RGCR VQFN RGC 64 2000 336.6 336.6 28.6 PGA5807RGCT VQFN RGC 64 250 336.6 336.6 28.6 PACKAGE MATERIALS INFORMATION www.ti.com 14-Jun-2013 Pack Materials-Page 2

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