PGA431K

PGA4311 BURR-BROWN | Alldatasheet

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Technical content

SBOS230A – MARCH 2002 – REVISED JUNE 2002 /C0052/C0262/C0067/C0104/C0097/C0110/C0110/C0101/C0108 /C0065/C0117/C0100/C0105/C0111 /C0086/C0111/C0108/C0117/C0109/C0101 /C0067/C0111/C0110/C0116/C0114/C0111/C0108 /C0080/C0071/C0065/C0052/C0051/C0049/C0049

FEATURES

/C0068DIGITALLY-CONTROLLED ANALOG VOLUME CONTROL: Four Independent Audio Channels Serial Control Interface Zero Crossing Detection Mute Function /C0068WIDE GAIN AND ATTENUATION RANGE: +31.5dB to –95.5dB with 0.5dB Steps /C0068LOW NOISE AND DISTORTION: 120dB Dynamic Range 0.0004% THD+N at 1kHz (U–Grade) 0.0002% THD+N at 1kHz (A–Grade) /C0068NOISE-FREE LEVEL TRANSITIONS /C0068LOW INTERCHANNEL CROSSTALK: –130dBFS /C0068POWER SUPPLIES: ±5V Analog, +5V Digital /C0068AVAILABLE IN AN SOP-28 PACKAGE

APPLICATIONS

/C0068AUDIO AMPLIFIERS /C0068MIXING CONSOLES /C0068MULTI–TRACK RECORDERS /C0068BROADCAST STUDIO EQUIPMENT /C0068MUSICAL INSTRUMENTS /C0068EFFECTS PROCESSORS /C0068A/V RECEIVERS /C0068CAR AUDIO SYSTEMS

DESCRIPTION

The PGA4311 is a high–performance, 4-channel audio volume control designed for professional and high-end consumer audio systems. Using high performance operational amplifier stages internal to the PGA4311 yields low noise and distortion, while providing the capability to drive 600Ω loads directly without buffering. The 3-wire serial control interface allows for connection to a wide variety of host controllers, in addition to support for daisy-chaining of multiple PGA4311 devices. www.ti.com Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Copyright  2002, Texas Instruments Incorporated/C0080/C0082/C0079/C0068/C0085/C0067/C0084/C0073/C0079/C0078 /C0068/C0065/C0084/C0065 /C0105/C0110/C0102/C0111/C0114/C0109/C0097/C0116/C0105/C0111/C0110 /C0105/C0115 /C0099/C0117/C0114/C0114/C0101/C0110/C0116 /C0097/C0115 /C0111/C0102 /C0112/C0117/C0098/C0108/C0105/C0099/C0097/C0116/C0105/C0111/C0110 /C0100/C0097/C0116/C0101/C0046 /C0080/C0114/C0111/C0100/C0117/C0099/C0116/C0115 /C0099/C0111/C0110/C0102/C0111/C0114/C0109 /C0116/C0111 /C0115/C0112/C0101/C0099/C0105/C0102/C0105/C0099/C0097/C0116/C0105/C0111/C0110/C0115 /C0112/C0101/C0114 /C0116/C0104/C0101 /C0116/C0101/C0114/C0109/C0115 /C0111/C0102 /C0084/C0101/C0120/C0097/C0115 /C0073/C0110/C0115/C0116/C0114/C0117/C0109/C0101/C0110/C0116/C0115 /C0115/C0116/C0097/C0110/C0100/C0097/C0114/C0100 /C0119/C0097/C0114/C0114/C0097/C0110/C0116/C0121/C0046 /C0080/C0114/C0111/C0100/C0117/C0099/C0116/C0105/C0111/C0110 /C0112/C0114/C0111/C0099/C0101/C0115/C0115/C0105/C0110/C0103 /C0100/C0111/C0101/C0115 /C0110/C0111/C0116 /C0110/C0101/C0099/C0101/C0115/C0115/C0097/C0114/C0105/C0108/C0121 /C0105/C0110/C0099/C0108/C0117/C0100/C0101 /C0116/C0101/C0115/C0116/C0105/C0110/C0103 /C0111/C0102 /C0097/C0108/C0108 /C0112/C0097/C0114/C0097/C0109/C0101/C0116/C0101/C0114/C0115/C0046 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

/C0080/C0071/C0065/C0052/C0051/C0049/C0049 SBOS230A – MARCH 2002 – REVISED JUNE 2002 www.ti.com ABSOLUTE MAXIMUM RATINGS (1) (1)Stresses above these ratings may cause permanent damage. Exposure to absolute maximum conditions for extended periods may degrade device reliability. ELECTROSTATIC DISCHARGE SENSITIVITY This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to ob- serve proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. PACKAGE/ORDERING INFORMATION PRODUCT PACKAGE –LEAD PACKAGE DESIGNATOR (1) OPERATING TEMPERATURE RANGE PACKAGE MARKING ORDERING NUMBER TRANSPORT MEDIA, QUANTITY PGA4311 (U Grade) SOP 28 DW 40°Ct o+ 8 5°C PGA4311U PGA4311U Rails PGA4311 (U–Grade) SOP –28 DW –40°C to +85°C PGA4311U PGA4311U/1K Tape and Reel, 1000 PGA4311 (A Grade) SOP 28 DW 40°Ct o+ 8 5°C PGA4311UA PGA4311UA Rails PGA4311 (A–Grade) SOP –28 DW –40°C to +85°C PGA4311UA PGA4311UA/1K Tape and Reel, 1000 (1)For the most current specifications and package information, refer to our web site at www. ti.com.

ELECTRICAL CHARACTERISTICS

At TA = +25°C, VA+ = +5V, VA– = –5V, VD + = +5V, RL = 100kΩ , CL = 20pF, BW measure = 10Hz to 20kHz, unless otherwise noted. PARAMETER CONDITIONS PGA4311U (U –Grade) PGA4311UA (A –Grade) UNITSPARAMETER CONDITIONS MIN TYP MAX MIN TYP MAX UNITS DC CHARACTERISTICS Step Size 0.5 0.5 dB Gain Error Gain Setting = 31.5dB ±0.05 ±0.05 dB Gain Matching ±0.05 ±0.05 dB Input Resistance 10 10 kΩ Input Capacitance 3 3 pF AC CHARACTERISTICS THD+N VIN = 2Vrms, f = 1kHz 0.0004 0.001 0.0002 0.0004 % Dynamic Range VIN = AGND, Gain = 0dB 116 120 116 120 dB Voltage Range, Output (VA–) + 1.25 (VA+) – 1.25 (VA–) + 1.25 (VA+) – 1.25 V Voltage Range, Input (without clipping) 2.5 2.5 Vrms Output Noise VIN = AGND, Gain = 0dB 2.5 4 2.5 4 µVrms Interchannel Crosstalk f = 1kHz –130 –130 dBFS OUTPUT BUFFER Offset Voltage VIN = AGND, Gain = 0dB 0.25 0.5 0.25 0.5 mV Load Capacitance Stability 100 100 pF Short–Circuit Current 50 50 mA Unity–Gain Bandwidth, Small Signal 10 10 MHz

/C0080/C0071/C0065/C0052/C0051/C0049/C0049 SBOS230A – MARCH 2002 – REVISED JUNE 2002 www.ti.com ELECTRICAL CHARACTERISTICS (Cont.) At TA = +25°C, VA+ = +5V, VA– = –5V, VD + = +5V, RL = 100kΩ , CL = 20pF, BW measure = 10Hz to 20kHz, unless otherwise noted. PARAMETER CONDITIONS PGA4311U (U –Grade) PGA4311UA (A –Grade) UNITSPARAMETER CONDITIONS MIN TYP MAX MIN TYP MAX UNITS DIGITAL CHARACTERISTICS High–Level Input Voltage, VIH +2.0 VD + +2.0 VD + V Low –Level Input Voltage, VIL –0.3 0.8 –0.3 0.8 V High–Level Output Voltage, VOH IO = 200µA (VA+) – 1.0 (VD +) – 1.0 V Low –Level Output Voltage, VOL IO = –3.2mA 0.4 0.4 V Input Leakage Current 1 10 1 10 µA SWITCHING CHARACTERISTICS Serial Clock (SCLK) Frequency fSCLK 0 6.25 0 6.25 MHz Serial Clock (SCLK) Pulse Width LOW tPH 80 80 ns Serial Clock (SCLK) Pulse Width HIGH tPL 80 80 ns MUTE Pulse Width LOW tMI 2.0 2.0 ms Input Timing SDI Setup Time tSDS 20 20 ns SDI Hold Time tSDH 20 20 ns CS Falling to SCLK Rising tCSCR 90 90 ns SCLK Falling to CS Rising tCFCS 35 35 ns Output Timing CS LOW to SDO Active tCSO 35 35 ns SCLK Falling to SDO Data Valid tCFDO 60 60 ns CS HIGH to SDO High Impedance tCSZ 100 100 ns POWER SUPPLY Operating Voltage Quiescent Current IA+ VA+ = +5V 17 22 17 22 mA IA– VA– = –5V 19 24 19 24 mA ID + VD + = +5V 0.5 1.0 0.5 1.0 mA Power–Supply Rejection Ratio PSRR (250Hz) 100 100 dB TEMPERATURE RANGE Operating Range –40 +85 –40 +85 °C Storage Range –65 +150 –65 +150 °C

/C0080/C0071/C0065/C0052/C0051/C0049/C0049 SBOS230A – MARCH 2002 – REVISED JUNE 2002 www.ti.com PIN CONFIGURATION Top View SO PIN ASSIGNMENTS PIN NAME FUNCTION

1 MUTE Mute Control Input (Active LOW)

2 AGND_1 Analog Ground, Channel 1

3 AIN_1 Analog Input, Channel 1

4 AGND_1 Analog Ground, Channel 1

5 AOUT _1 Analog Output, Channel 1

6 VA– Analog Power Supply, –5V

7 VA+ Analog Power Supply, +5V

8 AOUT _3 Analog Output, Channel 3

9 AGND_3 Analog Ground, Channel 3

10 AIN_3 Analog Input, Channel 3

11 AGND_3 Analog Ground, Channel 3

12 VD + Digital Power Supply, +5V

13 SDI Serial Data Input

14 CS Chip Select Input

15 SCLK Serial Clock Input

16 SDO Serial Data Output

17 DGND Digital Ground

18 AGND_4 Analog Ground, Channel 4

19 AIN_4 Analog Input, Channel 4

20 AGND_4 Analog Ground, Channel 4

21 AOUT _4 Analog Output, Channel 4

22 VA+ Analog Power Supply, +5V

23 VA– Analog Power Supply, –5V

24 AOUT _2 Analog Output, Channel 2

25 AGND_2 Analog Ground, Channel 2

26 AIN_2 Analog Input, Channel 2

27 AGND_2 Analog Ground, Channel 2

28 ZCEN Zero Crossing Enable (Active HIGH)

/C0080/C0071/C0065/C0052/C0051/C0049/C0049 SBOS230A – MARCH 2002 – REVISED JUNE 2002 www.ti.com TYPICAL CHARACTERISTICS At TA = +25°C, VA+ = +5V, VA– = –5V, VD + = +5V, RL = 100kΩ , CL = 20pF, BW measure = 10Hz to 20kHz, unless otherwise noted. (NOTE: All plots taken with PGA4311 A–Grade.)

/C0080/C0071/C0065/C0052/C0051/C0049/C0049 SBOS230A – MARCH 2002 – REVISED JUNE 2002 www.ti.com TYPICAL CHARACTERISTICS (Cont.) At TA = +25°C, VA+ = +5V, VA– = –5V, VD + = +5V, RL = 100kΩ , CL = 20pF, BW measure = 10Hz to 20kHz, unless otherwise noted. (NOTE: All plots taken with PGA4311 A–Grade.) GENERAL DESCRIPTION The PGA4311 is a four-channel audio volume control. It may be used in a wide array of professional and consumer audio equipment. The PGA4311 is fabricated in a sub-micron CMOS process. The heart of the PGA4311 is a resistor network, an analog switch array, and a high-performance op amp stage. The switches are used to select taps in the resistor network that, in turn, determine the gain of the amplifier stage. Switch selections are programmed using a serial control port. The serial port allows connection to a wide variety of host controllers. See Figure 1 for a functional block diagram of the PGA4311. POWER –UP STATE On power up, “power-up reset” is activated for about 100ms during which the circuit is in hardware MUTE state and all internal flip-flops are reset. At the end of this period, the offset calibration is initiated without any external signals. Once this has been completed, the gain byte value for all channels are set to 00 HEX , or the software MUTE condi- tion. The gain will remain at this setting until the host con- troller programs new settings for for each channel via the serial control port.

Figure 1. PGA4311 Block Diagram. power-supply voltage returns to greater than ±3.2V. The PGA4311 includes four independent channels. Each channel has a corresponding input and output pin. Typical Characteristics section of the datasheet.

Figure 3. Serial Interface Timing Requirements.

terface to control many PGA4311 devices. to allow enough SCLK cycles to load all devices. tion that can provide for noise-free level transitions. ing of the input signal, thus minimizing audible glitches. Figure 4. Daisy-Chaining Multiple PGA4311 Devices.

Figure 6. Typical PCB Layout Floor Plan.

/C0080/C0071/C0065/C0052/C0051/C0049/C0049 SBOS230A – MARCH 2002 – REVISED JUNE 2002 www.ti.com PACKAGE DRAWING

ORDERABLE DEVICE STATUS(1) PACKAGE TYPE PACKAGE DRAWING PINS PACKAGE QTY PGA4311U ACTIVE SOIC DW 28 28 PGA4311U/1K ACTIVE SOIC DW 28 1000 PGA4311U2 PREVIEW SOIC DW 28 1 PGA4311UA ACTIVE SOIC DW 28 28 PGA4311UA/1K ACTIVE SOIC DW 28 1000 PGA4311UA1 PREVIEW SOIC DW 28 1 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. PACKAGE OPTION ADDENDUM www.ti.com 17-May-2004

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