Sensor

PGA309AIPWRG4

Burr-Brown (TI)

Voltage Output PROFRAMMABLE SENSOR CONDITIONER

Manufacturer: Burr-Brown (TI)

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FEATURES

/C0068COMPLETE BRIDGE SENSOR CONDITIONER /C0068VOLTAGE OUTPUT: Ratiometric or Absolute /C0068DIGITAL CAL: No Potentiometers/Sensor Trims /C0068SENSOR ERROR COMPENSATION − Span, Offset, and Temperature Drifts /C0068LOW ERROR, TIME-STABLE /C0068SENSOR LINEARIZATION CIRCUITRY /C0068TEMPERATURE SENSE: Internal or External /C0068CALIBRATION LOOKUP TABLE LOGIC − Uses External EEPROM (SOT23-5) /C0068OVER/UNDER-SCALE LIMITING /C0068SENSOR FAULT DETECTION /C0068+2.7V TO +5.5V OPERATION /C0068−40°C to +125°C OPERATION /C0068SMALL TSSOP-16 PACKAGE

APPLICATIONS

/C0068BRIDGE SENSORS /C0068REMOTE 4-20mA TRANSMITTERS /C0068STRAIN, LOAD, AND WEIGH SCALES /C0068AUTOMOTIVE SENSORS EVALUATION TOOLS /C0068HARDWARE DESIGNER’S KIT (PGA309EVM) − Temperature Eval of PGA309 + Sensor − Full Programming of PGA309 − Sensor Compensation Analysis Tool

DESCRIPTION

The PGA309 is a programmable analog signal conditioner designed for bridge sensors. The analog signal path am- plifies the sensor signal and provides digital calibration for zero, span, zero drift, span drift, and sensor linearization errors with applied stress (pressure, strain, etc.). The cal- ibration is done via a One-Wire digital serial interface or through a Two-Wire industry-standard connection. The calibration parameters are stored in external nonvolatile memory (typically SOT23-5) to eliminate manual trimming and achieve long-term stability. The all-analog signal path contains a 2x2 input multiplex- er (mux), auto-zero programmable-gain instrumentation amplifier, linearization circuit, voltage reference, internal oscillator, control logic, and an output amplifier. Program- mable level shifting compensates for sensor DC offsets. The core of the PGA309 is the precision, low-drift, no 1/f noise Front-End PGA (Programmable Gain Amplifier). The overall gain of the Front-End PGA + Output Amplifier can be adjusted from 2.7V/V to 1152V/V. The polarity of the inputs can be switched through the input mux to ac- commodate sensors with unknown polarity output. The Fault Monitor circuit detects and signals sensor burnout, overload, and system fault conditions. For detailed application information, see the PGA309 User’s Guide (SBOU024), available for download at www.ti.com. All trademarks are the property of their respective owners. PGA309 SBOS292B − DECEMBER 2003 − REVISED JANUARY 2005 Voltage Output PROGRAMMABLE SENSOR CONDITIONER /C0080/C0082/C0079/C0068/C0085/C0067/C0084/C0073/C0079/C0078 /C0068/C0065/C0084/C0065 /C0105/C0110/C0102/C0111/C0114/C0109/C0097/C0116/C0105/C0111/C0110 /C0105/C0115 /C0099/C0117/C0114/C0114/C0101/C0110/C0116 /C0097/C0115 /C0111/C0102 /C0112/C0117/C0098/C0108/C0105/C0099/C0097/C0116/C0105/C0111/C0110 /C0100/C0097/C0116/C0101/C0046 /C0080/C0114/C0111/C0100/C0117/C0099/C0116/C0115 /C0099/C0111/C0110/C0102/C0111/C0114/C0109 /C0116/C0111 /C0115/C0112/C0101/C0099/C0105/C0102/C0105/C0099/C0097/C0116/C0105/C0111/C0110/C0115 /C0112/C0101/C0114 /C0116/C0104/C0101 /C0116/C0101/C0114/C0109/C0115 /C0111/C0102 /C0084/C0101/C0120/C0097/C0115 /C0073/C0110/C0115/C0116/C0114/C0117/C0109/C0101/C0110/C0116/C0115 /C0115/C0116/C0097/C0110/C0100/C0097/C0114/C0100 /C0119/C0097/C0114/C0114/C0097/C0110/C0116/C0121/C0046 /C0080/C0114/C0111/C0100/C0117/C0099/C0116/C0105/C0111/C0110 /C0112/C0114/C0111/C0099/C0101/C0115/C0115/C0105/C0110/C0103 /C0100/C0111/C0101/C0115 /C0110/C0111/C0116 /C0110/C0101/C0099/C0101/C0115/C0115/C0097/C0114/C0105/C0108/C0121 /C0105/C0110/C0099/C0108/C0117/C0100/C0101 /C0116/C0101/C0115/C0116/C0105/C0110/C0103 /C0111/C0102 /C0097/C0108/C0108 /C0112/C0097/C0114/C0097/C0109/C0101/C0116/C0101/C0114/C0115/C0046 www.ti.com Copyright  2003−2005, Texas Instruments Incorporated Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Analog Sensor Linearization Digital Temperature Compensation Analog Signal Conditioning Linear V OUT PGA309 Digital Cal VEXC VS 0 50 psi P Ext Temp Ext Temp Nonlinear Bridge Transducer Linearization Circuit Auto−Zero PGA Fault Monitor Int Temp Control Register Interface Circuitry EEPROM (SOT23−5) Ref T +125/C0095C −40/C0095C Over/Under Scale Limiter Lin DAC Temp ADC

/C0080/C0071/C0065/C0051/C0048/C0057 SBOS292B − DECEMBER 2003 − REVISED JANUARY 2005 www.ti.com PACKAGE/ORDERING INFORMATION (1) PRODUCT PACKAGE−LEAD PACKAGE DRAWING SPECIFIED TEMPERATURE RANGE PACKAGE MARKING ORDERING NUMBER TRANSPORT MEDIA, QUANTITY PGA309 TSSOP-16 PW −40°C to +125°C PGA309 PGA309AIPWR Tape and Reel, 2500 PGA309 TSSOP-16 PW −40°C to +125°C PGA309 PGA309AIPWT Tape and Reel, 250 (1)For the most current package and ordering information, see the Package Option Addendum located at the end of this data sheet, or see the TI website at www.ti.com. ABSOLUTE MAXIMUM RATINGS (1) Over operating free-air temperature range unless otherwise noted. (1)Stresses above these ratings may cause permanent damage. Exposure to absolute maximum conditions for extended periods may degrade device reliability. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those specified is not implied. (2)Input terminals are diode-clamped to the power-supply rails. Input signals that can swing more than 0.5V beyond the supply rails should be current limited to 10mA or less. This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.

/C0080/C0071/C0065/C0051/C0048/C0057 SBOS292B − DECEMBER 2003 − REVISED JANUARY 2005 www.ti.com

ELECTRICAL CHARACTERISTICS

BOLDFACE limits apply over the specified temperature range: TA = −40°C to +125°C TA = +25°C, VSA = VSD = +5V (VSA = VSUPPLY ANALOG , VSD = VSUPPLY DIGITAL; VSA must equal VSD ), GNDD = GNDA = 0, and VREF = REFIN/REFOUT = +5V, unless otherwise noted. PGA309 PARAMETER CONDITIONS MIN TYP MAX UNITS FRONT-END PGA + OUTPUT AMPLIFIER VOUT /VIN Differential Signal Gain Range(1) Fine Gain Adjust = 1 Front-End PGA Gains: 4, 8, 16, 23.27, 32, 42.67, 64, 128 Output Amplifier Gains: 2, 2.4, 3, 3.6, 4.5, 6, 9 8 to 1152 V/V Input Voltage Noise Density f = 1kHz 210 nV/√Hz VOUT Slew Rate 0.5 V/µs VOUT Settling Time (0.01%) VOUT /VIN Differential Gain = 8, RL = 5kΩ || 200pF 6 µs VOUT Settling Time (0.01%) VOUT /VIN Differential Gain = 191, RL = 5kΩ || 200pF 4.1 µs VOUT Nonlinearity 0.002 %FSR External Sensor Output Sensitivity VSA = VSD = VEXC = +5V 1 to 245 mV/V FRONT-END PGA Auto-Zero Internal Frequency 7 kHz Offset Voltage (RTI)(2) Coarse Offset Adjust Disabled ±3 ±50 µV vs Temperature /C00430.2 µV/°C vs Supply Voltage, VSA ±2 µV/V vs Common-Mode Voltage G F = Front-End PGA Gain 1500/GF 6000/GF µV/V Linear Input Voltage Range(3) 0.2 VSA −1.5 V Input Bias Current 0.1 1.5 nA Input Impedance: Differential 30 || 6 G Ω || pF Input Impedance: Common-Mode 50 || 20 G Ω || pF Input Voltage Noise 0.1Hz to 10Hz, GF = 128 4 µVPP PGA Gain Gain Range Steps 4, 8, 16, 23.27, 32, 42.67, 64, 128 4 to 128 V/V Initial Gain Error G F = 4 to 42 0.2 ±1 % G F = 64 0.25 ±1.2 % G F = 128 0.3 ±1.6 % vs Temperature 10 ppm/ °C Output Voltage Range 0.05 to VSA − 0.1 V Bandwidth Gain = 4 400 kHz Gain = 128 60 kHz COARSE OFFSET ADJUST (RTI OF FRONT-END PGA) Range ±(14)(VREF )(0.00085) ±56 ±59.5 ±64 mV vs Temperature 0.004 %/°C Resolution ±14 steps, 4-Bit + Sign 4 mV FINE OFFSET ADJUST (ZERO DAC) (RTO of the Front-End PGA)(2) Programming Range 0 VREF V Output Range 0.1 VSA −0.1 V Resolution 65,536 steps, 16-Bit DAC 73 µV Integral Nonlinearity 20 LSB Differential Nonlinearity 0.5 LSB Gain Error 0.1 % Gain Error Drift 10 ppm/°C Offset 5 mV Offset Drift 10 µV/°C OUTPUT FINE GAIN ADJUST (GAIN DAC) Range 0.33 to 1 V/V Resolution 65,536 steps, 16-Bit DAC 10 µV/V Integral Nonlinearity 20 LSB Differential Nonlinearity 0.5 LSB

/C0080/C0071/C0065/C0051/C0048/C0057 SBOS292B − DECEMBER 2003 − REVISED JANUARY 2005 www.ti.com ELECTRICAL CHARACTERISTICS (continued) BOLDFACE limits apply over the specified temperature range: TA = −40°C to +125°C TA = +25°C, VSA = VSD = +5V (VSA = VSUPPLY ANALOG , VSD = VSUPPLY DIGITAL; VSA must equal VSD ), GNDD = GNDA = 0, and VREF = REFIN/REFOUT = +5V, unless otherwise noted. PGA309 PARAMETER UNITSMAXTYPMINCONDITIONS OUTPUT AMPLIFIER Offset Voltage (RTI of Output Amplifier)(2) 3 mV vs Temperature 5 µV/°C vs Supply Voltage, VSA 30 µV/V Common-Mode Input Range 0 VSA −1.5 V Input Bias Current 100 pA Amplifier Internal Gain Gain Range Steps 2, 2.4, 3, 3.6, 4.5, 6, 9 2 to 9 V/V Initial Gain Error 2, 2.4, 3.6 0.25 ±1 % 4.5 0.3 ±1.2 % 6 0.4 ±1.5 % 9 0.6 ±2.0 % vs Temperature 2, 2.4, 3.6 5 ppm/ °C 4.5 5 ppm/ °C 6 15 ppm/ °C 9 30 ppm/ °C Output Voltage Range(4) R L = 10kΩ 0.1 4.9 V Open Loop Gain 115 dB Gain-Bandwidth Product 2 MHz Phase Margin Gain = 2, CL = 200pF 45 Degrees Output Resistance AC Small-Signal, Open-Loop, f = 1MHz, IO = 0 675 Ω OVER- AND UNDER-SCALE LIMITS (VREF = 4.096) Over-Scale Thresholds Ratio of VREF , Register 5—Bits D5, D4, D3 = ‘000’ 0.9708 Ratio of VREF , Register 5—Bits D5, D4, D3 = ‘001’ 0.9610 Ratio of VREF , Register 5—Bits D5, D4, D3 = ‘010’ 0.9394 Ratio of VREF , Register 5—Bits D5, D4, D3 = ‘011’ 0.9160 Ratio of VREF , Register 5—Bits D5, D4, D3 = ‘100’ 0.9102 Ratio of VREF , Register 5—Bits D5, D4, D3 = ‘101’ 0.7324 Ratio of VREF , Register 5—Bits D5, D4, D3 = ‘110’ 0.5528 Over-Scale Comparator Offset +6 +60 +114 mV Over-Scale Comparator Offset Drift +0.37 mV/°C Under-Scale Thresholds Ratio of VREF , Register 5—Bits D2, D1, D0 = ‘111’ 0.0605 Ratio of VREF , Register 5—Bits D2, D1, D0 = ‘110’ 0.0547 Ratio of VREF , Register 5—Bits D2, D1, D0 = ‘101’ 0.0507 Ratio of VREF , Register 5—Bits D2, D1, D0 = ‘100’ 0.0449 Ratio of VREF , Register 5—Bits D2, D1, D0 = ‘011’ 0.0391 Ratio of VREF , Register 5—Bits D2, D1, D0 = ‘010’ 0.0352 Ratio of VREF , Register 5—Bits D2, D1, D0 = ‘001’ 0.0293 Ratio of VREF , Register 5—Bits D2, D1, D0 = ‘000’ 0.0254 Under-Scale Comparator Offset −7 −50 +93 mV Under-Scale Comparator Offset Drift −0.15 mV/°C FAULT MONITOR CIRCUIT INP_HI, INN_HI Comparator Threshold See Note 5 VSA −1.2 or VEXC −0.1 V INP_LO, INN_LO Comparator Threshold 40 100 mV A1SAT_HI, A2SAT_HI Comparator Threshold VSA −0.12 V A1SAT_LO, A2SAT_LO Comparator Threshold VSA −0.12 V A3_VCM Comparator Threshold VSA −1.2 V Comparator Hysteresis 20 mV

/C0080/C0071/C0065/C0051/C0048/C0057 SBOS292B − DECEMBER 2003 − REVISED JANUARY 2005 www.ti.com ELECTRICAL CHARACTERISTICS (continued) BOLDFACE limits apply over the specified temperature range: TA = −40°C to +125°C TA = +25°C, VSA = VSD = +5V (VSA = VSUPPLY ANALOG , VSD = VSUPPLY DIGITAL; VSA must equal VSD ), GNDD = GNDA = 0, and VREF = REFIN/REFOUT = +5V, unless otherwise noted. PGA309 PARAMETER UNITSMAXTYPMINCONDITIONS INTERNAL VOLTAGE REFERENCE VREF1 Register 3, Bit D9 = 1 2.46 2.5 2.53 V VREF1 Drift vs Temperature +10 ppm/ °C VREF2 Register 3, Bit D9 = 0 4.0 4.096 4.14 V VREF2 Drift vs Temperature +10 ppm/ °C Input Current REFIN/REFOUT Internal VREF Disabled 100 µA Output Current REFIN/REFOUT VSA > 2.7V for VREF = 2.5V 1 mA VSA > 4.3V for VREF = 4.096V 1 mA TEMPERATURE SENSE CIRCUITRY (ADC) Internal Temperature Measurement Register 6, Bit D9 = 1 Accuracy ±2 °C Resolution 12-Bit + Sign, Two’s Complement Data Format ±0.0625 °C Temperature Measurement Range −55 +150 °C Conversion Rate R1, R0 = ‘11’, 12-Bit + Sign Resolution 24 ms TEMPERATURE ADC External Temperature Mode Temp PGA + Temp ADC Gain Range Steps G PGA = 1, 2, 4, 8 1 to 8 V/V Analog Input Voltage Range GND−0.2 VSA +0.2 V Temperature ADC Internal REF (2.048V) Register 6, Bit D8 = 1 Full-Scale Input Voltage (+Input) − (−Input) ±2.048/GPGA V Differential Input Impedance 2.8/GPGA M Ω Common-Mode Input Impedance G PGA = 1 3.5 M Ω G PGA = 2 3.5 M Ω G PGA = 4 1.8 M Ω G PGA = 8 0.9 M Ω Resolution R1, R0 = ‘00’, ADC2X = ‘0’, Conversion Time = 8ms 11 Bits + Sign R1, R0 = ‘01’, ADC2X = ‘0’, Conversion Time = 32ms 13 Bits + Sign R1, R0 = ‘10’, ADC2X = ‘0’, Conversion Time = 64ms 14 Bits + Sign R1, R0 = ‘11’, ADC2X = ‘0’, Conversion Time = 128ms 15 Bits + Sign Integral Nonlinearity 0.004 % Offset Error G PGA = 1 1.2 mV G PGA = 2 0.7 mV G PGA = 4 0.5 mV G PGA = 8 0.4 mV Offset Drift G PGA = 1 1.2 µV/°C G PGA = 2 0.6 µV/°C G PGA = 4 0.3 µV/°C G PGA = 8 0.3 µV/°C Offset vs VSA G PGA = 1 800 µV/V G PGA = 2 400 µV/V G PGA = 4 200 µV/V G PGA = 8 150 µV/V Gain Error 0.05 0.50 % Gain Error Drift 5 50 ppm/°C Noise All Gains < 1 LSB Gain vs VSA 80 ppm/V Common-Mode Rejection At DC and G PGA = 8 105 dB At DC and G PGA = 1 100 dB

/C0080/C0071/C0065/C0051/C0048/C0057 SBOS292B − DECEMBER 2003 − REVISED JANUARY 2005 www.ti.com ELECTRICAL CHARACTERISTICS (continued) BOLDFACE limits apply over the specified temperature range: TA = −40°C to +125°C TA = +25°C, VSA = VSD = +5V (VSA = VSUPPLY ANALOG , VSD = VSUPPLY DIGITAL; VSA must equal VSD ), GNDD = GNDA = 0, and VREF = REFIN/REFOUT = +5V, unless otherwise noted. PGA309 PARAMETER UNITSMAXTYPMINCONDITIONS TEMPERATURE ADC (CONTINUED) Temp ADC Ext. REF (VREFT = VREF, VEXC , or VSA) Register 6, Bit D8 = 0 Full-Scale Input Voltage (+Input) − (−Input) ±VREFT /GPGA V Differential Input Impedance 2.4/GPGA M Ω Common-Mode Input Impedance G PGA = 1 8 M Ω G PGA = 2 8 M Ω G PGA = 4 8 M Ω G PGA = 8 8 M Ω Resolution R1, R0 = ‘00’, ADC2X = ‘0’, Conversion Time = 6ms 11 Bits + Sign R1, R0 = ‘01’, ADC2X = ‘0’, Conversion Time = 24ms 13 Bits + Sign R1, R0 = ‘10’, ADC2X = ‘0’, Conversion Time = 50ms 14 Bits + Sign R1, R0 = ‘11’, ADC2X = ‘0’, Conversion Time = 100ms 15 Bits + Sign Integral Nonlinearity 0.01 % Offset Error G PGA = 1 2.5 mV G PGA = 2 1.25 mV G PGA = 4 0.7 mV G PGA = 8 0.3 mV Offset Drift G PGA = 1 1.5 µV/°C G PGA = 2 1.0 µV/°C G PGA = 4 0.7 µV/°C G PGA = 8 0.6 µV/°C Gain Error −0.2 % Gain Error Drift 2 ppm/°C Gain vs VSA 80 ppm/V Common-Mode Rejection At DC and G PGA = 8 100 dB At DC and G PGA = 1 85 dB External Temperature Current ExcitationITEMP Register 6, Bit D11 = 1 Current Excitation 5.8 7 8 µA Temperature Drift 5 nA/°C Voltage Compliance VSA −1.2 V LINEARIZATION ADJUST AND EXCITATION VOLTAGE (V EXC ) Range 0 Register 3, Bit D11 = 0 Linearization DAC Range With Respect to VFB −0.166 to +0.166 V/V Linearization DAC Resolution ±127 Steps, 7-Bit + Sign 1.307 mV/V VEXC Gain With Respect to VREF 0.83 V/V Gain Error Drift 25 ppm/°C Range 1 Register 3, Bit D11 = 1 Linearization DAC Range With Respect to VFB −0.124 to +0.124 V/V Linearization DAC Resolution ±127 Steps, 7-Bit + Sign 0.9764 mV/V VEXC Gain With Respect to VREF 0.52 V/V Gain Error Drift 25 ppm/°C VEXC Range Upper Limit IEXC = 5mA VSA − 0.5 V IEXC SHORT Short-Circuit VEXC Output Current 50 mA DIGITAL INTERFACE Two-Wire Compatible Bus Speed 1 400 kHz One-Wire Serial Speed Baud Rate 4.8K 38.4K Bits/s Maximum Lookup Table Size(6) 17 x 3 x 16 Bits Two-Wire Data Rate PGA309 to EEPROM (SCL frequency) 65 kHz LOGIC LEVELS Input Levels (SDA, SCL, PRG, TEST) Low 0.2 • VSD V (SDA, SCL, PRG, TEST) High 0.7 • VSD V (SDA, SCL) Hysteresis 0.1 • VSD V Pull-Up Current Source (SDA, SCL) 55 85 125 µA Pull-Down Current Source (TEST) 15 25 40 µA Output LOW Level (SDA, SCL, PRG) Open Drain, ISINK = 5mA 0.4 V

/C0080/C0071/C0065/C0051/C0048/C0057 SBOS292B − DECEMBER 2003 − REVISED JANUARY 2005 www.ti.com ELECTRICAL CHARACTERISTICS (continued) BOLDFACE limits apply over the specified temperature range: TA = −40°C to +125°C TA = +25°C, VSA = VSD = +5V (VSA = VSUPPLY ANALOG , VSD = VSUPPLY DIGITAL; VSA must equal VSD ), GNDD = GNDA = 0, and VREF = REFIN/REFOUT = +5V, unless otherwise noted. PGA309 PARAMETER UNITSMAXTYPMINCONDITIONS POWER SUPPLY VSA , VSD 2.7 5.5 V ISA + ISD , Quiescent Current VSA = VSD = +5V, without Bridge Load 1.2 1.6 mA POWER-ON RESET Power-Up Threshold VSA Rising 2.2 2.7 V Power-Down Threshold VSA Falling 1.7 V TEMPERATURE RANGE Specified Performance −40 +125 °C Operational − Degraded Performance −55 +150 °C (1)PGA309 total differential gain from input (VIN1−VIN2) to output (VOUT ). VOUT / (VIN1−VIN2) = (Front-End PGA gain) (Output Amplifier gain) (Gain DAC). (2)RTI = referred to input. RTO = referred to output. (3)Linear input range is the allowed min/max voltage on the VIN1 and VIN2 pins for the input PGA to continue to operate in a linear region. The allowed common-mode and differential voltage is dependent upon gain and offset settings. Refer to the Gain Scaling section for more information. (4)Unless limited by over/under-scale setting. (5)When V EXC is enabled, a minimum reference selector circuit becomes the reference for the comparator threshold. This minimum reference selector circuit uses VEXC − 100mV and VSA − 1.2V and compares the VINX pin to the lower of the two references. This ensures accurate fault monitoring in conditions where VEXC might be higher or lower than the input CMR of the PGA input amplifier relative to VSA . (6)Lookup Table allows multislope compensation over temperature. Lookup Table has access to 17 calibration points consisting of 3 adjustment values (Tx, Temperature, ZMx, Zero DAC, GMx, Gain DAC) that are stored in 16-bit data format (17x3x16 = Lookup Table size).

/C0080/C0071/C0065/C0051/C0048/C0057 SBOS292B − DECEMBER 2003 − REVISED JANUARY 2005 www.ti.com PIN CONFIGURATION Top View REF IN/REFOUT TEMP IN SDA SCL PRG GND D VSD TEST VEXC GND A VSA VIN1 VIN2 VFB VOUT VSJ PGA309 TSSOP PIN DESCRIPTION PIN NAME DESCRIPTION 1 VEXC Bridge sensor excitation. Connect to bridge if linearization and/or internal reference for bridge excitation is to be used. 2 GND A Analog ground. Connect to analog ground return path for VSA . Should be same as GNDD . 3 VSA Analog voltage supply. Connect to analog voltage supply. To be within 200mV of VSD . 4 VIN1 Signal input voltage 1. Connect to + or – output of sensor bridge. Internal multiplexer can change connection internally to Front-End PGA. 5 VIN2 Signal input voltage 2. Connect to + or – output of sensor bridge. Internal multiplexer can change connection internally to Front-End PGA. 6 VFB VOUT feedback pin. Voltage feedback sense point for over/under-scale limit circuitry. When internal gain set resistors for the output amplifier are used, this is also the voltage feedback sense point for the output amplifier. VFB in combination with VSJ allows for ease of external filter and protection circuits without degrading the PGA309 VOUT accuracy. VFB must always be connected to either VOUT or the point of feedback for VOUT , if external protection is used. 7 VOUT Analog output voltage of conditioned sensor. 8 VSJ Output amplifier summing junction. Use for output amplifier compensation when driving large capacitive loads (> 100pF) and/or for using external gain setting resistors for the output amplifier. 9 TEST Test/External Controller Mode pin. Pull to GNDD in normal mode. 10 VSD Digital voltage supply. Connect to digital voltage supply. To be within 200mV of VSA . 11 GND D Digital ground. Connect to digital ground return path for VSD . Should be same as GNDA. 12 PRG Single-wire interface program pin. UART-type interface for digital calibration of the PGA309 over a single wire. Can be connected to VOUT for a three-lead (VS, GND, VOUT ) digitally-programmable sensor assembly. 13 SCL Clock input/output for Two-Wire, industry-standard compatible interface for reading and writing digital calibration and configuration from external EEPROM. Can also communicate directly to the registers in the PGA309 through the Two-Wire, industry-standard compatible interface. 14 SDA Data input/output for Two-Wire, industry-standard compatible interface for reading and writing digital calibration and configuration from external EEPROM. Can also communicate directly to the registers in the PGA309 through the Two-Wire, industry-standard compatible interface. 15 TEMP IN External temperature signal input. PGA309 can be configured to read a bridge current sense resistor as an indicator of bridge temperature, or an external temperature sensing device such as diode junction, RTD, or thermistor. This input can be internally gained by 1, 2, 4, or 8. In addition, this input can be read differentially with respect to VGNDA , VEXC , or the internal/external VREF . There is also an internal, register-selectable, 7µA current source (ITEMP ) that can be connected to TEMPIN as an RTD, thermistor, or diode excitation source. 16 REF IN/REFOUT Reference input/output pin. As an output, the internal reference (selectable as 2.5V or 4.096V) is available for system use on this pin. As an input, the internal reference may be disabled and an external reference can then be applied as the reference for the PGA309.

/C0080/C0071/C0065/C0051/C0048/C0057 SBOS292B − DECEMBER 2003 − REVISED JANUARY 2005 www.ti.com TYPICAL CHARACTERISTICS TA = +25°C, VSA = VSD = +5V (VSA = VSUPPLY ANALOG , VSD = VSUPPLY DIGITAL, VSA must equal VSD ), GNDD = GNDA = 0, and VREF = REFIN/REFOUT = +5V, unless otherwise noted. Average 4.090 4.085 4.080 4.075 4.070 4.065 4.060 VREF (V) Temperature (/C0095C) −55 −35 −15 5 25 45 65 85 105 125 145 VREF vs TEMPERATURE IB CURRENT vs TEMPERATURE Temperature (/C0095C) −55 −35 −15 5 25 45 65 85 105 125 145 1.0 0.5 −0.5 −1.0 −1.5 −2.0 −2.5 −3.0 IB (nA) Average, nA ITEMP CURRENT vs TEMPERATURE Temperature (/C0095C) −55 −35 −15 5 25 45 65 85 105 125 145 ITEMP (µA) Average −10 −20 −30 COMMON−MODE REJECTION RATIO vs FREQUENCY Frequency (Hz) CMRR (dB) 10 100 1k 10k 100k 1M RTO of Front−End PGA −10 POWER−SUPPLY REJECTION RATIO vs FREQUENCY Frequency (Hz) PSRR (dB) 10 100 1k 10k 100k 1M Small−Signal VREF and VEXT Enabled VREF =2 . 5 V PSRR at VOUT CLOSED−LOOP GAIN vs FREQUENCY Frequency (Hz) Gain (dB) 10 100 1k 10k 100k 1M G OUTAMP = Output Amplifer Gain G OUTAMP =9 V / V G FRONT = 32V/V G OUTAMP =9 V / V G FRONT = 128V/V G OUTAMP =2 V / V G FRONT =8 V / V G OUTAMP =2 V / V G FRONT =3 2 V / V

/C0080/C0071/C0065/C0051/C0048/C0057 SBOS292B − DECEMBER 2003 − REVISED JANUARY 2005 www.ti.com TYPICAL CHARACTERISTICS (Cont.) TA = +25°C, VSA = VSD = +5V (VSA = VSUPPLY ANALOG , VSD = VSUPPLY DIGITAL, VSA must equal VSD ), GNDD = GNDA = 0, and VREF = REFIN/REFOUT = +5V, unless otherwise noted. VOUT S W I N GT OR A I Lv sILOAD ILOAD (mA) VS VS − 0.1 VS − 0.2 VS − 0.3 VS − 0.4 VS − 0.5 0.5 0.4 0.3 0.2 0.1 5 1 01 52 02 5 VS =2 . 7 V VS =5 V VS =5 V VS =2 . 7 V IQ vs TEMPERATURE Temperature (/C0095C) −55 −35 −15 5 25 45 65 85 105 125 145 1.6 1.4 1.2 1.0 0.8 0.6 0.4 0.2 IQ (mA) All Blocks Enabled Ref, Exc, and ADC Disabled TEMPERATURE ADC ERROR (INTERNAL MODE) Actual Die Temperature (/C0095C) −55 −35 −15 5 25 45 65 85 105 125 145 0.4 0.2 −0.2 −0.4 −0.6 −0.8 −1.0 −1.2 Temp ADC Error (/C0095C) TEMPERATURE ADC ERROR (EXTERNAL MODES) Input Signal (% FS of VREF ) −100 −80 −60 −40 −20 0 20 40 60 80 100 0.4 0.3 0.2 0.1 −0.1 −0.2 −0.3 −0.4 Total Error (% of FS) Reg 6 = 0403h VREF =5 VE x t e r n a l 15−Bit + Sign Reg 6 = 0503h VREF =2 . 0 4 8 V (Temp ADC Internal) 15−Bit + Sign Reg 6 = 0430h VREF = 2.5V Internal 11−Bit + Sign Reg 6 = 0433h VREF = 2.5V Internal 15−Bit + Sign VREF NOISE (0.1Hz TO 10Hz) 1s/div 50µV/div VREF = 4.096V Measured After Bandpass Filter 0.1Hz Second−Order High−Pass 10Hz Fourth−Order Low−Pass VOUT NOISE (0.1Hz TO 10Hz PEAK−TO−PEAK NOISE) 1s/div 1mV/div G=1 1 5 2 Coarse Offset =−59mV Measured After Bandpass Filter 0.1Hz Second−Order High−Pass 10Hz Fourth−Order Low−Pass VIN =+ 6 1 m V CLK_CFG= 00 (default)

brief overview of each major function. Table 1. PGA309 Adjustment Capability sensors with unknown polarity output. Amplifier that provides additional programmable gain. brought out on the PGA309 for application flexibility. RFI/EMI filtering required in many end applications. an output range of 0.1V to VSA − 0.1V. sensor excitation/linearization through the VEXC pin. reference or to VSA for ratiometric-scaled systems.

Figure 1. Simplified Diagram of the PGA309 in a Typical Configuration.

/C0080/C0071/C0065/C0051/C0048/C0057 SBOS292B − DECEMBER 2003 − REVISED JANUARY 2005 www.ti.com ADC FOR TEMPERATURE SENSING The temperature sense circuitry drives the compensation for the sensor span and offset drift. Either internal or external temperature sensing is possible. The temperature can be sensed in one of the following ways: /C0068Bridge impedance change (excitation current sense, in the positive or negative part of the bridge), for sensors with large temperature coefficient of resistance (TCR > 0.1%/°C). /C0068On-chip PGA309 temperature, when the chip is located sufficiently close to the sensor. /C0068External diode, thermistor, or RTD placed on the sensor membrane. An internal 7µA current source may be enabled to excite these types of temperature sensors. The temperature signal is digitized by the onboard Temp ADC. The output of the Temp ADC is used by the control digital circuit to read the data from the Lookup Table in an external EEPROM, and set the output of the Gain DAC and the Zero DAC to the calibrated values as temperature changes. An additional function provided through the Temp ADC is the ability to read the V OUT pin back through the Temp ADC input mux. This provides flexibility for a digital output through either One-Wire or Two-Wire interface, as well as the possibility for an external microcontroller to perform real-time custom calibration of the PGA309. EXTERNAL EEPROM AND TEMPERATURE COEFFICIENTS The PGA309 uses an industry-standard Two-Wire external EEPROM (typically, a SOT23-5 package). A 1k-bit (minimum) EEPROM is needed when using all 17 temperature coefficients. Larger EEPROMs may be used to provide space for a serial number, lot code, or other data. The first part of the external EEPROM contains the configuration data for the PGA309, with settings for: /C0068Register 3—Reference Control and Linearization /C0068Register 4—PGA Coarse Offset and Gain/Output Amplifier Gain /C0068Register 5—PGA Configuration and Over/Under- Scale Limit /C0068Register 6—Temp ADC Control This section of the EEPROM contains its own individual checksum (Checksum1). The second part of the external EEPROM contains up to 17 temperature index values and corresponding temperature coefficients for the Zero DAC and Gain DAC adjustments with measured temperature, and also contains its own checksum (Checksum2). The PGA309 lookup logic contains a linear interpolation algorithm for accurate DAC adjustments between stored temperature indexes. This approach allows for a piecewise linear temperature compensation of up to 17 temperature indexes and associated temperature coefficients. If either Checksum1, Checksum2, or both are incorrect, the output of the PGA309 is set to high-impedance. FAULT MONITOR To detect sensor burnout or a short, a set of four comparators are connected to the inputs of the Front-End PGA. If any of the inputs are taken to within 100mV of ground or V EXC, or violate the input CMR of the Front-End PGA, then the corresponding comparator sets a sensor fault flag that causes the PGA309 V OUT to be driven within 100mV of either VSA or ground, depending upon the alarm configuration setting (Register 5—PGA Configuration and Over/Under-Scale Limit). This will be well above the set Over-Scale Limit level or well below the set Under-Scale Limit level. The state of the fault condition can be read in digital form in Register 8—Alarm Status Register. If the Over/Under-Scale Limit is disabled, the PGA309 output voltage will still be driven within 100mV of either V SA or ground, depending upon the alarm configuration setting. There are five other fault detect comparators that help detect subtle PGA309 front-end violations that could otherwise result in linear voltages at VOUT that would be interpreted as valid states. These are especially useful during factory calibration and setup, and are configured through Register 5—PGA Configuration and Over/Under-Scale Limit. Their status can also be read back through Register 8—Alarm Status Register. OVER-SCALE AND UNDER-SCALE LIMITS The over-scale and under-scale limit circuitry combined with the fault monitor circuitry provides a means for system diagnostics. A typical sensor-conditioned output may be scaled for 10% to 90% of the system ADC range for the sensor normal operating range. If the conditioned pressure sensor is below 4%, it is considered under-pressure; if over 96%, it is considered over-pressure. The PGA309 over/under-scale limit circuit can be programmed individually for under-scale and over-scale values that clip or limit the PGA309 output. From a system diagnostic view, 10% to 90% of ADC range is normal operation, < 4% is under-pressure, and > 96% is over-pressure. If the fault detect circuitry is used, a detected fault will cause the PGA309 output to be driven to positive or negative saturation. If this fault

/C0080/C0071/C0065/C0051/C0048/C0057 SBOS292B − DECEMBER 2003 − REVISED JANUARY 2005 www.ti.com flag is programmed for high, then > 97% ADC range will be a fault; if programmed for low, then < 3% ADC range will be a fault. In this configuration, the system software can be used to distinguish between over- or under-pressure condition, which indicates an out-of-control process, or a sensor fault. POWER-UP AND NORMAL OPERATION The PGA309 has circuitry to detect when the power supply is applied to the PGA309, and reset the internal registers and circuitry to an initial state. This reset also occurs when the supply is detected to be invalid, so that the PGA309 is in a known state when the supply becomes valid again. The rising threshold for this circuit is typically 2.2V and the falling threshold is typically 1.7V. After the power supply becomes valid, the PGA309 waits for approximately 25ms and then attempts to read the configuration data from the external EEPROM device. If the EEPROM has the proper flag set in address locations 0 and 1, then the PGA309 continues reading the first part of the EEPROM; otherwise, the PGA309 waits for one second before trying again. If the PGA309 detects no response from the EEPROM, the PGA309 waits for one second and tries again; otherwise, the PGA309 tries to free the bus and waits for 25ms before trying to read the EEPROM again. If a successful read of the first part of the EEPROM is accomplished, (including valid Checksum1 data), the PGA309 triggers the Temp ADC to measure temperature. For 16-bit resolution results, the converter takes approximately 125ms to complete a conversion. Once the conversion is complete, the PGA309 begins reading the Lookup Table information from the EEPROM (second part) to calculate the settings for the Gain DAC and Zero DAC. The PGA309 reads the entire Lookup Table so that it can determine if the checksum for the Lookup Table (Checksum2) is correct. Each entry in the Lookup Table requires approximately 500µs to read from the EEPROM. Once the checksum is determined to be valid, the calculated values for the Gain and Zero DACs are updated into their respective registers, and the output amplifier is enabled. The PGA309 then begins looping through this entire procedure, starting with reading the EEPROM configuration registers from the first part of the EEPROM, then starting a new conversion on the Temp ADC, which then triggers reading the Lookup Table data from the second part of the EEPROM. This loop continues indefinitely. DIGITAL INTERFACE There are two digital interfaces on the PGA309. The PRG pin uses a One-Wire, UART-compatible interface with bit rates from 4.8Kbits/s to 38.4Kbits/s. The SDA and SCL pins together form an industry standard Two-Wire interface at clock rates from 1kHz to 400kHz. The external EEPROM uses the Two-Wire interface. Communication to the PGA309 internal registers, as well as to the external EEPROM, for programming and readback can be conducted through either digital interface. It is also possible to connect the One-Wire communication pin, PRG, to the V OUT pin in true three-wire sensor modules and still allow for programming. In this mode, the PGA309 output amplifier may be enabled for a set time period and then disabled again to allow sharing of the PRG pin with the V OUT connection. This allows for both digital calibration and analog readback during sensor calibration in a three-wire sensor module. The Two-Wire interface has timeout mechanisms to prevent bus lockup from occurring. The Two-Wire master controller in the PGA309 has a mode that attempts to free up a stuck-at-zero SDA line by issuing SCL pulses, even when the bus is not indicated as idle after a timeout period has expired. The timeout will only apply when the master portion of the PGA309 is attempting to initiate a Two-Wire communication.

Figure 2. Detailed Block Diagram

Orderable Device Status(1) Package Type Package Drawing Pins Package Qty Eco Plan(2) Lead/Ball FinishMSL Peak Temp (3) PGA309AIPWR ACTIVE TSSOP PW 16 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM PGA309AIPWRG4 ACTIVE TSSOP PW 16 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM PGA309AIPWT ACTIVE TSSOP PW 16 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM PGA309AIPWTG4 ACTIVE TSSOP PW 16 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM (1)The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2)Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontentfor the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS):TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt):This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br):TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. PACKAGE OPTION ADDENDUM www.ti.com 5-Apr-2006 Addendum-Page 1

*All dimensions are nominal Device Package Type Package Drawing Pins SPQ Reel Diameter (mm) Reel Width W1 (mm) A0 (mm) B0 (mm) K0 (mm) P1 (mm) W (mm) Pin1 Quadrant PACKAGE MATERIALS INFORMATION www.ti.com 30-Jan-2009 Pack Materials-Page 1

*All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) PGA309AIPWR TSSOP PW 16 2500 346.0 346.0 29.0 PGA309AIPWT TSSOP PW 16 250 190.5 212.7 31.8 PACKAGE MATERIALS INFORMATION www.ti.com 30-Jan-2009 Pack Materials-Page 2

MTSS001C – JANUARY 1995 – REVISED FEBRUARY 1999 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 PW (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE

14 PINS SHOWN

0,65 M0,10 0,10 0,25 0,50 0,75 0,15 NOM Gage Plane 9,80 9,60 7,90 7,70 2016 6,60 6,40 4040064/F 01/97 0,30 6,60 6,20 0,19 4,30 4,50 0,15 A 1,20 MAX 5,10 4,90 3,10 2,90 A MAX A MIN DIM PINS ** 0,05 4,90 5,10 Seating Plane 0°–8° NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice. C. Body dimensions do not include mold flash or protrusion not to exceed 0,15. D. Falls within JEDEC MO-153

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Product Information

PGA309AIPWRG4 specifications and overview.

Summary

Voltage Output PROFRAMMABLE SENSOR CONDITIONER

Description

Voltage Output PROFRAMMABLE SENSOR CONDITIONER

Source title PGA309AIPWRG4 Datasheet(PDF) - Burr-Brown (TI)

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