PGA309AIPWR

PGA309 TI | Alldatasheet

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Analog Sensor Linearization Digital T emperature Compensation Analog Signal Conditioning PGA309 Digital Cal VEXC 0 50 psi P Ext T emp Ext T emp Nonlinear Bridge Transducer Linearization Circuit Auto- Zero PGA Fault Monitor Int T emp Control Register Interface Circuitry EEPROM (SOT23-5) Ref T +125 C/c176 /c45 /c176 40 C Over/Under Scale Limiter Lin DAC T emp ADC Linear VOUT VS PGA309 www.ti.com SBOS292C –DECEMBER 2003–REVISED JANUARY 2011 VoltageOutput ProgrammableSensorConditioner Check forSamples: PGA309 1FEATURES DESCRIPTION 2• Complete BridgeSensor Conditioner The PGA309 is a programmable analog signal conditionerdesignedforbridgesensors.The analog• VoltageOutput:Ratiometricor Absolute signalpath amplifiesthe sensorsignaland provides• DigitalCal:No Potentiometers/SensorTrims digitalcalibrationforzero,span,zerodrift,span drift,• Sensor ErrorCompensation and sensor linearizationerrorswith appliedstress – Span, Offset,and Temperature Drifts (pressure,strain,etc.).The calibrationisdone viaa One-Wire digitalserialinterfaceor through a• Low Error,Time-Stable Two-Wire industry-standardconnection. The• Sensor LinearizationCircuitry calibrationparameters are stored in external

• Temperature Sense: Internalor External nonvolatilememory (typicallySOT23-5) to eliminate manual trimmingand achievelong-termstability.• CalibrationLookup TableLogic – Uses ExternalEEPROM (SOT23-5) The all-analogsignalpath containsa 2x2 input multiplexer(mux), auto-zero programmable-gain• Over/Under-ScaleLimiting instrumentationamplifier,linearizationcircuit,voltage• Sensor FaultDetection reference,internaloscillator,controllogic,and an
• +2.7V TO +5.5V Operation output amplifier.Programmable level shifting compensatesforsensordc offsets.• –40°C to+125°C Operation
• Small TSSOP-16 Package The coreofthePGA309 istheprecision,low-drift,no 1/f noise Front-End PGA (Programmable Gain Amplifier).The overallgainof the Front-EndPGA +APPLICATIONS Output Amplifiercan be adjustedfrom 2.7V/V to• BridgeSensors 1152V/V.The polarityof the inputscan be switched• Remote 4-20mA Transmitters throughtheinputmux toaccommodate sensorswith
• Strain,Load, and Weigh Scales unknown polarityoutput.The FaultMonitorcircuit detectsand signalssensor burnout,overload,and• Automotive Sensors systemfaultconditions. EVALUATION TOOLS For detailedapplicationinformation,see thePGA309
• Hardware Designer’s Kit(PGA309EVM) User's Guide (SBOU024) availablefordownload at www.ti.com.– Temperature EvalofPGA309 + Sensor – FullProgramming ofPGA309 – Sensor Compensation AnalysisTool Pleasebe aware thatan importantnoticeconcerningavailability,standardwarranty,and use incriticalapplicationsofTexas Instrumentssemiconductorproductsand disclaimerstheretoappearsattheend ofthisdatasheet. 2Alltrademarksarethepropertyoftheirrespectiveowners. PRODUCTION DATA informationiscurrentas ofpublicationdate. Copyright© 2003–2011,Texas InstrumentsIncorporatedProductsconform to specificationsper the terms of the Texas Instrumentsstandardwarranty.Productionprocessingdoes not necessarilyincludetestingofallparameters.

SBOS292C –DECEMBER 2003–REVISED JANUARY 2011 www.ti.com This integratedcircuitcan be damaged by ESD. Texas Instrumentsrecommends thatallintegratedcircuitsbe handled with appropriateprecautions.Failuretoobserveproperhandlingand installationprocedurescan cause damage. ESD damage can rangefromsubtleperformancedegradationtocompletedevicefailure.Precisionintegratedcircuitsmay be more susceptibletodamage because verysmallparametricchanges couldcause thedevicenottomeet itspublishedspecifications. PACKAGE/ORDERING INFORMATION (1) PACKAGE PACKAGE PRODUCT PACKAGE-LEAD DESIGNATOR MARKING PGA309 TSSOP-16 PW PGA309 (1) Forthemost currentpackage and orderinginformationsee thePackage OptionAddendum attheend ofthisdocument,orsee theTI web siteatwww.ti.com. ABSOLUTE MAXIMUM RATINGS (1) Over operatingfree-airtemperaturerange,unlessotherwisenoted. PARAMETER PGA309 UNIT SupplyVoltage,VSD ,VSD +7.0 V InputVoltage,VIN1,VIN2 (2) –0.3toVSA +0.3 V InputCurrent,VFB ,VOUT ±150 mA InputCurrent ±10 mA OutputCurrentLimit 50 mA StorageTemperatureRange –60 to+150 °C OperatingTemperatureRange –55 to+150 °C JunctionTemperature +150 °C ESD Ratings Human Body Model (HBM) 4 kV (1) Stressesabove theseratingsmay cause permanentdamage. Exposuretoabsolutemaximum conditionsforextendedperiodsmay degradedevicereliability.These arestressratingsonly,and functionaloperationofthedeviceattheseorany otherconditionsbeyond thosespecifiedisnotimplied. (2) Inputterminalsarediode-clampedtothepower-supplyrails.Inputsignalsthatcan swingmore than0.5Vbeyond thesupplyrailsshould be currentlimitedto10mA orless.

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www.ti.com SBOS292C –DECEMBER 2003–REVISED JANUARY 2011

ELECTRICAL CHARACTERISTICS

Boldfacelimitsapplyoverthespecifiedtemperaturerange,TA = –40°C to+125°C. AtTA = +25°C, VSA = VSD = +5V (VSA = VSUPPLY ANALOG ,VSD = VSUPPLY DIGITAL;VSA must equalVSD ),GND D = GND A = 0,and VREF = REF IN/REFOUT = +5V, unlessotherwisenoted. PGA309 PARAMETER CONDITIONS MIN TYP MAX UNIT Front-EndPGA + Output Amplifier VOUT /VIN DifferentialSignalGain Range (1) Finegainadjust= 1 8 to1152 V/V Front-EndPGA Gains:4,8,16,23.27,32,42.67,64,128 OutputAmplifiergains:2,2.4,3,3.6,4.5,6,9 InputVoltageNoiseDensity f= 1kHz 210 nV/√Hz VOUT Slew Rate 0.5 V/ms VOUT SettlingTime (0.01%) VOUT /VIN Differentialgain= 8,R L = 5kΩ ||200pF 6 ms VOUT SettlingTime (0.01%) VOUT /VIN Differentialgain= 191,R L = 5kΩ ||200pF 4.1 ms VOUT Nonlinearity 0.002 %FSR ExternalSensorOutputSensitivity VSA = VSD = VEXC = +5V 1 to245 mV/V Front-EndPGA Auto-ZeroInternalFrequency 7 kHz OffsetVoltage(RTI)(2) Coarse offsetadjustdisabled ±3 ±50 mV vs Temperature ±0.2 mV/°C vs SupplyVoltage,VSA ±2 mV/V vs Common-Mode Voltage G F = Front-EndPGA gain 1500/GF 6000/GF mV/V LinearInputVoltageRange (3) 0.2 VSA − 1.5 V InputBiasCurrent 0.1 1.5 nA InputImpedance:Differential 30 ||6 G Ω ||pF InputImpedance:Common-Mode 50 ||20 G Ω ||pF InputVoltageNoise 0.1Hzto10Hz,G F = 128 4 mVPP PGA Gain Gain Range Steps 4,8,16,23.27,32,42.67,64,128 4 to128 V/V InitialGain Error G F = 4 to42 0.2 ±1 % G F = 64 0.25 ±1.2 % G F = 128 0.3 ±1.6 % vs Temperature 10 ppm/ °C Output VoltageRange 0.05toVSA − 0.1 V Bandwidth Gain = 4 400 kHz Gain = 128 60 kHz Coarse OffsetAdjust (RTIofFront-EndPGA) Range ±(14)(VREF )(0.00085) ±56 ±59.5 ±64 mV vs Temperature 0.004 %/°C Drift ±14 steps,4-bit+ sign 4 mV FineOffsetAdjust(ZeroDAC) (RTO oftheFront-EndPGA) (2) Programming Range 0 VREF V OutputVoltageRange 0.1 VSA – 0.1 V Resolution 65,536steps,16-bitDAC 73 mV IntegralNonlinearity 20 LSB DifferentialNonlinearity 0.5 LSB Gain Error 0.1 % Gain ErrorDrift 10 ppm/°C Offset 5 mV OffsetDrift 10 mV/°C (1) PGA309 totaldifferentialgainfrominput(VIN1 – VIN2)tooutput(VOUT ).VOUT /(VIN1 – VIN2)= (Front-endPGA gain)× (OutputAmplifier gain)× (GainDAC). (2) RTI = Referred-to-input.RTO = referredtooutput. (3) Linearinputrangeistheallowedmin/max voltageon theVIN1 and VIN2 pinsfortheinputPGA tocontinuetooperateina linearregion. The allowedcommon-mode and differentialvoltagedepends on gainand offsetsettings.RefertotheGain Scalingsectionformore information. Copyright© 2003–2011,Texas InstrumentsIncorporated SubmitDocumentationFeedback 3 ProductFolderLink(s):PGA309

SBOS292C –DECEMBER 2003–REVISED JANUARY 2011 www.ti.com ELECTRICAL CHARACTERISTICS (continued) Boldfacelimitsapplyoverthespecifiedtemperaturerange,TA = –40°C to+125°C. AtTA = +25°C, VSA = VSD = +5V (VSA = VSUPPLY ANALOG ,VSD = VSUPPLY DIGITAL;VSA must equalVSD ),GND D = GND A = 0,and VREF = REF IN/REFOUT = +5V, unlessotherwisenoted. PGA309 PARAMETER CONDITIONS MIN TYP MAX UNIT Output FineGain Adjust(GainDAC) Range 0.33to1 V/V Resolution 65,536steps,16-bitDAC 10 mV/V IntegralNonlinearity 20 LSB DifferentialNonlinearity 0.5 LSB Output Amplifier OffsetVoltage(RTIofOutputAmplifier)(4) 3 mV vs Temperature 5 mV/°C vs SupplyVoltage,VSA 30 mV/V Common-Mode InputRange 0 VS – 1.5 V InputBiasCurrent 100 pA AmplifierInternalGain Gain Range Steps 2,2.4,3,3.6,4.5,6,9 2 to9 V/V InitialGain Error 2,2.4,3.6 0.25 ±1 % 4.5 0.3 ±1.2 % 6 0.4 ±1.5 % 9 0.6 ±2.0 % vs Temperature 2,2.4,3.6 5 ppm/ °C 4.5 5 ppm/ °C 6 15 ppm/ °C 9 30 ppm/ °C Output VoltageRange (5) R L = 10kΩ 0.1 4.9 V Open-Loop Gain 115 dB Gain-BandwidthProduct 2 MHz Phase Margin Gain = 2,C L = 200pF 45 deg OutputResistance AC Small-signal,open-loop,f= 1MHz, IO = 0 675 Ω Over-and Under-ScaleLimits VREF = 4.096 Over-ScaleThresholds RatioofVREF ,Register5— bitsD5, D4, D3 = ‘000’ 0.9708 RatioofVREF ,Register5— bitsD5, D4, D3 = ‘001’ 0.9610 RatioofVREF ,Register5— bitsD5, D4, D3 = ‘010’ 0.9394 RatioofVREF ,Register5— bitsD5, D4, D3 = ‘011’ 0.9160 RatioofVREF ,Register5— bitsD5, D4, D3 = ‘100’ 0.9102 RatioofVREF ,Register5— bitsD5, D4, D3 = ‘101’ 0.7324 RatioofVREF ,Register5— bitsD5, D4, D3 = ‘110’ 0.5528 Over-ScaleComparatorOffset +6 +60 +114 mV Over-ScaleComparatorOffsetDrift +0.37 mV/°C Under-ScaleThresholds RatioofVREF ,Register5— bitsD2, D1, D0 = ‘111’ 0.0605 RatioofVREF ,Register5— bitsD2, D1, D0 = ‘110’ 0.0547 RatioofVREF ,Register5— bitsD2, D1, D0 = ‘101’ 0.0507 RatioofVREF ,Register5— bitsD2, D1, D0 = ‘100’ 0.0449 RatioofVREF ,Register5— bitsD2, D1, D0 = ‘011’ 0.0391 RatioofVREF ,Register5— bitsD2, D1, D0 = ‘010 0.0352 RatioofVREF ,Register5— bitsD2, D1, D0 = ‘001’ 0.0293 RatioofVREF ,Register5— bitsD2, D1, D0 = ‘000’ 0.0254 Unde-rScaleComparatorOffset −7 −50 +93 mV Under-ScaleComparatorOffsetDrift −0.15 mV/°C (4) RTI = Referred-to-input.RTO = referredtooutput. (5) Unlesslimitedby theover/under-scalesetting.

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www.ti.com SBOS292C –DECEMBER 2003–REVISED JANUARY 2011 ELECTRICAL CHARACTERISTICS (continued) Boldfacelimitsapplyoverthespecifiedtemperaturerange,TA = –40°C to+125°C. AtTA = +25°C, VSA = VSD = +5V (VSA = VSUPPLY ANALOG ,VSD = VSUPPLY DIGITAL;VSA must equalVSD ),GND D = GND A = 0,and VREF = REF IN/REFOUT = +5V, unlessotherwisenoted. PGA309 PARAMETER CONDITIONS MIN TYP MAX UNIT FaultMonitorCircuit INP_HI,INN_HI ComparatorThreshold See (6) VSA − 1.2orVEXC − 0.1 V INP_LO, INN_LO ComparatorThreshold 40 100 mV A1SAT_HI, A2SAT_HI ComparatorThreshold VSA − 0.12 V A1SAT_LO, A2SAT_LO ComparatorThreshold VSA − 0.12 V A3_VCM ComparatorThreshold VSA − 1.2 V ComparatorHysteresis 20 mV InternalVoltageReference VREF1 Register3,bitD9 = 1 2.46 2.5 2.53 V VREF1 Driftvs Temperature +10 ppm/ °C VREF2 IPU Register3,bitD9 = 0 4.0 4.096 4.14 V VREF2 Driftvs Temperature +10 ±7 ppm/ °C InputCurrentREF IN/REFOUT InternalVREF disabled 100 mA OutputCurrentREF IN/REFOUT VSA > 2.7VforVREF = 2.5V 1 mA VSA > 4.3VforVREF = 4.096V 1 mA Temperature Sense Circuitry(ADC) InternalTemperatureMeasurement Register6,bitD9 = 1 xx Accuracy ±2 °C xx Resolution 12-Bit+ sign,twoscomplement dataformat ±0.0625 °C xx TemperatureMeasurement Range −55 +150 °C xx ConversionRate R 1,R 0 = ‘11’,12-bit+ signresolution 24 ms Temperature ADC ExternalTemperatureMode Temp PGA + Temp ADC 1 to8 V/V xx Gain Range Steps G PGA = 1,2,4,8 GND −0.2 VSA +0.2 V xx AnalogInputVoltageRange TemperatureADC InternalREF (2.048V) Register6,bitD8 = 1 xx Full-ScaleInputVoltage (+Input)− (−Input) ±2.048/GPGA V xx DifferentialInputImpedance 2.8/GPGA M Ω xx Common-Mode InputImpedance G PGA = 1 3.5 M Ω G PGA = 2 3.5 M Ω G PGA = 4 1.8 M Ω G PGA = 8 0.9 M Ω xx Resolution R1, R0 = ‘00’,ADC2X = ‘0’,conversiontime= 8ms 11 Bits+ Sign R1, R0 = ‘01’,ADC2X = ‘0’,conversiontime= 32ms 13 Bits+ Sign R1, R0 = ‘10’,ADC2X = ‘0’,conversiontime= 64ms 14 Bits+ Sign R1, R0 = ‘11’,ADC2X = ‘0’,conversiontime= 128ms 15 Bits+ Sign xx IntegralNonlinearity 0.004 % xx OffsetError G PGA = 1 1.2 mV G PGA = 2 0.7 mV G PGA = 4 0.5 mV G PGA = 8 0.4 mV xx OffsetDrift G PGA = 1 1.2 mV/°C G PGA = 2 0.6 mV/°C G PGA = 4 0.3 mV/°C G PGA = 8 0.3 mV/°C (6) When VEXC isenabled,a minimum referenceselectorcircuitbecomes thereferenceforthecomparatorthreshold.Thisminimum referenceselectorcircuituses VEXC − 100mV and VSA − 1.2Vand compares theVINX pintothelowerofthetwo references.This configurationensuresaccuratefaultmonitoringinconditionswhere VEXC mightbe higherorlowerthantheinputCMR ofthePGA input amplifierrelativetoVSA . Copyright© 2003–2011,Texas InstrumentsIncorporated SubmitDocumentationFeedback 5 ProductFolderLink(s):PGA309

SBOS292C –DECEMBER 2003–REVISED JANUARY 2011 www.ti.com ELECTRICAL CHARACTERISTICS (continued) Boldfacelimitsapplyoverthespecifiedtemperaturerange,TA = –40°C to+125°C. AtTA = +25°C, VSA = VSD = +5V (VSA = VSUPPLY ANALOG ,VSD = VSUPPLY DIGITAL;VSA must equalVSD ),GND D = GND A = 0,and VREF = REF IN/REFOUT = +5V, unlessotherwisenoted. PGA309 PARAMETER CONDITIONS MIN TYP MAX UNIT Temperature ADC. continued xx Offsetvs VSA G PGA = 1 800 mV/V G PGA = 2 400 mV/V G PGA = 4 200 mV/V G PGA = 8 150 mV/V xx Gain Error 0.05 0.50 % xx Gain ErrorDrift 5 50 ppm/°C xx Noise Allgains < 1 LSB xx Gain vs VSA 80 ppm/V xx Common-Mode Rejection Atdc and G PGA = 8 105 dB Atdc and G PGA = 1 100 dB Temp ADC Ext.REF (VREFT = VREF ,VEXC ,orVSA ) Register6,bitD8 = 0 xx Full-ScaleInputVoltage (+Input)− (−Input) ±VREFT /GPGA V xx DifferentialInputImpedance 2.4/GPGA M Ω xx Common-Mode InputImpedance G PGA = 1 8 M Ω G PGA = 2 8 M Ω G PGA = 4 8 M Ω G PGA = 8 8 M Ω xx Resolution R1, R0 = ‘00’,ADC2X = ‘0’,conversiontime= 6ms 11 Bits+ Sign R1, R0 = ‘01’,ADC2X = ‘0’,conversiontime= 24ms 13 Bits+ Sign R1, R0 = ‘10’,ADC2X = ‘0’,conversiontime= 50ms 14 Bits+ Sign R1, R0 = ‘11’,ADC2X = ‘0’,conversiontime= 100ms 15 Bits+ Sign xx IntegralNonlinearity 0.01 % xx OffsetError G PGA = 1 2.5 mV G PGA = 2 1.25 mV G PGA = 4 0.7 mV G PGA = 8 0.3 mV xx OffsetDrift G PGA = 1 1.5 mV/°C G PGA = 2 1.0 mV/°C G PGA = 4 0.7 mV/°C G PGA = 8 0.6 mV/°C xx Gain Error −0.2 % xx Gain ErrorDrift 2 ppm/°C xx Gain vs VSA 80 ppm/V xx Common-Mode Rejection Atdc and G PGA = 8 100 dB Atdc and G PGA = 1 85 dB ExternalTemperatureCurrentExcitationITEMP Register6,bitD11 = 1 xx CurrentExcitation 5.8 7 8 mA xx TemperatureDrift 5 nA/°C xx VoltageCompliance VSA −1.2 V

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www.ti.com SBOS292C –DECEMBER 2003–REVISED JANUARY 2011 ELECTRICAL CHARACTERISTICS (continued) Boldfacelimitsapplyoverthespecifiedtemperaturerange,TA = –40°C to+125°C. AtTA = +25°C, VSA = VSD = +5V (VSA = VSUPPLY ANALOG ,VSD = VSUPPLY DIGITAL;VSA must equalVSD ),GND D = GND A = 0,and VREF = REF IN/REFOUT = +5V, unlessotherwisenoted. PGA309 PARAMETER CONDITIONS MIN TYP MAX UNIT LinearizationAdjustand ExcitationVoltage(VEXC ) Range 0 Register3,bitD11 = 0 xx LinearizationDAC Range WithrespecttoVFB −0.166to+0.166 V/V xx LinearizationDAC Resolution ±127 steps,7-bit+ sign 1.307 mV/V xx VEXC Gain WithrespecttoVREF 0.83 V/V xx Gain ErrorDrift 25 ppm/°C Range 1 Register3,bitD11 = 1 xx LinearizationDAC Range WithrespecttoVFB −0.124to+0.124 V/V xx LinearizationDAC Resolution ±127 steps,7-bit+ sign 0.9764 mV/V xx VEXC Gain WithrespecttoVREF 0.52 V/V xx Gain ErrorDrift 25 ppm/°C VEXC Range Upper Limit IEXC = 5mA VSA −0.5 V IEXC SHORT Short-circuitVEXC outputcurrent 50 mA DigitalInterface Two-WireCompatible Bus speed 1 400 kHz One-Wire Serialspeed baud rate 4.8K 38.4K Bits/s Maximum Lookup TableSize(7) 17 x 3 x 16 Bits Two-WireData Rate PGA309 toEEPROM (SCL frequency) 65 kHz Logic Levels InputLevels(SDA, SCL, PRG, TEST) Low 0.2•VSD V InputLevels(SDA, SCL, PRG, TEST) High 0.7•VSD V InputLevels(SDA, SCL) Hysteresis 0.1•VSD V Pull-UpCurrentSource(SDA, SCL) 55 85 125 mA Pull-DownCurrentSource(TEST) 15 25 40 mA OutputLOW Level(SDA, SCL, PRG) Open drain,ISINK = 5mA 0.4 V Power Supply VSA, VSD 2.7 5.5 V ISA + ISD ,QuiescentCurrent VSA = VSD = +5V, withoutbridgeload 1.2 1.6 mA Power-On Reset (POR) Power-Up Threshold VS rising 2.2 2.7 V Power-Down Threshold VS falling 1.7 V Temperature Range SpecifiedPerformanceRange –40 +125 °C Operational-DegradedPerformanceRange –55 +150 °C (7) Lookup tableallowsmultislopecompensationovertemperature.Lookup tablehas accessto17 calibrationpointsconsistingofthree adjustmentvalues(Tx,Temperature,ZMx, ZeroDAC, GMx, Gain DAC) thatarestoredin16-bitdataformat(17x3x16= Lookup table size). Copyright© 2003–2011,Texas InstrumentsIncorporated SubmitDocumentationFeedback 7 ProductFolderLink(s):PGA309

SBOS292C –DECEMBER 2003–REVISED JANUARY 2011 www.ti.com PIN CONFIGURATION PW PACKAGE TSSOP-16 (TOP VIEW) PIN DESCRIPTIONS PIN NO. NAME DESCRIPTION Bridgesensorexcitation.Connecttobridgeiflinearizationand/orinternalreferenceforbridgeexcitation1 VEXC istobe used. 2 GND A Analogground.ConnecttoanaloggroundreturnpathforVSA .Shouldbe same as GND D . 3 VSA Analogvoltagesupply.Connecttoanalogvoltagesupply.To be within200mV ofVSD . Signalinputvoltage1.Connectto+ or– outputofsensorbridge.Internalmultiplexercan change4 VIN1 connectioninternallytoFront-EndPGA. Signalinputvoltage2.Connectto+ or– outputofsensorbridge.Internalmultiplexercan change5 VIN2 connectioninternallytoFront-EndPGA. VOUT feedbackpin.Voltagefeedbacksense pointforover/under-scalelimitcircuitry.When internalgain setresistorsfortheoutputamplifierareused,thisisalsothevoltagefeedbacksense pointforthe 6 VFB outputamplifier.VFB incombinationwithVSJ allowsforease ofexternalfilterand protectioncircuits withoutdegradingthePGA309 VOUT accuracy.VFB must alwaysbe connectedtoeitherVOUT orthe pointoffeedbackforVOUT ,ifexternalprotectionisused. 7 VOUT Analogoutputvoltageofconditionedsensor. Outputamplifiersumming junction.Use foroutputamplifiercompensationwhen drivinglargecapacitive8 VSJ loads(> 100pF)and/orforusingexternalgainsettingresistorsfortheoutputamplifier. 9 TEST Test/Externalcontrollermode pin.PulltoGND D innormalmode. 10 VSD Digitalvoltagesupply.Connecttodigitalvoltagesupply.To be within200mV ofVSA . 11 GND D Digitalground.ConnecttodigitalgroundreturnpathforVSD .Shouldbe same as GND A. Single-wireinterfaceprogrampin.UART-type interfacefordigitalcalibrationofthePGA309 overa 12 PRG singlewire.Can be connectedtoVOUT fora three-lead(VS,GND, VOUT )digitally-programmablesensor assembly. Clockinput/outputforTwo-Wire,industry-standardcompatibleinterfaceforreadingand writingdigital 13 SCL calibrationand configurationfromexternalEEPROM. Can alsocommunicatedirectlytotheregistersin thePGA309 throughtheTwo-Wire,industry-standardcompatibleinterface. Data input/outputforTwo-Wire,industry-standardcompatibleinterfaceforreadingand writingdigital 14 SDA calibrationand configurationfromexternalEEPROM. Can alsocommunicatedirectlytotheregistersin thePGA309 throughtheTwo-Wire,industry-standardcompatibleinterface. Externaltemperaturesignalinput.PGA309 can be configuredtoreada bridgecurrentsense resistor as an indicatorofbridgetemperature,oran externaltemperaturesensingdevicesuch as diode junction,RTD, orthermistor.Thisinputcan be internallygainedby 1,2,4,or8.Inaddition,thisinput15 TEMP IN can be readdifferentiallywithrespecttoVGNDA ,VEXC ,ortheinternal/externalVREF .Thereisalsoan internal,register-selectable,7mA currentsource(ITEMP )thatcan be connectedtoTEMP IN as an RTD, thermistor,ordiodeexcitationsource. Referenceinput/outputpin.As an output,theinternalreference(selectableas 2.5Vor4.096V)is 16 REF IN/REFOUT availableforsystemuse on thispin.As an input,theinternalreferencemay be disabledand an externalreferencecan thenbe appliedas thereferenceforthePGA309.

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4.090 4.085 4.080 4.075 4.070 4.065 4.060 T emperature ( C)/c176 /c45 55 /c45 35 /c45 15 5 25 45 65 85 105 125 145 V REF (V) T emperature ( C)/c176 /c45 55 /c45 35 /c45 15 5 25 45 65 85 105 125 145 1.0 0.5 /c45 0.5 /c45 1.0 /c45 1.5 /c45 2.0 /c45 2.5 /c45 3.0 Average, nA I (nA)B T emperature ( C)/c176 /c45 55 /c45 35 /c45 15 5 25 45 65 85 105 125 145 Average I ( A) /c109 TEMP /c4510 /c4520 /c4530 Frequency (Hz) CMRR (dB) 10 100 1k 10k 100k 1M RTO of Front- End PGA /c4510 Frequency (Hz) PSRR (dB) 10 100 1k 10k 100k 1M Small-Signal V and V Enabled V = 2.5V PSRR at V REF EXT REF OUT Frequency (Hz) Gain (dB) 10 100 1k 10k 100k 1M G = Output Amplifier GainOUTAMP G = 9V/V G = 128V/V OUTAMP FRONT G = 9V/V G = 32V/V OUTAMP FRONT G = 2V/V G = 32V/V OUTAMP FRONT G = 2V/V G = 8V/V OUTAMP FRONT PGA309 www.ti.com SBOS292C –DECEMBER 2003–REVISED JANUARY 2011 TYPICAL CHARACTERISTICS AtTA = +25°C, VSA = VSD = +5V (VSA = VSUPPLY ANALOG ,VSD = VSUPPLY DIGITAL,VSA must equalVSD ),GND D = GND A = 0,and VREF = REF IN/REFOUT = +5V, unlessotherwisenoted. VREF vs TEMPERATURE IB CURRENT vs TEMPERATURE Figure1. Figure2. ITEMP CURRENT vs TEMPERATURE COMMON-MODE REJECTION RATIO vs FREQUENCY Figure3. Figure4. POWER-SUPPLY REJECTION RATIO vs FREQUENCY CLOSED −LOOP GAIN vs FREQUENCY Figure5. Figure6. Copyright© 2003–2011,Texas InstrumentsIncorporated SubmitDocumentationFeedback 9 ProductFolderLink(s):PGA309

V 0.1S S S S S /c45 /c45 /c45 /c45 /c45 V 0.2 V 0.3 V 0.4 V 0.5 0.5 0.4 0.3 0.2 0.1 VS = 2.7V V = 2.7VS V = 5VS V = 5VS I (mA)LOAD T emperature ( C)/c176 /c45 55 /c45 35 /c45 15 5 25 45 65 85 105 125 145 1.6 1.4 1.2 1.0 0.8 0.6 0.4 0.2 All Blocks Enabled Ref, Exc, and ADC DisabledI (mA)Q /c45100 /c4580 /c4560 /c4540 /c4520 0 20 40 60 80 100 0.4 0.3 0.2 0.1 /c450.1 /c450.2 /c450.3 /c450.4 T otal Error (% of FS) Input Signal (% FS of V )REF Reg 6 = 0433h V = 2.5V Internal 15-Bit + Sign REF Reg 6 = 0430h V = 2.5V Internal 11-Bit + Sign REF Reg 6 = 0403h V = 5V Internal 15-Bit + Sign REF Reg 6 = 0503h V = 2.048V Internal (T emp ADC Internal) 15-Bit + Sign REF Actual Die T emperature ( C)/c176 /c45 55 /c45 35 /c45 15 5 25 45 65 85 105 125 145 0.4 0.2 /c45 0.2 /c45 0.4 /c45 0.6 /c45 0.8 /c45 1.0 /c45 1.2 T emp ADC Error ( C) /c176 1s/div

50 V/div

/c109 Measured After Bandpass Filter 0.1Hz Second-Order High-Pass 10Hz Fourth-Order Low-Pass V = 4.096VREF 1s/div 1mV/div Measured After Bandpass Filter 0.1Hz Second-Order High-Pass 10Hz Fourth-Order Low-Pass V = +61mV CLK_CFG = 00 (default) IN G = 1152 Coarse Offset = 59mV/c45 PGA309 SBOS292C –DECEMBER 2003–REVISED JANUARY 2011 www.ti.com TYPICAL CHARACTERISTICS (continued) AtTA = +25°C, VSA = VSD = +5V (VSA = VSUPPLY ANALOG ,VSD = VSUPPLY DIGITAL,VSA must equalVSD ),GND D = GND A = 0,and VREF = REF IN/REFOUT = +5V, unlessotherwisenoted. VOUT SWING TO RAIL vs ILOAD IQ vs TEMPERATURE Figure7. Figure8. TEMPERATURE ADC ERROR (INTERNAL MODE) TEMPERATURE ADC ERROR (EXTERNAL MODES) Figure9. Figure10. VREF NOISE VOUT NOISE (0.1HzTO 10Hz) (0.1HzTO 10Hz PEAK-TO-PEAK NOISE) Figure11. Figure12.

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0.1 0.01 10 100 Frequency (Hz) e ( V/ ), RTI /c109 ND Hz/c214 Coarse Offset Adjust = 59mV V = +61mV CLK_CFG = 00 (default) /c45 IN 10k 100k1k1 0.1 0.01 10 100 Frequency (Hz) e ( V/ ), RTI /c109 ND Hz/c214 Coarse Offset Adjust = 0mV CLK_CFG = 00 (default) Time (10 s/div)/c109 Gain = 8 V (500mV/div) OUT Gain = 1152 Time (10 s/div)/c109 V (500mV/div) OUT Gain = 8 Time (10 s/div)/c109 V (50mV/div) OUT Gain = 256 Time (10 s/div)/c109 V (50mV/div) OUT PGA309 www.ti.com SBOS292C –DECEMBER 2003–REVISED JANUARY 2011 TYPICAL CHARACTERISTICS (continued) AtTA = +25°C, VSA = VSD = +5V (VSA = VSUPPLY ANALOG ,VSD = VSUPPLY DIGITAL,VSA must equalVSD ),GND D = GND A = 0,and VREF = REF IN/REFOUT = +5V, unlessotherwisenoted. INPUT VOLTAGE NOISE DENSITY INPUT VOLTAGE NOISE DENSITY Figure13. Figure14. LARGE-SIGNAL STEP RESPONSE LARGE-SIGNAL STEP RESPONSE Figure15. Figure16. SMALL-SIGNAL STEP RESPONSE SMALL-SIGNAL STEP RESPONSE Figure17. Figure18. Copyright© 2003–2011,Texas InstrumentsIncorporated SubmitDocumentationFeedback 11 ProductFolderLink(s):PGA309

Time (100 s/div)/c109 V (200mV/div), V (1V/div) IN OUT VIN VOUT 0 500 1000 1500 2000 2500 0.5% Settling Time ( s) /c109 C (pF)LOAD G = 9V/VOUTAMP G = 3.6V/VOUTAMP G = 2V/VOUTAMP Frequency (Hz) Phase ( )/c176 10k 100k 1M 10M0.1 120 100 /c45 45 /c45 90 /c45 135 /c45 180 /c45 225 1 10 100 A (dB) OL C = 100pF R = 4.7k /c87 L L /c455 /c4510 /c4515 /c4520 Error (LSB) Code (LSB) 7000010000 20000 30000 40000 60000 500000 Unit 1 Unit 2 /c455 /c4510 /c4515 /c4520 Error (LSB) Code (LSB) 7000010000 20000 30000 40000 60000 500000 PGA309 SBOS292C –DECEMBER 2003–REVISED JANUARY 2011 www.ti.com TYPICAL CHARACTERISTICS (continued) AtTA = +25°C, VSA = VSD = +5V (VSA = VSUPPLY ANALOG ,VSD = VSUPPLY DIGITAL,VSA must equalVSD ),GND D = GND A = 0,and VREF = REF IN/REFOUT = +5V, unlessotherwisenoted. CAPACITIVE LOAD DRIVE OVERVOLTAGE RECOVERY Figure19. Figure20. OUTPUT AMPLIFIER OPEN-LOOP GAIN/PHASE vs FREQUENCY ZERO DAC TYPICAL ERROR vs CODE Figure21. Figure22. GAIN DAC TYPICAL ERROR vs CODE Figure23.

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www.ti.com SBOS292C –DECEMBER 2003–REVISED JANUARY 2011 FUNCTIONAL DESCRIPTION Converter(Temp ADC). In orderto compensate for second-orderand higherdriftnonlinearity,the spanOVERVIEW driftcan be fittedto piecewiselinearcurvesduringThe PGA309 is a programmable analog signal calibrationwiththe coefficientsstoredinan externalconditionerdesigned for resistivebridge sensor nonvolatileEEPROM lookuptable.applications.Itisa completesignalconditionerwith Followingthe finegain adjuststage is the Outputbridgeexcitation,initialspan and offsetadjustment, Amplifierthatprovidesadditionalprogrammablegain.temperature adjustment of span and offset, Two key outputamplifierconnections,VFB and VSJ,internal/externaltemperaturemeasurement capability, are brought out on the PGA309 for applicationoutput over-scaleand under-scalelimiting,fault flexibility.These connectionsallowforan accuratedetection,and digitalcalibration.The PGA309, in a conditionedsignalvoltagewhile also providingacalibratedsensor module, can reduce errorsto the means for PGA309 output overvoltageand largelevelapproachingthebridgesensorrepeatability.See capacitiveloadingforRFI/EMI filteringrequiredinFigure 24 for a block diagram of the PGA309. many end applications.Followingisa briefoverviewofeach majorfunction. OFFSET ADJUSTMENTSENSOR ERROR ADJUSTMENT RANGE The sensor offsetadjustmentis performed in twoThe adjustment capabilityof the PGA309 is stages.The input-referredCoarse OffsetAdjustDACsummarized inTable1. has approximatelya ±60mV offsetadjustmentrange fora selectedVREF of 5V. The fineoffsetand theTable1.PGA309 Adjustment Capability offsetdriftare canceledby the16-bitZero DAC thatFSS (full-scalesensitivity) 1mV/V to245mV/V sums the signalwith the outputof the front-end Span TC Over ±3300ppmFS/ °C (1) instrumentationamplifier.Similarto the Gain DAC, Span TC nonlinearity ≥ 10% theinputdigitalvaluesoftheZeroDAC arecontrolled by the data in the Temperature CompensationZerooffset ±200%FS (2) Lookup Table,storedinexternalEEPROM, drivenbyZerooffsetTC Over ±3000ppmFS/ °C (2) theTemp ADC. The programming range oftheZeroZerooffsetTC nonlinearity ≥ 10% DAC is0V to VREF withan outputrange of 0.1V to Sensorimpedance Down to200Ω(3) VSA – 0.1V. 1. Depends on thetemperaturesensingscheme. VOLTAGE REFERENCE2. Combined coarseand fineoffsetadjust. The PGA309 containsa precisionlow-driftvoltage3. Lower impedance possibleby usinga dropping reference(selectablefor2.5V or4.096V)thatcan beresistorinserieswiththebridge. used forexternalcircuitrythroughtheREF IN/REFOUT pin.This same referenceis used forthe CoarseGAIN SCALING OffsetAdjust DAC, Zero DAC, Over/Under-Scale The coreofthePGA309 istheprecisionlow-driftand Limitsand sensorexcitation/linearizationthroughthe no 1/fnoiseFront-EndPGA. The overallgainofthe VEXC pin.When theinternalreferenceisdisabled,the Front-EndPGA + Output Amplifiercan be adjusted REF IN/REFOUT pin should be connected to an from 2.7V/V to 1152V/V. The polarityof the inputs externalreferenceor to VSA forratiometric-scaled can be switched through the 2x2 input mux to systems. accommodate sensorswithunknown polarityoutput. SENSOR EXCITATION AND LINEARIZATIONThe Front-EndPGA providesinitialcoarsesignalgain using a no 1/f noise, auto-zeroinstrumentation A dedicatedcircuitwitha 7-bit+ signDAC forsensor amplifier.The finegainadjustisaccomplishedby the voltageexcitationand linearizationisprovidedon the 16-bitattenuatingGain Digital-to-AnalogConverter PGA309. Thisblockscalesthereferencevoltageand (GainDAC). ThisGain DAC iscontrolledby thedata sums itwith a portionof the PGA309 outputto in the Temperature Compensation Lookup Table compensate the positiveor negativebow-shaped driven by the Temperature Analog-to-Digital nonlinearityexhibitedby many sensors over their applied pressure range. Sensors not requiring linearizationcan be connecteddirectlyto the supply (VSA ) or to the VEXC pinwiththe LinearizationDAC (LinDAC) settozero. Copyright© 2003–2011,Texas InstrumentsIncorporated SubmitDocumentationFeedback 13 ProductFolderLink(s):PGA309

SpanTC and OffsetTC Adjust Lookup T able with interpolation Output Coarse Gain Adjust (2 to 9) 2x2 Multiplexer Int/Ext Feedback PGA309 +5V T est Logic Fault Conditions Monitoring Circuit T emp ADC Signals Mux T emperature ADC Linearization DAC Fault Out Fine Gain Adjust Fine Offset Adjust Front-End PGA Out TEST Fault Out SDA SCL T emperature ADC Input Select Internal T emp Sense Zero DAC Gain DAC Output Amp +5V /c83 VSD VREF VFB VFB RTEMP GNDA GNDD VFB VSJ VOUT VEXC TEMPIN VIN1 VIN2 VTEMP VOS VOUT VOUT VOUT FILT KLIN KREF VSA REFIN/REFOUT RISO 100/c87 RFB 100/c87 Power-On Reset Band-Gap Voltage Reference T wo-Wire EEPROM (SOT23-5) Over-/Under- Scale Limits Front-End PGA (Gain 4 to 128) CL 10nF CF 150pF Bridge Sensor Coarse Offset Adjust PGA309 SBOS292C –DECEMBER 2003–REVISED JANUARY 2011 www.ti.com Figure24. SimplifiedDiagram ofthePGA309 ina TypicalConfiguration

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www.ti.com SBOS292C –DECEMBER 2003–REVISED JANUARY 2011 ADC FOR TEMPERATURE SENSING algorithmfor accurateDAC adjustmentsbetween storedtemperatureindexes.ThisapproachallowsforThe temperature sense circuitrydrives the a piecewiselineartemperaturecompensationofup tocompensationforthe sensor span and offsetdrift. 17 temperatureindexesand associatedtemperatureEitherinternalor externaltemperaturesensing is coefficients.possible.The temperaturecan be sensed inone of thefollowingways: If eitherChecksum1, Checksum2, or both are incorrect,the output of the PGA309 is set to• Bridge impedance change (excitationcurrent high-impedance.sense, in the positiveor negativepart of the bridge),for sensors with large temperature FAULT MONITORcoefficientofresistance(TCR > 0.1%/°C).

• On-chip PGA309 temperature,when the chip is To detectsensor burnoutor a short,a set of four locatedsufficientlyclosetothesensor. comparators are connected to the inputsof the Front-EndPGA. Ifany of the inputsare taken to• Externaldiode,thermistor,or RTD placedon the within100mV ofground or VEXC ,or violatetheinputsensormembrane. An internal7mA currentsource CMR of the Front-EndPGA, then the correspondingmay be enabled to excite these types of comparatorsetsa sensorfaultflagthatcauses thetemperaturesensors. PGA309 VOUT tobe drivenwithin100mV ofeitherVSAThe temperaturesignalis digitizedby the onboard or ground,depending upon the alarm configurationTemp ADC. The outputoftheTemp ADC isused by setting (Register 5— PGA Configuration andthe controldigitalcircuitto read the data from the Over/Under-ScaleLimit).Thiswillbe wellabove theLookup Table inan externalEEPROM, and setthe set Over-ScaleLimitlevelor well below the setoutputof the Gain DAC and the Zero DAC to the Under-Scale Limit level.The state of the faultcalibratedvaluesas temperaturechanges. conditioncan be read in digitalform in Register 8— Alarm StatusRegister.Ifthe Over/Under-ScaleAn additionalfunctionprovidedthroughthe Temp Limitisdisabled,thePGA309 outputvoltagewillstillADC istheabilitytoread theVOUT pinback through be drivenwithin100mV of eitherVSA or ground,theTemp ADC inputmux. Thisprovidesflexibilityfor dependingupon thealarmconfigurationsetting.a digitaloutputthrougheitherOne-Wire or Two-Wire interface,as wellas the possibilityforan external There are fiveotherfaultdetectcomparatorsthatmicrocontrollerto perform real-time custom help detectsubtlePGA309 front-endviolationsthatcalibrationofthePGA309. couldotherwiseresultinlinearvoltagesatVOUT that would be interpretedas validstates.These areEXTERNAL EEPROM AND TEMPERATURE especiallyusefulduringfactorycalibrationand setup,COEFFICIENTS and are configured through Register 5— PGA Configurationand Over/Under-Scale Limit.TheThe PGA309 uses an industry-standardTwo-Wire respectivestatusof each can also be read backexternalEEPROM (typically,a SOT23-5 package).A throughRegister8— AlarmStatusRegister.1k-bit(minimum)EEPROM isneeded when usingall 17 temperaturecoefficients.LargerEEPROMs may OVER-SCALE AND UNDER-SCALE LIMITSEbe used to providespace fora serialnumber, lot code,orotherdata. The over-scale and under-scale limitcircuitry combined withthe faultmonitorcircuitryprovidesaThe firstpartof the externalEEPROM containsthe means for system diagnostics. A typicalconfigurationdataforthePGA309, withsettingsfor: sensor-conditionedoutputmay be scaledfor10% to• Register3— ReferenceControland Linearization 90% ofthesystem ADC rangeforthesensornormal• Register4— PGA Coarse Offsetand Gain/Output operatingrange.IftheconditionedpressuresensorisAmplifierGain below 4%, itis consideredunder-pressure;ifover
• Register 5— PGA Configuration and 96%, itisconsideredover-pressure. Over/Under-ScaleLimit The PGA309 over/under-scalelimitcircuitcan be• Register6— Temp ADC Control programmed individuallyfor under-scale and This sectionof the EEPROM containsits own over-scalevaluesthatcliporlimitthePGA309 output. individualchecksum (Checksum1). From a system diagnosticview,10% to90% ofADC range is normal operation,less than 4% isThe second partof the externalEEPROM contains under-pressure, and greater than 96% isup to17 temperatureindexvaluesand corresponding over-pressure.Ifthe faultdetectcircuitryisused,atemperaturecoefficientsforthe Zero DAC and Gain detectedfaultwillcause the PGA309 outputto beDAC adjustmentswithmeasured temperature,and driventopositiveornegativesaturation.alsocontainsitsown checksum (Checksum2).The PGA309 lookuplogiccontainsa linearinterpolation Copyright© 2003–2011,Texas InstrumentsIncorporated SubmitDocumentationFeedback 15 ProductFolderLink(s):PGA309

V = mux_sign V + V GI + V GD GOOUT IN Coarse_Offset Zero_DAC[ ] /c63 /c63 /c63 /c63( ( PGA309 SBOS292C –DECEMBER 2003–REVISED JANUARY 2011 www.ti.com Ifthisfaultflagisprogrammed forhigh,thengreater DIGITAL INTERFACE interface.Communication to the PGA309 internalPOWER-UP AND NORMAL OPERATION registers,as wellas to the externalEEPROM, for programming and readback can be conductedThe PGA309 has circuitryto detectwhen the power througheitherdigitalinterface.supply is appliedto the PGA309, and reset the PGA309 triggersthe Temp ADC to measure PGA309 TRANSFER FUNCTIONtemperature.For 16-bit resolutionresults,the convertertakesapproximately125ms to completea Equation1 shows themathematicalexpressionthatis conversion.Once the conversionis complete,the used to compute the output voltage,VOUT . This PGA309 beginsreadingtheLookup Tableinformation equationcan also be rearrangedalgebraicallyto from the EEPROM (second part)to calculatethe solve for differentterms. For example, during settingsfortheGain DAC and ZeroDAC. calibration,thisequationis rearrangedto solvefor VIN.The PGA309 readstheentireLookup Tableso thatit can determineifthechecksum fortheLookup Table (Checksum2) is correct.Each entryin the Lookup (1) Tablerequiresapproximately500ms toread from the Where:EEPROM. Once the checksum isdeterminedto be valid,the calculatedvaluesforthe Gain and Zero mux_sign: Thisterm changes thepolarityofthe DACs areupdatedintotheirrespectiveregisters,and inputsignal;valueis±1. the outputamplifieris enabled.The PGA309 then VIN:The inputsignalforthePGA309; VIN1 = VINP, beginsloopingthroughthisentireprocedure,starting VIN2 = VINN. with reading the EEPROM configurationregisters VCoarse_Offset: The coarse offsetDAC outputfrom the firstpartof the EEPROM, then startinga voltage.new conversionon the Temp ADC, which then GI:Inputstagegain.triggersreadingthe Lookup Table data from the VZero_DAC :ZeroDAC outputvoltage.second partof the EEPROM. This loop continues indefinitely. GD: Gain DAC. GO: Outputstagegain.

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R R Auto Zero Auto Zero R Auto Zero PGA Diff Amp xG Bandgap Reference POR PGA Gain Select (1 of 8) Range of 4 to 128 (with PGA Diff Amp Gain = 4) RGO Output Gain Select (1 of 7) Range of 2 to 9 Digital Controls SCL PRG SDA x0.52 x0.83 x0.124 x0.166 INT/EXT FB Select Alarm Register Inputs T emp ADC Ref Mux T emp ADC Internal REFInternal T emp Sense 16 3 10 112 1 /c83 Fault Monitor Circuit T est Logic T emp ADC Input Mux T emp ADC REF Select T emp Select Source T emp ADC, PGA (x1, x2, x4, x8) T emp ADC Input Mux Select Interface and Control Circuitry Control Registers Alarm Register Offset TC Adjust and Scan TC Adjust Look-Up Logic with Interpolation Algorithm Output Amplifier Input Mux Input Mux Control Coarse Offset Adjust Fine Offset Adjust Fine Gain Adjust (16-Bit) TEST RFO PGA309 VEXC VEXC VSA VFB VSA VSA VSD VSD VREFT VREF RF RF RG VREF VREF VREF VFB VFB VOUT VSJ VIN2 VIN1 GNDA GNDD VOUT VINP VINN VREF VREF VEXC VEXC VOUT VSA ITEMP

7 A/c109

I EnableTEMP V Internal Set (2.5V or 4.096V) REF V Internal Set (2.5V or 4.096V) REF V EnableEXC REF /REFIN OUT TEMPIN TEMPIN 7-Bit + Sign Lin DAC 15-Bit + Sign T emp ADC Linearization and V Gain Adjust EXC VREF RSET Gain DAC 3-Bit DAC Scale Limiter 3-Bit DAC Over-Scale Limit Under-Scale Limit Front-End PGA Output Front-End PGA PGA309 www.ti.com SBOS292C –DECEMBER 2003–REVISED JANUARY 2011 Figure25. DetailedBlock Diagram Copyright© 2003–2011,Texas InstrumentsIncorporated SubmitDocumentationFeedback 17 ProductFolderLink(s):PGA309

SBOS292C –DECEMBER 2003–REVISED JANUARY 2011 www.ti.com

REVISION HISTORY

NOTE: Page numbers forpreviousrevisionsmay differfrompage numbers inthecurrentversion. Changes from RevisionB (January,2005)toRevisionC Page

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www.ti.com 23-May-2025 PACKAGING INFORMATION Orderable part number Status (1) Material type (2) Package | Pins Package qty | Carrier RoHS (3) Lead finish/ Ball material (4) MSL rating/ Peak reflow (5) Op temp (°C) Part marking (6) PGA309AIPWR Active Production TSSOP (PW) | 16 2500 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 125 PGA 309A PGA309AIPWR.B Active Production TSSOP (PW) | 16 2500 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 125 PGA 309A PGA309AIPWRG4.B Active Production TSSOP (PW) | 16 2500 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 125 PGA 309A PGA309AIPWT Active Production TSSOP (PW) | 16 250 | SMALL T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 125 PGA 309A PGA309AIPWT.B Active Production TSSOP (PW) | 16 250 | SMALL T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 125 PGA 309A PGA309AIPWTG4 Active Production TSSOP (PW) | 16 250 | SMALL T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 125 PGA 309A (1) Status: For more details on status, see our product life cycle. (2) Material type: When designated, preproduction parts are prototypes/experimental devices, and are not yet approved or released for full production. Testing and final process, including without limitation quality assurance, reliability performance testing, and/or process qualification, may not yet be complete, and this item is subject to further changes or possible discontinuation. If available for ordering, purchases will be subject to an additional waiver at checkout, and are intended for early internal evaluation purposes only. These items are sold without warranties of any kind. (3) RoHS values: Yes, No, RoHS Exempt. See the TI RoHS Statement for additional information and value definition. (4) Lead finish/Ball material: Parts may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two lines if the finish value exceeds the maximum column width. (5) MSL rating/Peak reflow: The moisture sensitivity level ratings and peak solder (reflow) temperatures. In the event that a part has multiple moisture sensitivity ratings, only the lowest level per JEDEC standards is shown. Refer to the shipping label for the actual reflow temperature that will be used to mount the part to the printed circuit board. (6) Part marking: There may be an additional marking, which relates to the logo, the lot trace code information, or the environmental category of the part. Multiple part markings will be inside parentheses. Only one part marking contained in parentheses and separated by a "~" will appear on a part. If a line is indented then it is a continuation of the previous line and the two combined represent the entire part marking for that device. Addendum-Page 1

www.ti.com 23-May-2025 Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. OTHER QUALIFIED VERSIONS OF PGA309 : NOTE: Qualified Version Definitions: Addendum-Page 2

PACKAGE MATERIALS INFORMATION www.ti.com 3-Jun-2022 TAPE AND REEL INFORMATION Reel Width (W1) REEL DIMENSIONS A0B0K0WDimension designed to accommodate the component lengthDimension designed to accommodate the component thicknessOverall width of the carrier tapePitch between successive cavity centersDimension designed to accommodate the component width TAPE DIMENSIONSK0 P1B0WA0Cavity QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE Pocket QuadrantsSprocket HolesQ1Q1Q2Q2Q3Q3Q4Q4User Direction of Feed P1ReelDiameter *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Reel Diameter (mm) Reel Width W1 (mm) (mm) (mm) (mm) (mm) W (mm) Pin1 Quadrant Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION www.ti.com 3-Jun-2022 TAPE AND REEL BOX DIMENSIONS Width (mm) W LH *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) PGA309AIPWR TSSOP PW 16 2500 356.0 356.0 35.0 PGA309AIPWT TSSOP PW 16 250 210.0 185.0 35.0 Pack Materials-Page 2

www.ti.com PACKAGE OUTLINE C 14X 0.65 4.55 16X 0.30 0.19 TYP6.6 6.2

1.2 MAX

0.15 0.05 0.25 GAGE PLANE -80 B NOTE 4 4.5 4.3 A NOTE 3 5.1 4.9 0.75 0.50 (0.15) TYP TSSOP - 1.2 mm max heightPW0016A SMALL OUTLINE PACKAGE 4220204/A 02/2017

0.1 C A B

0.1 C NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed 0.15 mm per side. 4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side. 5. Reference JEDEC registration MO-153. SEATING PLANE A 20 DETAIL A TYPICAL SCALE 2.500

www.ti.com EXAMPLE BOARD LAYOUT

0.05 MAX

0.05 MIN

16X (1.5) 16X (0.45) 14X (0.65) (5.8) (R0.05) TYP TSSOP - 1.2 mm max heightPW0016A SMALL OUTLINE PACKAGE 4220204/A 02/2017 NOTES: (continued) 6. Publication IPC-7351 may have alternate designs. 7. Solder mask tolerances between and around signal pads can vary based on board fabrication site. LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE: 10X SYMM SYMM 8 9 15.000 METALSOLDER MASK OPENING METAL UNDER SOLDER MASK SOLDER MASK OPENING EXPOSED METALEXPOSED METAL SOLDER MASK DETAILS NON-SOLDER MASK DEFINED (PREFERRED) SOLDER MASK DEFINED

www.ti.com EXAMPLE STENCIL DESIGN 16X (1.5) 16X (0.45) 14X (0.65) (5.8) (R0.05) TYP TSSOP - 1.2 mm max heightPW0016A SMALL OUTLINE PACKAGE 4220204/A 02/2017 NOTES: (continued) 8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 9. Board assembly site may have different recommendations for stencil design. SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL SCALE: 10X SYMM SYMM 8 9

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