PGA308AIDRKR

PGA308_16 TI1 | Alldatasheet

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Gain□Select VIN1 5 VREF VS VIN2 Auto-Zero PGA 7-Bit□+□Sign DAC PGA308 16-Bit DAC Output Amplifier NOTE: (1)□Ref□=□V or□V selectable.REF S VEXC VREF VFB 4 10 1 VOUT VSJ GND Input Mux Scale Limit 1WDigital□Interface (One-Wire) OTP (7□Banks) RAM Coarse□Offset VREF VREF 16-Bit DAC Ref(1) Ref(1) Fine□Offset Output□Gain Fine□Gain Output Gain Select DOUT Select 3-Bit DAC Underscale 3-Bit DAC Overscale D /VOUT CLAMP Bridge Sensor PGA308 www.ti.com SBOS440B –JULY 2008–REVISED DECEMBER 2010 Single-Supply,Auto-ZeroSensorAmplifier withProgrammableGainandOffset Check forSamples: PGA308 1FEATURES DESCRIPTION 2• DigitalCalibrationforBridgeSensors The PGA308 isa programmableanalogsensorsignal conditioner.The analog signalpath amplifiesthe• OffsetSelect:Coarse and Fine sensorsignaland providesdigitalcalibrationforoffset• Gain Select:Coarse and Fine and gain.Calibrationisdone viathe1W pin,a digital• BridgeFaultMonitor One-Wire, UART-compatible interface. For

• InputMux forLead Swap three-terminalsensor modules, 1W may be connected to VOUT and the assembly programmed• Over/Under ScaleLimits through the VOUT pin.Gain and offsetcalibration• D OUT /VOUT Clamp Function parametersare storedonboard in seven banks of
• Seven Banks OTP Memory one-time programmable (OTP) memory. The power-on reset (POR) OTP bank may be• One-Wire DigitalUART Interface programmed a totaloffourtimes.• OperatingVoltage:+2.7V to+5.5V The all-analogsignalpath containsa 2×2 input• Temperature Range: –40°C to+125°C multiplexer(mux) to allow electronicsensor lead• MSOP-10 and 3mm × 4mm DFN-10 Packages swapping, a coarse offsetadjust,an auto-zero programmable gain instrumentationamplifier(PGA), APPLICATIONS a fine gain adjust,a fine offsetadjust,and a programmable gain outputamplifier.Faultmonitor• BridgeSensors circuitrydetects and signals sensor burnout,• Remote 4-20mA Transmitters overload, and system fault conditions.• Strain,Load, Weigh Scales Over/under-scalelimitsprovideadditionalmeans for• Automotive Sensors system leveldiagnostics.The dual-useD OUT /VCLAMP pincan be used as a programmable digitaloutputor EVALUATION TOOLS as a VOUT over-voltageclamp.
• PGA308EVM (Hardware and Software) For detailedapplicationinformation,see thePGA308 – Calibrationand Configuration User's Guide (SBOU069) availablefordownload at – Sensor Emulation www.ti.com. Pleasebe aware thatan importantnoticeconcerningavailability,standardwarranty,and use incriticalapplicationsofTexas Instrumentssemiconductorproductsand disclaimerstheretoappearsattheend ofthisdatasheet. 2Alltrademarksarethepropertyoftheirrespectiveowners. PRODUCTION DATA informationiscurrentas ofpublicationdate. Copyright© 2008–2010,Texas InstrumentsIncorporatedProductsconform to specificationsper the terms of the Texas Instrumentsstandardwarranty.Productionprocessingdoes not necessarilyincludetestingofallparameters.

SBOS440B –JULY 2008–REVISED DECEMBER 2010 www.ti.com This integratedcircuitcan be damaged by ESD. Texas Instrumentsrecommends thatallintegratedcircuitsbe handled with appropriateprecautions.Failuretoobserveproperhandlingand installationprocedurescan cause damage. ESD damage can rangefromsubtleperformancedegradationtocompletedevicefailure.Precisionintegratedcircuitsmay be more susceptibletodamage because verysmallparametricchanges couldcause thedevicenottomeet itspublishedspecifications. PACKAGE/ORDERING INFORMATION (1) PACKAGE PACKAGE PRODUCT PACKAGE-LEAD DESIGNATOR MARKING MSOP-10 DGS P30A PGA308 3mm × 4mm DFN-10 DRK P30B (1) Forthemost currentpackage and orderinginformationsee thePackage OptionAddendum attheend ofthisdocument,orsee theTI web siteatwww.ti.com. ABSOLUTE MAXIMUM RATINGS (1) Over operatingfree-airtemperaturerange,unlessotherwisenoted. PARAMETER PGA308 UNIT SupplyVoltage,VS +5.5 V D OUT /VCLAMP OutputCurrentLimit ±10 mA InputCurrent –10 to+10 mA VIN1,VIN2,VREF ,1W, D OUT /VCLAMP ,VSJ (2) GND – 0.3toVS + 0.3 V PinProtection VFB TerminalVoltage –30 to30 V VFB TerminalCurrent –10 to10 mA VOUT –160 to160 mA OperatingTemperatureRange –40 to+150 °C StorageTemperatureRange –55 to+150 °C JunctionTemperature +165 °C ESD Ratings Human Body Model (HBM) 2000 V (1) Stressesabove theseratingsmay cause permanentdamage. Exposuretoabsolutemaximum conditionsforextendedperiodsmay degradedevicereliability.These arestressratingsonly,and functionaloperationofthedeviceattheseorany otherconditionsbeyond thosespecifiedisnotimplied. (2) Terminalsarediode-clampedtothepower-supplyrails,VS and GND. Limitcurrentto10mA orless.

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www.ti.com SBOS440B –JULY 2008–REVISED DECEMBER 2010

ELECTRICAL CHARACTERISTICS

Boldfacelimitsapplyoverthespecifiedtemperaturerange,TA = –40°C to+125°C. AtTA = +25°C, VS = +5V, GND = 0V,D OUT /VCLAMP = +5V, and VREF = +5V, unlessotherwisenoted. PGA308 PARAMETER CONDITIONS MIN TYP MAX UNIT VOUT /VIN DifferentialSignalGains (1) Front-EndPGA gains(GF):4,6,8,12,16,32,64,100,200, 2.67 9600 (Front-EndPGA + OutputAmplifier) 400,480,600,800,960,1200,1600 V/VOutputAmplifiergains:2,2.4,3,3.6,4,4.5,6 FineGain Adjust= 0.33to1 VOUT /VIN Slew Rate CMP_SEL [CFG1 register]= 0 0.6 V/ms(Front-EndPGA + OutputAmplifier) CMP_SEL [CFG1 register]= 1 0.3 V/ms VOUT /VIN SettlingTime (0.01%FSR) VOUT /VIN differentialgain= 8, 13 ms(Front-EndPGA + OutputAmplifier) VOUT = +0.5V to+4.5V step,comp off,no capacitiveload VOUT /VIN differentialgain= 200, 15 msVOUT = +0.5V to+4.5V step,comp off,no capacitiveload ExternalSensor Output Sensitivity(2) VS = VREF = VCLAMP = +5V 0.08 296 mV/V FRONT-END PGA Auto-ZeroInternalFrequency 40 kHz OffsetVoltage(RTI)(3) Coarse OffsetAdjustdisabled ±5 ±40 mV vs Temperature Coarse OffsetAdjustdisabled ±0.2 mV/°C vs SupplyVoltage,VS Coarse OffsetAdjustdisabled 2 + 150/GF 10 + 1000/GF mV/V vs Common-Mode Voltage G F = Front-EndPGA gain, 1 + 250/GF 10 + 2000/GF mV/V Coarse OffsetAdjustdisabled OffsetVoltageProgramming Range (RTI)(3) Coarse OffsetAdjustenabled, –100 100 mV Coarse OffsetAdjustcontrolsoffset vs Temperature Coarse OffsetAdjustenabled ±0.2 mV/°C vs SupplyVoltage,VS Coarse OffsetAdjustenabled 2 + 150/GF mV/V vs Common-Mode Voltage G F = Front-EndPGA gain, 1 + 250/GF mV/V Coarse OffsetAdjustenabled LinearInputVoltageRange (4) 0.2 VS – 1.4 V InputBiasCurrent ±0.3 ±1.5 nA vs Temperature 10 pA/°C InputOffsetCurrent ±0.1 ±1.5 nA vs Temperature 10 pA/°C InputImpedance:Differential 30 ∥ 6 G Ω ∥ pF InputImpedance:Common-Mode 50 ∥ 20 G Ω ∥ pF InputVoltageNoise RTI,dc to10Hz,G F = 100,R S = 0Ω 1.2 mVPP InputVoltageNoiseDensity RTI,voltagenoisedensity,f= 1kHz,Coarse OffsetAdjust= 50 nV/√Hz RTI,voltagenoisedensity,f= 1kHz, 80 nV/√Hz Coarse OffsetAdjust= 100mV InputEMI FilterFrequency f3dB InputEMI filtertoGND, VIN1 and VIN2 40 MHz PGA Gain(5) Gain Range Steps 4,6,8,12,16,32,64,100,200,400,480,600,800,960, 4 1600 V/V 1200,1600 InitialGain Error G F ≤ 16 ±0.03 ±0.25 % 600 ≤ G F ≤ 1600 ±0.3 ±1 % vs Temperature 6 ppm/ °C OutputVoltageRange 0.05 VS – 0.05 V Bandwidth G F = 4 400 kHz G F = 1600 10 kHz (1) PGA308 totaldifferentialgainfrominput(VIN1 – VIN2)tooutput(VOUT ):VOUT /(VIN1 – VIN2)= (PGA gain)× (outputamplifiergain)× (fine gainadjust)withoutputamplifierinternalgainsused. (2) Based on bridgesensorexcitationvoltageof+5V and PGA308 outputvoltagespan of4V.Individualapplicationsmust considernoise, small-signalbandwidth,and requiredsystemerrortoassessifthePGA308 willwork fora givensensorsensitivity. (3) RTI = Referred-to-input. (4) Linearinputrangeistheallowedmin/max voltageon theVIN1 and VIN2 pinsforthefront-endPGA tocontinuetooperateina linear region.The allowedcommon-mode and differentialvoltagedepends on gainand offsetsettings.RefertothePGA308 User's Guide (SBOU069), formore information. (5) IREF currentloadistypically100mA whileinShutdown mode. AlthoughtheoutputamplifierisdisabledinShutdown mode, RFO and RGO (180kΩ typicaltotal)remainconnectedinseriesbetween VFB and GND whileinShutdown mode. See Figure37,DetailedBlock Diagram,formore information. Copyright© 2008–2010,Texas InstrumentsIncorporated SubmitDocumentationFeedback 3 ProductFolderLink(s):PGA308

SBOS440B –JULY 2008–REVISED DECEMBER 2010 www.ti.com ELECTRICAL CHARACTERISTICS (continued) Boldfacelimitsapplyoverthespecifiedtemperaturerange,TA = –40°C to+125°C. AtTA = +25°C, VS = +5V, GND = 0V,D OUT /VCLAMP = +5V, and VREF = +5V, unlessotherwisenoted. PGA308 PARAMETER CONDITIONS MIN TYP MAX UNIT Coarse OffsetAdjust (RTIofFront-EndPGA) (6) Range VREF = +5V –100 +100 mV Resolution 7 bit+ sign,VREF = +5V 1 mV PSRR 2 mV/V CMRR 1 mV/V Drift Coarse OffsetAdjust= 100mV 1.2 mV/°C FineOffsetAdjust(ZeroDAC) Programming Range RTO ofFront-EndPGA –0.5VREF +0.5VREF V OutputVoltageRange 0.1 VS – 0.1 V Resolution 65,536steps,16-bitDAC, VREF = +5V 76 mV IntegralNonlinearity ±6 LSB DifferentialNonlinearity ±0.5 LSB Gain Error ±0.5 % Gain ErrorDrift ±4 ppm/ °C Offset ±4 mV OffsetDrift ±10 mV/°C PSRR ±200 mV/V Output Amplifier Output FineGain Adjust(GainDAC) Range 0.33 1 V/V Resolution 65,536steps,16-bitDAC 10 mV/V IntegralNonlinearity ±6 LSB DifferentialNonlinearity ±0.5 LSB Gain Error ±0.2 % Gain Drift 3 ppm/ °C Output Amplifier OffsetVoltage(RTIofOutputAmplifier)(6) ±3 mV vs Temperature ±5 mV/°C vs SupplyVoltage,VS ±100 mV/V Common-Mode InputRange 0 VS – 1.5 V InputBiasCurrent ±100 pA AmplifierInternalGain Gain Range Steps 2,2.4,3,3.6,4,4.5,6 2 6 V/V InitialGain Error ±0.05 ±0.25 % vs Temperature ±1 ppm/ °C OutputVoltageRange IOUT = 0.5mA (7) 0.03 VS – 0.06 V IOUT = 4mA (7) 0.1 VS – 0.1 V OutputShort-CircuitCurrent ISC Sourcing/sinking 10 mA Open-Loop Gain at0.1Hz 106 dB Gain-BandwidthProduct 2 MHz Phase Margin Gain = 2,C L = 200pF 45 deg OutputResistance R O AC small-signal,open-loop,f= 1MHz, IOUT = 0,see 500 Ω Figure28 (6) RTI = Referred-to-input. (7) Unlesslimitedby theover/under-scalesetting,orVCLAMP pin.

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www.ti.com SBOS440B –JULY 2008–REVISED DECEMBER 2010 ELECTRICAL CHARACTERISTICS (continued) Boldfacelimitsapplyoverthespecifiedtemperaturerange,TA = –40°C to+125°C. AtTA = +25°C, VS = +5V, GND = 0V,D OUT /VCLAMP = +5V, and VREF = +5V, unlessotherwisenoted. PGA308 PARAMETER CONDITIONS MIN TYP MAX UNIT Over-and Under-ScaleLimits Over-ScaleThresholds VLIM = 4V,register-selectableratioofVLIM OS0 HL[2:0](CFG1 registerD[5:3])= 000 0.97 0.9805 0.99 V/V OS1 HL[2:0](CFG1 registerD[5:3])= 001 0.9588 0.9688 0.9788 V/V OS2 HL[2:0](CFG1 registerD[5:3])= 010 0.9509 0.9609 0.9709 V/V OS3 HL[2:0](CFG1 registerD[5:3])= 011 0.9392 0.9492 0.9492 V/V OS4 HL[2:0](CFG1 registerD[5:3])= 100 0.8416 0.8516 0.8616 V/V OS5 HL[2:0](CFG1 registerD[5:3])= 101 0.7673 0.7773 0.7873 V/V OS6 HL[2:0](CFG1 registerD[5:3])= 110 0.6189 0.6289 0.6389 V/V OS7 HL[2:0](CFG1 registerD[5:3])= 111 0.5603 0.5703 0.5803 V/V Over-ScaleThresholdTempco ±3 ppm/ °C Over-ScaleAmplifierOffset ±9 mV Over-ScaleAmplifierOffsetDrift ±10 mV/°C Under-ScaleThresholds VLIM = 5V,register-selectableratioofVLIM US7 LL[2:0](CFG1 registerD[2:0])= 111 0.0487 0.0547 0.0607 V/V US6 LL[2:0](CFG1 registerD[2:0])= 110 0.04478 0.05078 0.05678 V/V US5 LL[2:0](CFG1 registerD[2:0])= 101 0.04088 0.04688 0.05288 V/V US4 LL[2:0](CFG1 registerD[2:0])= 100 0.03306 0.03906 0.04506 V/V US3 LL[2:0](CFG1 registerD[2:0])= 011 0.02916 0.03516 0.04116 V/V US2 LL[2:0](CFG1 registerD[2:0])= 010 0.02525 0.03125 0.03725 V/V US1 LL[2:0](CFG1 registerD[2:0])= 001 0.01743 0.02343 0.02943 V/V US0 LL[2:0](CFG1 registerD[2:0])= 000 0.01353 0.01953 0.02553 V/V Under-ScaleThresholdTempco ±3 ppm/ °C Under-ScaleAmplifierOffset ±9 mV Under-ScaleAmplifierOffsetDrift ±10 mV/°C Output VoltageClamp InputVoltageRange VCLAMP ≤ VS,VS = +5V 1.25 4.95 V InputBiasCurrent ±60 nA VOUT Clamp Point VCLAMP – 0.05 VCLAMP VCLAMP + 0.05 V FaultMonitorCircuit (ExternalComparators) INP_HI ComparatorThreshold FaultDetectMode Select= 0 (bridgefault);see CFG1 Smallerof(VS – 1.2)or(0.65VFLT) V INN_HI ComparatorThreshold register INP_LO ComparatorThreshold FaultDetectMode Select= 0 (bridgefault);see CFG1 Largerof(0.1V)or(0.35VFLT) V INN_LO ComparatorThreshold register FaultMonitorReference VFLT FaultMonitorReference;see CFG1 register,FLT REF bit VS orVREF V setsVFLT INP_HI ComparatorThreshold FaultDetectMode Select= 1 (common-mode fault);see VS – 1.2 V INN_HI ComparatorThreshold CFG1 register INP_LO ComparatorThreshold FaultDetectMode Select= 1 (common-mode fault);see 70 100 130 mV INN_LO ComparatorThreshold CFG1 register ComparatorHysteresis 7 mV ComparatorInputOffsetVoltage ±10 mV FaultMonitorCircuit (InternalComparators) A1SAT_LO ComparatorThreshold Thresholdisamplifiernegativesaturationvoltage 100 mV A2SAT_LO ComparatorThreshold A1SAT_HI ComparatorThreshold Thresholdisamplifierpositivesaturationvoltage VS – 0.12 V A2SAT_HI ComparatorThreshold A3SAT_LO ComparatorThreshold Thresholdisamplifiernegativesaturationvoltage 50 mV VIN1,VIN2 Pull-upCurrentSources Pull-UpCurrentSource IPU Register-selectable 15 30 45 nA CurrentSourceMatching ±1.5 ±7 nA CurrentSource Tempco ±5 pA/°C Copyright© 2008–2010,Texas InstrumentsIncorporated SubmitDocumentationFeedback 5 ProductFolderLink(s):PGA308

SBOS440B –JULY 2008–REVISED DECEMBER 2010 www.ti.com ELECTRICAL CHARACTERISTICS (continued) Boldfacelimitsapplyoverthespecifiedtemperaturerange,TA = –40°C to+125°C. AtTA = +25°C, VS = +5V, GND = 0V,D OUT /VCLAMP = +5V, and VREF = +5V, unlessotherwisenoted. PGA308 PARAMETER CONDITIONS MIN TYP MAX UNIT VREF InputRange 1.8 VS V InputResistance 43 kΩ DigitalInterface One-Wire Serialspeed baud rate 4.8k 114k bits/s Logic Levels LogicLevels(1W pin) Low 0.8 V High 2.0 V Hysteresis 100 mV OutputLow Level(1W pin) Open drain,ISINK = 4mA 0.4 V OutputLevels(DOUT /VCLAMP ) Low, D OUT mode selected,ISINK = 4mA and VS = +4.5V,or 0.4 V ISINK = 2mA and VS = +2.7V High,D OUT mode selected,ISOURCE = 4mA and VS = +4.5V, VS – 0.4 V or ISOURCE = 2mA and VS = +2.7V POWER SUPPLY SupplyVoltage VS 2.7 5.5 V OTP Program Voltage VS-PGM 4.5 5.5 V QuiescentCurrent IQ VS = +5V, does notincludeIREF 1.3 1.6 mA Shutdown SupplyCurrent ISHDN VS = +5V, does notincludeIREF (8) 260 mA POWER-ON RESET (POR) Power-Up Threshold VS rising 2.1 V Power-Down Threshold VS falling 1.7 V TEMPERATURE RANGE SpecifiedPerformanceRange –40 +125 °C Operational-DegradedPerformanceRange –40 +150 °C ThermalResistance MSOP-10, Junction-to-Ambient qJA 150 °C/W (8) IREF currentloadistypically100mA whileinShutdown mode. AlthoughtheoutputamplifierisdisabledinShutdown mode, RFO and RGO (180kΩ typicaltotal)remainconnectedinseriesbetween VFB and GND whileinShutdown mode. See Figure37,DetailedBlock Diagram,formore information.

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Power□Supply Easy-T o-Use Calibration USB VOUT VIN2 VCC One-Wire GND +5V /c43 /c45 Sensor Out Ground CF 47pF CF 10nF RPU VIN1 VFB VSJ +5V D /OUT VCLAMP VS GND Bridge Sensor VREF PC ADC VCC PGA308 www.ti.com SBOS440B –JULY 2008–REVISED DECEMBER 2010 TYPICAL THREE-WIRE APPLICATION CIRCUIT Copyright© 2008–2010,Texas InstrumentsIncorporated SubmitDocumentationFeedback 7 ProductFolderLink(s):PGA308

SBOS440B –JULY 2008–REVISED DECEMBER 2010 www.ti.com PIN CONFIGURATIONS DGS PACKAGE DRK PACKAGEMSOP-10 3x4 DFN-10(TOP VIEW) (TOP VIEW) PIN DESCRIPTIONS PIN # NAME DESCRIPTION Dual-usepin:Outputvoltageclamp limitforVOUT orprogrammabledigitaloutput.The outputvoltage clamp functionisforuse inmultiplesupplysystemswhere thePGA308 may be atVS = +5V and the systemanalog-to-digitalconverter(ADC) ispowered at+3V. SettingVCLAMP to+3.2V prevents 1 D OUT /VCLAMP over-voltageand latch-upon thesystemADC input.VCLAMP may be setthrougha resistordividerfrom VS.Ifconfiguredfordigitaloutput,theD OUT functionallowsforconfigurationpluscalibrationofa sensor module eitherthroughtheOne-Wireinterface(1W pin)oras a permanentlyconfiguredmodule through thepower-onreset(POR) OTP memory setting. One-Wireinterfaceprogrampin.UART interfacefordigitalcalibrationofthePGA308 overa single2 1W wire.Can be connectedtoVOUT fora threeterminal(VS,GND, VOUT )programmablesensorassembly. 3 GND Ground. 4 VS +Voltagesupply. Signalinputvoltage1.Connectto+ or– outputofthesensorbridge.Internalmultiplexercan change5 VIN1 connectioninternallytofront-endPGA. Signalinputvoltage2.Connectto+ or– outputofthesensorbridge.Internalmultiplexercan change6 VIN2 connectioninternallytofront-endPGA. Outputamplifiersumming junction.Use foroutputamplifiercompensationwhen drivinglargecapacitive7 VSJ loads(> 200pF)and/orforusingexternalgainsettingresistorsfortheoutputamplifier. VOUT feedbackpin.Voltagefeedbacksense pointforover-/under-scalelimitcircuitry.Ifinternalgainset resistorsfortheoutputamplifierareused,thispinisalsothevoltagefeedbacksense pointforthe 8 VFB outputamplifier.VFB incombinationwithVSJ allowsforuse ofexternalfilterand protectioncircuits withoutdegradingthePGA308 VOUT accuracy.VFB must alwaysbe connectedtoeitherVOUT orthe pointoffeedbackforVOUT ifexternalfilteringisused. 9 VOUT Analogoutputvoltageofconditionedsensor. Referencevoltageinputpin.VREF isused forcoarseoffsetadjustand ZeroDAC. VREF orVS may be10 VREF individuallyselectedforover-/under-scalethresholdreferenceand faultmonitorcomparatorreference.

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T emperature□( C)/c176 /c45 50 15010075 1250/c45 25 50 25 Input□Bias□Current,□Pull-Up□Enabled□(nA) T emperature□( C)/c176 /c45 50 15010075 1250/c45 25 50 25 900 800 700 600 500 400 300 200 100 Input□Bias□Current□(pA) T emperature□( C)/c176 /c45 50 15010075 125/c45 25 50 250 0.6 0.5 0.4 0.3 0.2 0.1 Error□from□Ideal□Value□(%) +11mV□Offset□Adjust /c45 10mV□Offset□Adjust +51mV□to□+99mV□Offset□Adjust /c45 /c45 100mV□Offset□Adjust50mV□to T emperature□(/c176 C) /c45 50 15010075 1250 3/c115 3/c115 /c45 25 50 25 /c45 10 /c45 20 /c45 30 /c45 40 Output□Voltage□( V) /c109 Three□T ypical□Units□Shown Unit□1 Unit□2 Unit□3 V OUT (500 /c109V/div) Time□(2s/div) Coarse□Offset□=□0V Coarse□Offset□=□2.5mV Frequency□(Hz) 100 1k 10k 100k 0.1 0.01 RTF□Front-End□Noise□( V/ ) /c109 /c214 Hz Offset□=□100mV,□G□=□4x1x1 Offset□=□40mV,□G□=□100x1x1 Offset□=□100mV,□G□=□32x1x1 Offset□=□0V,□G□=□1600x1x1 Clock Feed- through PGA308 www.ti.com SBOS440B –JULY 2008–REVISED DECEMBER 2010 TYPICAL CHARACTERISTICS AtTA = +25°C, VS = VREF = D OUT /VCLAMP = +5V, R L = 10kΩ and C L = 100pF connectedtoGND, unlessotherwisenoted. Gain formatispresented:G = FE-PGA × FineGain × OutputGain. FRONT-END PGA INPUT BIAS CURRENT FRONT-END PGA INPUT BIAS CURRENT WITH IPU ENABLED vs TEMPERATURE WITH IPU DISABLED vs TEMPERATURE Figure1. Figure2. COARSE OFFSET ADJUST ERROR vs FRONT-END PGA OFFSET VOLTAGE vs TEMPERATURE TEMPERATURE Figure3. Figure4. 0.1HzTO 10Hz OUTPUT NOISE INPUT-REFERRED FRONT-END NOISE vs (G = 1600) FREQUENCY Figure5. Figure6. Copyright© 2008–2010,Texas InstrumentsIncorporated SubmitDocumentationFeedback 9 ProductFolderLink(s):PGA308

T emperature□( C)/c176 /c45 50 15010075 1250/c45 25 50 25 /c45 1 /c45 2 /c45 3 /c45 4 /c45 5 /c45 6 /c45 7 /c45 8 /c45 9 /c45 10 Over-Scale□T otal□Error□(mV) Eight□Programming□Levels□Shown OS6 OS7 OS5 OS2 OS0 OS1 OS3,□OS4 T emperature□( C)/c176 /c45 50 15010075 1250/c45 25 50 25 Under-Scale□T otal□Error□(mV) Eight□□Programming□Levels□Shown US0 US6US5 US7 US1 US2 US3 US4 T emperature□(/c176 C) /c45 50 15010075 125/c45 25 50 0 25 0.2 /c45 0.2 /c45 0.4 /c45 0.6 /c45 0.8 /c45 1.0 /c45 1.2 /c45 1.4 /c45 1.6 /c45 1.8 /c45 2.0 Offset□Error□from□Ideal□Value□(mV) 156mV 2.344V 4.844V Frequency□(Hz) 10 10k1k100 120 110 100 CMR□(dB) G□=□4x1x2 G□=□32x1x2 G□=□100x1x2 G□=□600x1x2 Frequency□(Hz) 10 10k1k100 120 110 100 PSRR□(dB) G□=□100x1x2 G□=□600x1x2 G□=□32x1x2 G□=□4x1x2 Frequency□(Hz) 1k 10M100k 1M10k 10000 1000 100 0.1 Gain G□=□800x1x2 G□=□400x1x2 G□=□32x1x3 G□=□4x1x2 G□=□1600x1x6 PGA308 SBOS440B –JULY 2008–REVISED DECEMBER 2010 www.ti.com TYPICAL CHARACTERISTICS (continued) AtTA = +25°C, VS = VREF = D OUT /VCLAMP = +5V, R L = 10kΩ and C L = 100pF connectedtoGND, unlessotherwisenoted. Gain formatispresented:G = FE-PGA × FineGain × OutputGain. OVER-SCALE TOTAL ERROR vs TEMPERATURE UNDER-SCALE TOTAL ERROR vs TEMPERATURE (5V Ref) (4V Ref) Figure7. Figure8. ZERO DAC OFFSET ERROR vs COMMON-MODE REJECTION (RTI)vs TEMPERATURE FREQUENCY Figure9. Figure10. POWER-SUPPLY REJECTION RATIO (RTI)vs GAIN vs FREQUENCY FREQUENCY Figure11. Figure12.

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T emperature□(/c176 C) /c45 50 15010075 1250/c45 25 50 25 4.99 4.98 4.97 4.96 4.95 4.94 4.93 4.92 4.91 4.90 4.89 V with□V High□(V) OUT CLAMP T emperature□( C)/c176 /c45 50 15010075 1250/c45 25 50 25 1.30 1.29 1.28 1.27 1.26 1.25 1.24 1.23 1.22 1.21 1.20 V with□V Low□(V) OUT CLAMP V (1V/div) OUT V CM□(2V/div) IN Time□(25 s/div)/c109 R =□10k CMP□SEL□=□0,/c87/c44L C =□0,□C =□0,L F Gain□=□4x1x2 V CM□=□5VIN V CM□=□3VIN 50mV/div Time□(250 s/div)/c109 2.5V□V ,□RCLAMP L =□10k ,/c87 G□=□32x1x2,□300Hz□Triangle□Wave 50mV/div Time□(250 s/div)/c109 2.5V□V ,□RCLAMP L =□10k ,/c87 G□=□32x1x2,□300Hz□Triangle□Wave 50mV/div Time□(250 s/div)/c109 2.5V□V ,□RCLAMP L =□10k/c87, G□=□32x1x2,□300Hz□Triangle□Wave PGA308 www.ti.com SBOS440B –JULY 2008–REVISED DECEMBER 2010 TYPICAL CHARACTERISTICS (continued) AtTA = +25°C, VS = VREF = D OUT /VCLAMP = +5V, R L = 10kΩ and C L = 100pF connectedtoGND, unlessotherwisenoted. Gain formatispresented:G = FE-PGA × FineGain × OutputGain. VOUT WITH VCLAMP HIGH (4.94V)vs VOUT WITH VCLAMP LOW (1.25V)vs TEMPERATURE TEMPERATURE Figure13. Figure14. VCLAMP RESPONSE COMMON-MODE OVER-VOLTAGE RECOVERY (No Cap Load, CMP SEL = 1) Figure15. Figure16. VCLAMP RESPONSE VCLAMP RESPONSE (No Cap Load, CMP SEL = 0) (CL = 10nF,CMP SEL = 1) Figure17. Figure18. Copyright© 2008–2010,Texas InstrumentsIncorporated SubmitDocumentationFeedback 11 ProductFolderLink(s):PGA308

Time□(250 s/div)/c109 2.5V□V ,□RCLAMP L =□10k ,/c87 G□=□32x1x2,□300Hz□Triangle□Wave VS V 0.1/c45S V 0.2/c45S V 0.3/c45S V 0.4/c45S GND□+□0.4 GND□+□0.3 GND□+□0.2 GND□+□0.1 GND 0 3 6 9 12 15 Output□Voltage□(V) V =□2.7VS V =□5.5VSV =□3VS V =□5VS T emperature□( C)/c176 /c45 50 15010075 1250/c45 25 50 25 1.6 1.4 1.2 1.0 0.8 0.6 0.4 0.2 I (mA)Q Frequency□(Hz) 0.01 10M1M100k10k1k1001010.1 120 100 /c45 20 Output□Amplifier□Open-Loop□Gain□(dB) C =□10nFL RL L=□10k/c87 ,□C =□10nF RL L=□1k/c87 ,□C =□10nF CL /c163 100pF Frequency□(Hz) 0.01 10M1M100k10k1k1001010.1 120 100 /c45 20 Output□Amplifier□Open-Loop□Gain□(dB) C =□10nFL R =□10k ,□C/c87L L =□10nF R =□1k ,□C/c87L L =□10nF C 100pFL /c163 Frequency□(Hz) 0.01 10M1M100k10k1k1001010.1 180 160 140 120 100 /c45 20 Output□Amplifier□Open-Loop□Phase□( ) /c176 C =□10nFL R =□10k ,□C/c87L L =□10nF R =□1k ,□C/c87L L =□10nF C 100pF/c163L PGA308 SBOS440B –JULY 2008–REVISED DECEMBER 2010 www.ti.com TYPICAL CHARACTERISTICS (continued) AtTA = +25°C, VS = VREF = D OUT /VCLAMP = +5V, R L = 10kΩ and C L = 100pF connectedtoGND, unlessotherwisenoted. Gain formatispresented:G = FE-PGA × FineGain × OutputGain. VCLAMP RESPONSE OUTPUT VOLTAGE vs (CL = 10nF,CMP SEL = 0) OUTPUT CURRENT Figure19. Figure20. QUIESCENT CURRENT vs OUTPUT AMPLIFIER OPEN-LOOP GAIN vs TEMPERATURE FREQUENCY (CMP SEL = 1) Figure21. Figure22. OUTPUT AMPLIFIER OPEN-LOOP GAIN vs OUTPUT AMPLIFIER OPEN-LOOP PHASE vs FREQUENCY (CMP SEL = 0) FREQUENCY (CMP SEL = 1) Figure23. Figure24.

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Time□(5 s/div)/c109 G□=□4x1x2 V =□100mVOPP RL =□10k/c87 Frequency□(Hz) 0.01 10M1M100k10k1k1001010.1 180 160 140 120 100 /c45 20 Output□Amplifier□Open-Loop□Phase□( ) /c176 C =□10nFL RL L=□10k/c87 ,□C =□10nF RL L=□1k/c87 ,□C =□10nF CL /c163 100pF 20mV/div Time□(5 s/div)/c109 G□=□4x1x2 V =□100mVOPP RL =□10k/c87 Frequency□(Hz) 10 100 1k 10k 100k 1M 10M 10k 100 Open-Loop□Output□Impedance□( ) /c87 I =□0L IL =□500/c109A I =□5mAL CMP□SEL□=□1 CMP□SEL□=□0 V (50mV/div) OUT Time□(50 s/div)/c109 R =□10k R =□100 ,L ISO /c87/c44 /c87 C =□10nF ,□CL F =□47pF , G□=□600x1x2,□f□=□4kHz,□V =□100mVOPP V (1V/div) OUT Time□(50 s/div)/c109 R =□10k R =□100 ,L ISO /c87/c44 /c87 C =□10nF ,□CL F =□47pF , PGA308 www.ti.com SBOS440B –JULY 2008–REVISED DECEMBER 2010 TYPICAL CHARACTERISTICS (continued) AtTA = +25°C, VS = VREF = D OUT /VCLAMP = +5V, R L = 10kΩ and C L = 100pF connectedtoGND, unlessotherwisenoted. Gain formatispresented:G = FE-PGA × FineGain × OutputGain. OUTPUT AMPLIFIER OPEN-LOOP PHASE vs CAPACITIVE LOAD DRIVE FREQUENCY (CMP SEL = 0) C L = 1nF Figure25. Figure26. CAPACITIVE LOAD DRIVE OPEN-LOOP OUTPUT IMPEDANCE vs C L = 10pF FREQUENCY Figure27. Figure28. SMALL-SIGNAL STEP RESPONSE LARGE-SIGNAL STEP RESPONSE CMP SEL = 1 CMP SEL = 1 Figure29. Figure30. Copyright© 2008–2010,Texas InstrumentsIncorporated SubmitDocumentationFeedback 13 ProductFolderLink(s):PGA308

V (50mV/div) OUT Time□(50 s/div)/c109 R =□10k R =□100 ,L ISO /c87/c44 /c87 C =□10nF ,□CL F =□47pF , V (1V/div) OUT Time□(50 s/div)/c109 R =□10k R =□100 ,L ISO /c87/c44 /c87 C =□10nF ,□CL F =□47pF , V OUT (50mV/div) Time□(50/c109 s/div) R =□10kL L /c87/c44 C =□0,□C =□0,F G□=□600x1x2,□f□=□4kHz,□VOPP =□100mV V (1V/div) OUT Time□(50 s/div)/c109 R =□10kL /c87/c44 C =□0,□CL F =□0, V (50mV/div) OUT Time□(50 s/div)/c109 R =□10kL /c87/c44 C =□0,□C =□0,L F V (1V/div) OUT Time□(50 s/div)/c109 R =□10kL /c87/c44 C =□0,□C =□0,L F PGA308 SBOS440B –JULY 2008–REVISED DECEMBER 2010 www.ti.com TYPICAL CHARACTERISTICS (continued) AtTA = +25°C, VS = VREF = D OUT /VCLAMP = +5V, R L = 10kΩ and C L = 100pF connectedtoGND, unlessotherwisenoted. Gain formatispresented:G = FE-PGA × FineGain × OutputGain. SMALL-SIGNAL STEP RESPONSE LARGE-SIGNAL STEP RESPONSE CMP SEL = 1 CMP SEL = 1 Figure31. Figure32. SMALL-SIGNAL STEP RESPONSE LARGE-SIGNAL STEP RESPONSE CMP SEL = 0 CMP SEL = 0 Figure33. Figure34. SMALL-SIGNAL STEP RESPONSE LARGE-SIGNAL STEP RESPONSE CMP SEL = 0 CMP SEL = 0 Figure35. Figure36.

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www.ti.com SBOS440B –JULY 2008–REVISED DECEMBER 2010 FUNCTIONAL DESCRIPTION OVERVIEW VOLTAGE REFERENCE The PGA308 isan idealbuildingblockforresistive The PGA308 VREF pin provides input from a bridge sensor conditioningand general data referencevoltage.The referencevoltageisused by acquisition.Digitally-programmablecoarseoffset,fine the Coarse OffsetAdjustand Zero DACs. The fault offset,and gain may be controlledin realtime or monitorcircuitrytrippoints,as wellas theover-and permanentlyprogrammed intothePGA308. under-scalelimits,can be selectedto be referenced to eitherVS or VREF . This flexibilityaccommodates absoluteorratiometricmode designs.SENSOR ERROR ADJUSTMENT RANGE The PGA308 isdesignedtoreadilyaccommodate the FAULT MONITOR CIRCUIT SENSOR FAULTfollowingsensors: DETECTION Span25°C :0.08mV/V to296mV/V To detectsensorburnoutand/orshort,a setof fourInitialOffset:20mV/V comparators (external fault comparators) are Span and offsetare based on a bridge sensor connectedtotheinputsofthefront-endPGA. There excitationvoltageof +5V, a PGA308 outputvoltage are two fault-detectmodes of operationforthese span of 4V (+0.5V to +4.5V),VREF of +5V, and a comparators. VOUT /VIN gainup to9600.For properPGA308 setup, consider noise, small-signalbandwidth, VOUT /VIN Common-Mode Fault gain,and requiredsystemerror. If eitherof the inputsare taken outsideof the common-mode range of the amplifier[greaterthanAMPLIFICATION SIGNAL PATH (VS – 1.2V), or less than 100mV], then the correspondingcomparatorsets a sensor faultflagThe coreofthePGA308 isa precision,low drift,and thatcan be programmed todrivethePGA308 VOUT tolow noise front-endprogrammable gain amplifier within100mV (IOUT < 4mA) ofeitherVS (orVCLAMP if(PGA).Thisfront-endPGA has gaincapabilitiesfrom VCLAMP isused) or ground.Thisleveliswellabovex4 to x1600.The outputamplifierhas a gainrange the set over-scalelimitlevelor wellbelow the setfrom×2 to×6.A finegainadjustinfrontoftheoutput under-scalelimitlevel.The stateofthefaultconditionamplifieroffersa selectable×0.33to×1.0attenuation can be readindigitalformintheALRM register.Ifthefactor.Thisarchitectureyieldsa VOUT /VIN gainrange over-scale/under-scalelimitingis disabled, theforthePGA309 of×2.67to×9600.Many applications PGA308 outputvoltageisalsodrivenwithin100mVuse overallgainsof ×1600 or less.The selectionof (IOUT < 4mA) ofeitherVS (orVCLAMP ifVCLAMP isused)gains in the front-endPGA and outputamplifier, or ground,depending on the selectedfaultpolarityalthoughcapable of up to ×9600 overallgain,are (highorlow).intendedto allowforgaindistributionthroughoutthe PGA308; thisdesign enables optimum span and BridgeFaultoffsetscalingfrominputtooutput.The polarityofthe inputscan be switchedthroughthe inputmux to To assistin identifyingmis-wiring,or open- oraccommodate sensorswithunknown polarityoutput. short-circuitconditions,the PGA308 providesbridgeHigher gains reduce bandwidth and requiremore faultmonitoring.For bridgefaultdetection,eitherVSanalog filteringand/or system analog-to-digitalor VREF (whicheverisused forbridgeexcitation)canconverter(ADC) averagingtorejectnoise. be chosen as VFLT.Ifeitheroftheinputsaretakento lessthanthelargerofeither100mV or0.35VFLT,thenCOARSE AND FINE OFFSET ADJUSTMENT a faultissignaled.Also,ifeitheroftheinputsistaken togreaterthanthesmallerof(VS – 1.2V)or0.65VFLT,The sensoroffsetadjustmentisdone intwo stages. thena faultissignaled.ThisfaultdetectionallowsforThe input-referredCoarse OffsetAdjustDAC has a operationwith bridgedifferentialvoltagesof up to±100mV offsetadjustmentrange fora selectedVREF 30% of the bridge excitationvoltage. Theof+5V. Any residualinputsensoroffsetiscorrected correspondingcomparatorsets a sensor faultflagand any desiredVOUT offsetpedestalforzero-applied thatcan be programmed todrivethePGA308 VOUT tosensor straininputis set by a Fine OffsetAdjust within100mV (IOUT < 4mA) ofeitherVS (orVCLAMP ifthroughthe 16-bitZero DAC thatadds to the signal VCLAMP isused) or ground.Thisleveliswellabovefromtheoutputofthefront-endPGA. the set over-scalelimitlevelor wellbelow the set Copyright© 2008–2010,Texas InstrumentsIncorporated SubmitDocumentationFeedback 15 ProductFolderLink(s):PGA308

SBOS440B –JULY 2008–REVISED DECEMBER 2010 www.ti.com under-scalelimitlevel.If over-scale/under-scale DIGITAL INTERFACE: ONE-WIRE PROGRAM limitingis disabled,the PGA308 outputvoltageis PROTOCOL drivenwithin100mV (IOUT < 4mA) of eitherVS or The PGA308 can be configuredthrougha single-wire,ground,dependingon theselectedfaultpolarity(high UART-compatibleinterface(1W pin).Itispossibletoorlow). connect thissingle-wirecommunicationpin to the VOUT pinintruethree-terminalmodules (VS,ground,AdditionalFaultDetection and sensorout)and continuetoallowforcalibration There are fiveadditionalfaultdetectcomparators and configurationprogramming. (internalfaultcomparators)thathelp detectsubtle All communication transactionsstart with anPGA308 front-endviolationsthatcouldresultinlinear initializationbyte transmittedby the controller.Thisvoltagesat VOUT and be interpretedas validstates. byte (55h) sets the baud rate used for theThese comparators are especiallyuseful during communicationtransaction.The baud rateissensedfactorycalibrationand setup. duringtheinitializationbyteofeverytransaction,and is used throughoutthe entiretransaction.EachAlarm Register transactionmay use a differentbaud rate,ifdesired. Each ofninefaultconditionssetsa correspondingbit Baud ratesof4.8kto114k bits/secondaresupported. intheAlarm register.The stateofthefaultcondition Each communication consistsof severalbytes ofcan be readdigitallyfromtheAlarmregister. data.Each byteconsistsof10-bitperiods.The firstbit isthe startbitand isalways '0'.When idle,the 1WOVER-SCALE AND UNDER-SCALE LIMITS pinshouldalwaysbe high.The second throughninth bitsare the eightdata bitsforthe byte and areThe over-scale and under-scale limitcircuitry transferredLSB first.The 10thbitisthestopbitandprovidesa programmable upper and lowercliplimit isalways'1'.forthePGA308 outputvoltage.When combined with oftheregister.D OUT /VCLAMP PIN output thispin can be used for sensor module configuration.The valuemay be pre-programmedin the one-time programmable (OTP) banks, or controlledthroughtheOne-Wireinterface(1W pin).

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www.ti.com SBOS440B –JULY 2008–REVISED DECEMBER 2010 Timeout on theOne-Wire Interface ONE-WIRE OPERATION WITH 1W CONNECTED TO VOUTThe PGA308 includesa timeout mechanism. If synchronizationbetween the controllerand the In some sensorapplications,itisdesiredto provide PGA308 is lost for any reason, the timeout the end user of the sensor module withthreepins: mechanism allowsthe One-Wire interfaceto reset VS,GND, and Sensor Out.Itisalsodesiredinthese communication. The timeout period is set to applicationsto digitallycalibratethe sensor module approximately28ms (typical).Ifthe timeoutperiod afteritsfinalassemblyofsensorand electronics.The expires between the initializationbyte and the PGA308 has a mode that allows the One-Wire command byte,between thecommand byteand any interfacepin(1W) to be tieddirectlyto the PGA308 data byte,or between any data bytes,the PGA308 outputpin(VOUT ). resetsthe One-Wire interfacecircuitryso that it To calibratethePGA308 inThree-Wireconfiguration,expectsan initializationbyte.Everytimethata byteis program the internalregistersand measure thetransmittedon the singlewireinterface,thistimeout resultingVOUT .To do thiswhileVOUT isconnectedtoperiodrestarts. 1W requiresthe abilityto enable and disableVOUT . Thus, the 1W/V OUT lineoperatesin a multiplexedPOWER-ON SEQUENCE mode where 1W is used as a bidirectionaldigital The PGA308 providescircuitryto detectwhen the interfacewhileVOUT isdisabled,and VOUT drivesthe power supplyisappliedto the PGA308 and resets lineas a conditionedsensoroutputvoltagewhen itis the internalregistersto a known power-on reset enabled. space dataisread.The valueread from thisregisterpoints toone oftheseven OTP banks,whichisthenloadedspace intoRAM. space space space space space space space space Copyright© 2008–2010,Texas InstrumentsIncorporated SubmitDocumentationFeedback 17 ProductFolderLink(s):PGA308

V = mux_sign V + V GI + V GD GOOUT IN Coarse_Offset Zero_DAC[ ] /c63 /c63 /c63 /c63( ( PGA308 SBOS440B –JULY 2008–REVISED DECEMBER 2010 www.ti.com OTP MEMORY BANKS PGA308 TRANSFER FUNCTION There are fourone-timeprogrammable (OTP) bank Equation1 shows themathematicalexpressionthatis selectionregisters:BANK SEL1, BANK SEL2, BANK used to compute the output voltage,VOUT . This SEL3, and BANK SEL4. Bank selectionmay be set equationcan also be rearrangedalgebraicallyto fourtimesby programming theBANK SELx registers solve for differentterms. For example, during inorder(1,2, 3, 4).The defaultOTP bank used on calibration,thisequationis rearrangedto solvefor POR isthe locationstoredin the lastprogrammed VIN. BANK SELx register.Therefore,if programmed, BANK SEL4 alwayshas priorityoverlower-numbered (1)bank selectregisters. Where:The PGA308 containsseven OTP user memory mux_sign: Thisterm changes thepolarityofthebanks. All seven of these banks may be inputsignal;valueis±1independentlyprogrammed. However, the default bank atPOR can be setonlyfourtimes.The seven VIN:The inputsignalforthePGA308; VIN1 = VINP, possibleOTP user memory banks allow an end VIN2 = VINN productwitha microcontrollerinterfacebetween the VCoarse_Offset: The coarse offsetDAC outputend-userand thePGA308 toselectfromup toseven voltagefactory pre-programmed configurations.It also GI:Inputstagegainprovides total user flexibilityfor any other VZero_DAC :ZeroDAC outputvoltageconfigurationthroughsoftwarecommunicationover theOne-Wire interface(1W pin).Thisflexibilityallows GD: Gain DAC no-scraprecoveryfrommiscalibrationsituations. GO: Outputstagegain

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Control□Registers RAM Alarm□Register RF RF RG R R VREF Auto Zero Auto Zero Auto Zero Output Amplifier Input□Mux VINN VINP Front-End PGA□Gain PGA Diff□Amp NOTES: (1)□User-adjustable□feature. (2)□Optional□connection;□see□the section□for□more□information.One-Wire□Operation□with□1W□Connected□to□VOUT (3)□Optional□connection;□see□the□PGA308□User's□Guide□for□more□information. RGO VOUT□FILT CF CL VREF VREF VS VREF 16-Bit□DAC 0□<□V <□VZDAC REFInput□Mux□Control(1) 7-Bit□+□Sign DAC Coarse□Offset□Range(1) Coarse□Offset□Adjust(1) Fault□Monitor Circuit Ref Select Bridge Sensor Zero□DAC Gain□DACVIN1 VOS VREF VS VIN2 Fine□Offset□Adjust(1) (16-Bit) PGA□Gain□Select□(1□of□16)(1) Range□of□4□to□1600 (w/PGA□Diff□Amp□Gain□=□4) Front-End□PGA□Out Gain□=□x4□to□x1600 Offset□Due□to□Zero□DAC /c450.5V <□Offset□<□+0.5VREF REF Alarm□Register□Inputs Output□Gain□Select□(1-of-7)(1) Range□of□2□to□5 INT/EXT□FB□Select(1) Fault□Ref Select(1) Fault□Detect□Mode(1) Fine□Gain□Adjust□(16-Bit)(1) OS/US□Ref□Select(1) D OUT CLAMP (1) Digital Controls RFO RISOVOUT RCL1 RCL2 D /VOUT CLAMP VCLAMP Mode Only VFB VSJ Scale Limit Interface and Control Circuitry OTP (7□Banks) Clamp VLIM 3-Bit□DAC Under-Scale□Limit(1) VLIM VS 3-Bit□DAC Over-Scale□Limit(1) (2) (3) POR VS VS Ref Select Digital□OutVS VREF VLIM VREF GND PGA308 PGA308 www.ti.com SBOS440B –JULY 2008–REVISED DECEMBER 2010 Figure37. DetailedBlock Diagram Copyright© 2008–2010,Texas InstrumentsIncorporated SubmitDocumentationFeedback 19 ProductFolderLink(s):PGA308

SBOS440B –JULY 2008–REVISED DECEMBER 2010 www.ti.com

REVISION HISTORY

NOTE: Page numbers forpreviousrevisionsmay differfrompage numbers inthecurrentversion. Changes from RevisionA (April,2009)toRevisionB Page

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www.ti.com 8-Jul-2016 Addendum-Page 1 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/Ball Finish (6) MSL Peak Temp (3) Op Temp (°C) Device Marking (4/5) Samples PGA308AIDGSR ACTIVE VSSOP DGS 10 2500 Green (RoHS & no Sb/Br) CU NIPDAUAG Level-2-260C-1 YEAR -40 to 125 P30A PGA308AIDGSRG4 ACTIVE VSSOP DGS 10 2500 Green (RoHS & no Sb/Br) CU NIPDAUAG Level-2-260C-1 YEAR -40 to 125 P30A PGA308AIDGST ACTIVE VSSOP DGS 10 250 Green (RoHS & no Sb/Br) CU NIPDAUAG Level-2-260C-1 YEAR -40 to 125 P30A PGA308AIDGSTG4 ACTIVE VSSOP DGS 10 250 Green (RoHS & no Sb/Br) CU NIPDAUAG Level-2-260C-1 YEAR -40 to 125 P30A PGA308AIDRKR ACTIVE VSON DRK 10 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 P30B PGA308AIDRKT ACTIVE VSON DRK 10 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 P30B (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device.

www.ti.com 8-Jul-2016 Addendum-Page 2 (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. OTHER QUALIFIED VERSIONS OF PGA308 :

• Automotive: PGA308-Q1 NOTE: Qualified Version Definitions:
• Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects

*All dimensions are nominal Device Package Type Package Drawing Pins SPQ Reel Diameter (mm) Reel Width W1 (mm) (mm) (mm) (mm) (mm) W (mm) Pin1 Quadrant PACKAGE MATERIALS INFORMATION www.ti.com 8-Jul-2016 Pack Materials-Page 1

*All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) PGA308AIDGSR VSSOP DGS 10 2500 366.0 364.0 50.0 PGA308AIDGST VSSOP DGS 10 250 366.0 364.0 50.0 PGA308AIDRKR VSON DRK 10 3000 367.0 367.0 35.0 PGA308AIDRKT VSON DRK 10 250 210.0 185.0 35.0 PACKAGE MATERIALS INFORMATION www.ti.com 8-Jul-2016 Pack Materials-Page 2

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