PGA2320 TI | Alldatasheet
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Technical content
FEATURES
/C0068DIGITALLY-CONTROLLED ANALOG VOLUME CONTROL: Two Independent Audio Channels Serial Control Interface Zero Crossing Detection Mute Function /C0068WIDE GAIN AND ATTENUATION RANGE: +31.5dB to −95.5dB with 0.5dB Steps /C0068LOW NOISE AND DISTORTION: 120dB Dynamic Range 0.0003% THD+N at 1kHz /C0068LOW INTERCHANNEL CROSSTALK: −126dBFS /C0068NOISE-FREE LEVEL TRANSITIONS /C0068POWER SUPPLIES: /C004315V Analog, +5V Digital /C0068AVAILABLE IN SOL−16 PACKAGE /C0068PIN-FOR-PIN COMPATIBLE WITH THE PGA2310
APPLICATIONS
/C0068AUDIO AMPLIFIERS /C0068MIXING CONSOLES /C0068MULTI-TRACK RECORDERS /C0068BROADCAST STUDIO EQUIPMENT /C0068MUSICAL INSTRUMENTS /C0068EFFECTS PROCESSORS /C0068A/V RECEIVERS /C0068CAR AUDIO SYSTEMS
DESCRIPTION
The PGA2320 is a high-performance, stereo audio volume control designed for professional and high-end consumer audio systems. The ability to operate from ±15V analog power supplies enables the PGA2320 to process input signals with large voltage swings, thereby preserving the dynamic range available in the overall signal path. Using high performance operational amplifier stages internal to the PGA2320 yields low noise and distortion, while providing the capability to drive 600Ω loads directly without buffering. The three-wire serial control interface allows for connection to a wide variety of host controllers, in addition to support for daisy-chaining of multiple PGA2320 devices. PGA2320 SBOS312B − JULY 2004 − REVISED DECEMBER 2004 Stereo Audio Volume Control www.ti.com Copyright 2004, Texas Instruments Incorporated Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. All trademarks are the property of their respective owners. /C0080/C0082/C0079/C0068/C0085/C0067/C0084/C0073/C0079/C0078 /C0068/C0065/C0084/C0065 /C0105/C0110/C0102/C0111/C0114/C0109/C0097/C0116/C0105/C0111/C0110 /C0105/C0115 /C0099/C0117/C0114/C0114/C0101/C0110/C0116 /C0097/C0115 /C0111/C0102 /C0112/C0117/C0098/C0108/C0105/C0099/C0097/C0116/C0105/C0111/C0110 /C0100/C0097/C0116/C0101/C0046 /C0080/C0114/C0111/C0100/C0117/C0099/C0116/C0115 /C0099/C0111/C0110/C0102/C0111/C0114/C0109 /C0116/C0111 /C0115/C0112/C0101/C0099/C0105/C0102/C0105/C0099/C0097/C0116/C0105/C0111/C0110/C0115 /C0112/C0101/C0114 /C0116/C0104/C0101 /C0116/C0101/C0114/C0109/C0115 /C0111/C0102 /C0084/C0101/C0120/C0097/C0115 /C0073/C0110/C0115/C0116/C0114/C0117/C0109/C0101/C0110/C0116/C0115 /C0115/C0116/C0097/C0110/C0100/C0097/C0114/C0100 /C0119/C0097/C0114/C0114/C0097/C0110/C0116/C0121/C0046 /C0080/C0114/C0111/C0100/C0117/C0099/C0116/C0105/C0111/C0110 /C0112/C0114/C0111/C0099/C0101/C0115/C0115/C0105/C0110/C0103 /C0100/C0111/C0101/C0115 /C0110/C0111/C0116 /C0110/C0101/C0099/C0101/C0115/C0115/C0097/C0114/C0105/C0108/C0121 /C0105/C0110/C0099/C0108/C0117/C0100/C0101 /C0116/C0101/C0115/C0116/C0105/C0110/C0103 /C0111/C0102 /C0097/C0108/C0108 /C0112/C0097/C0114/C0097/C0109/C0101/C0116/C0101/C0114/C0115/C0046
/C0080/C0071/C0065/C0050/C0051/C0050/C0048 SBOS312B − JULY 2004 − REVISED DECEMBER 2004 www.ti.com This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. ABSOLUTE MAXIMUM RATINGS over operating free-air temperature range unless otherwise noted(1) PGA2320 UNIT VA+ +15.5 V Supply voltage VA− −15.5 VSupply voltage VD + +5.5 V Analog input voltage 0 to VA+, VA− V Digital input voltage −0.3 to VD + V Operating temperature range −40 to +85 °C Storage temperature range −65 to +150 °C Junction temperature +150 °C Lead temperature (soldering, 10s) +300 °C Package temperature (IR, reflow, 10s) +235 °C (1)Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to absolute maximum conditions for extended periods may degrade device reliability. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those specified is not implied. PACKAGE/ORDERING INFORMATION For the most current package and ordering information, see the Package Option Addendum located at the end of this data sheet.
/C0080/C0071/C0065/C0050/C0051/C0050/C0048 SBOS312B − JULY 2004 − REVISED DECEMBER 2004 www.ti.com
ELECTRICAL CHARACTERISTICS
At TA = +25°C, VA+ = +15V, VA− = −15V, VD + = +5V, RL = 100kΩ, CL = 20pF, BW measure = 20Hz to 20kHz, unless otherwise noted. PGA2320 PARAMETER TEST CONDITIONS MIN TYP MAX UNIT DC CHARACTERISTICS Step Size 0.5 dB Gain Error Gain Setting = 31.5dB ±0.1 dB Gain Matching ±0.1 dB Input Resistance 12 kΩ Input Capacitance 18 pF AC CHARACTERISTICS THD+N VIN = 10VPP, f = 1kHz 0.0003 0.001 % Dynamic Range VIN = AGND, Gain = 0dB 115 120 dB Voltage Range, Input and Output (VA−) + 0.86 (VA+) − 0.86 V Output Noise VIN = AGND, Gain = 0dB 10.5 17.5 µVRMS Interchannel Crosstalk f = 1kHz −126 dBFS OUTPUT BUFFER Offset Voltage VIN = AGND, Gain = 0dB 1 7.5 mV Load Capacitance Stability 1000 pF Short-Circuit Current 75 mA Unity-Gain Bandwidth, Small Signal 1 MHz DIGITAL CHARACTERISTICS High-Level Input Voltage, VIH +2.0 VD + V Low-Level Input Voltage, VIL −0.3 0.8 V High-Level Output Voltage, VOH IO = 200µA (VD +) − 1.0 V Low-Level Output Voltage, VOL IO = −2mA 0.4 V Input Leakage Current 1 10 µA SWITCHING CHARACTERISTICS Serial Clock (SCLK) Frequency tSCLK 0 6.25 MHz Serial Clock (SCLK) Pulse Width Low tPH 80 ns Serial Clock (SCLK) Pulse Width High tPL 80 ns MUTE Pulse Width Low tMI 2.0 ms Input Timing SDI Setup Time tSDS 20 ns SDI Hold Time tSDH 20 ns CS Falling to SCLK Rising tCSCR 90 ns SCLK Falling to CS Rising tCFCS 35 ns Output Timing CS Low to SDO Active tCSO 35 ns SCLK Falling to SDO Data Valid tCFDO 60 ns POWER SUPPLY Operating Voltage Quiescent Current IA+ VA+ = +15V 11 16 mA IA− VA− = −15V 11 16 mA ID + VD + = +5V 0.6 1.5 mA
/C0080/C0071/C0065/C0050/C0051/C0050/C0048 SBOS312B − JULY 2004 − REVISED DECEMBER 2004 www.ti.com PIN CONFIGURATION Top View ZCEN CS SDI VD + DGND SCLK SDO MUTE VINL AGNDL VOUT L VA− VA+ VOUT R AGNDR VINR PGA2320 PIN ASSIGNMENTS PIN NAME FUNCTION
1 ZCEN Zero Crossing Enable Input (Active High)
2 CS Chip-Select Input (Active Low)
3 SDI Serial Data input
4 VD + Digital Power Supply, +5V
5 DGND Digital Ground
6 SCLK Serial Clock Input
7 SDO Serial Data Output
8 MUTE Mute Control Input (Active Low)
9 VINR Analog Input, Right Channel
10 AGNDR Analog Ground, Right Channel
11 VOUT R Analog Output, Right Channel
12 VA+ Analog Power Supply, +15V
13 VA− Analog Power Supply, −15V
14 VOUT L Analog Output, Left Channel
15 AGNDL Analog Ground, Left Channel
16 VINL Analog Input, Left Channel
/C0080/C0071/C0065/C0050/C0051/C0050/C0048 SBOS312B − JULY 2004 − REVISED DECEMBER 2004 www.ti.com TYPICAL CHARACTERISTICS At TA = +25°C, VA+ = +15V, VA− = −15V, VD + = +5V, RL = 100kΩ, CL = 20pF, BW measure = 20Hz to 20kHz, unless otherwise noted. FREQUENCY RESPONSE (0dB = 6.0V RMS ) GAIN = 0dB Frequency (Hz) Amplitude (dB) 1.0 0.8 0.6 0.4 0.2 −0.2 −0.4 −0.6 −0.8 −1.0 1k 10k10010 100k 200k THD+N vs INPUT AMPLITUDE (Gain = 0dB, f = 1kHz) Input Amplitude (VRMS ) THD+N (%) 0.1 0.01 0.001 0.0001 1100m 10 THD+N vs INPUT FREQUENCY (Gain = 0dB, Amplitude = 3.0VRMS ,R L =1 0 0 kΩ) Input Frequency (Hz) THD+N (%) 0.01 0.001 0.0001 1k10020 10k 20k THD+N vs INPUT FREQUENCY (Gain = 0dB, Amplitude = 3.0VRMS ,R L =6 0 0Ω) Input Frequency (Hz) THD+N (%) 0.01 0.001 0.0001 1k10020 10k 20k THD+N vs INPUT FREQUENCY (Gain = 0dB, Amplitude = 8.5VRMS ,R L =1 0 0 kΩ) Input Frequency (Hz) THD+N (%) 0.01 0.001 0.0001 1k10020 10k 20k THD+N vs INPUT FREQUENCY (Gain = 0dB, Amplitude = 8.5VRMS ,R L =6 0 0Ω) Input Frequency (Hz) THD+N (%) 0.01 0.001 0.0001 1k10020 10k 20k
/C0080/C0071/C0065/C0050/C0051/C0050/C0048 SBOS312B − JULY 2004 − REVISED DECEMBER 2004 www.ti.com TYPICAL CHARACTERISTICS (continued) At TA = +25°C, VA+ = +15V, VA− = −15V, VD + = +5V, RL = 100kΩ, CL = 20pF, BW measure = 20Hz to 20kHz, unless otherwise noted. CROSSTALK OR CHANNEL SEPARATION vs INPUT FREQUENCY (Gain = 0dB, Amplitude = 8.5VRMS ) Input Frequency (Hz) Crosstalk (dB) −10 −20 −30 −40 −50 −60 −70 −80 −90 −100 −110 −120 −130 −140 1k10020 10k 20k
superior analog characteristics that the process offers. block diagram of the PGA2320. via the serial control port. VOUT R (pin 11) and VOUT L (pin 14). Figure 1. PGA2320 Block Diagram
into SDI on the rising edge of SCLK. The protocol for the serial control port is shown in Figure 2. Figure 2. Serial Interface Protocol
analog ground (AGNDR or AGNDL). Figure 3. Serial Interface Timing Requirements
enough SCLK cycles to load all devices. to minimize audible artifacts. Figure 4. Daisy-Chaining Multiple PGA2320 Devices
recommended PCB floor plan for the PGA2320. through 16 are on the analog side of the board. Figure 6. Typical PCB Layout Floor Plan
www.ti.com 23-May-2025 PACKAGING INFORMATION Orderable part number Status (1) Material type (2) Package | Pins Package qty | Carrier RoHS (3) Lead finish/ Ball material (4) MSL rating/ Peak reflow (5) Op temp (°C) Part marking (6) PGA2320IDW Active Production SOIC (DW) | 16 40 | TUBE Yes NIPDAU Level-2-260C-1 YEAR -40 to 85 PGA2320I PGA2320IDW.A Active Production SOIC (DW) | 16 40 | TUBE Yes NIPDAU Level-2-260C-1 YEAR -40 to 85 PGA2320I PGA2320IDW1G4.A Active Production SOIC (DW) | 16 40 | TUBE Yes NIPDAU Level-2-260C-1 YEAR -40 to 85 PGA2320I PGA2320IDWR Active Production SOIC (DW) | 16 2000 | LARGE T&R Yes NIPDAU Level-2-260C-1 YEAR -40 to 85 PGA2320I PGA2320IDWR.A Active Production SOIC (DW) | 16 2000 | LARGE T&R Yes NIPDAU Level-2-260C-1 YEAR -40 to 85 PGA2320I (1) Status: For more details on status, see our product life cycle. (2) Material type: When designated, preproduction parts are prototypes/experimental devices, and are not yet approved or released for full production. Testing and final process, including without limitation quality assurance, reliability performance testing, and/or process qualification, may not yet be complete, and this item is subject to further changes or possible discontinuation. If available for ordering, purchases will be subject to an additional waiver at checkout, and are intended for early internal evaluation purposes only. These items are sold without warranties of any kind. (3) RoHS values: Yes, No, RoHS Exempt. See the TI RoHS Statement for additional information and value definition. (4) Lead finish/Ball material: Parts may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two lines if the finish value exceeds the maximum column width. (5) MSL rating/Peak reflow: The moisture sensitivity level ratings and peak solder (reflow) temperatures. In the event that a part has multiple moisture sensitivity ratings, only the lowest level per JEDEC standards is shown. Refer to the shipping label for the actual reflow temperature that will be used to mount the part to the printed circuit board. (6) Part marking: There may be an additional marking, which relates to the logo, the lot trace code information, or the environmental category of the part. Multiple part markings will be inside parentheses. Only one part marking contained in parentheses and separated by a "~" will appear on a part. If a line is indented then it is a continuation of the previous line and the two combined represent the entire part marking for that device. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 1
PACKAGE MATERIALS INFORMATION www.ti.com 23-May-2025 TAPE AND REEL INFORMATION Reel Width (W1) REEL DIMENSIONS A0B0K0WDimension designed to accommodate the component lengthDimension designed to accommodate the component thicknessOverall width of the carrier tapePitch between successive cavity centersDimension designed to accommodate the component width TAPE DIMENSIONSK0 P1B0WA0Cavity QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE Pocket QuadrantsSprocket HolesQ1Q1Q2Q2Q3Q3Q4Q4User Direction of Feed P1ReelDiameter *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Reel Diameter (mm) Reel Width W1 (mm) (mm) (mm) (mm) (mm) W (mm) Pin1 Quadrant Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION www.ti.com 23-May-2025 TAPE AND REEL BOX DIMENSIONS Width (mm) W LH *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) PGA2320IDWR SOIC DW 16 2000 350.0 350.0 43.0 Pack Materials-Page 2
PACKAGE MATERIALS INFORMATION www.ti.com 23-May-2025 TUBE L - Tube length T - Tube height W - Tube width B - Alignment groove width *All dimensions are nominal Device Package Name Package Type Pins SPQ L (mm) W (mm) T (µm) B (mm) PGA2320IDW DW SOIC 16 40 506.98 12.7 4826 6.6 PGA2320IDW.A DW SOIC 16 40 506.98 12.7 4826 6.6 PGA2320IDW1G4.A DW SOIC 16 40 506.98 12.7 4826 6.6 Pack Materials-Page 3
www.ti.com GENERIC PACKAGE VIEW This image is a representation of the package family, actual package may vary. Refer to the product data sheet for package details. SOIC - 2.65 mm max heightDW 16 SMALL OUTLINE INTEGRATED CIRCUIT7.5 x 10.3, 1.27 mm pitch 4224780/A
www.ti.com PACKAGE OUTLINE C TYP10.63 9.97
2.65 MAX
14X 1.27 16X 0.51 0.31 8.89 TYP0.33 0.10 0 - 8 0.3 0.1 (1.4) 0.25 GAGE PLANE 1.27 0.40 A NOTE 3 10.5 10.1 B NOTE 4 7.6 7.4 4220721/A 07/2016 SOIC - 2.65 mm max heightDW0016A SOIC NOTES: 1. All linear dimensions are in millimeters. Dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed 0.15 mm, per side. 4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm, per side. 5. Reference JEDEC registration MS-013. 1 16
0.25 C A B
0.1 C SEE DETAIL A DETAIL A TYPICAL SCALE 1.500
www.ti.com EXAMPLE BOARD LAYOUT
0.07 MAX
0.07 MIN
(9.3) 14X (1.27) R0.05 TYP 16X (2) 16X (0.6) 4220721/A 07/2016 SOIC - 2.65 mm max heightDW0016A SOIC NOTES: (continued) 6. Publication IPC-7351 may have alternate designs. 7. Solder mask tolerances between and around signal pads can vary based on board fabrication site. METAL SOLDER MASK OPENING NON SOLDER MASK DEFINED SOLDER MASK DETAILS OPENING SOLDER MASK METAL SOLDER MASK DEFINED LAND PATTERN EXAMPLE SCALE:7X SYMM 8 9 SEE DETAILS SYMM
www.ti.com EXAMPLE STENCIL DESIGN R0.05 TYP 16X (2) 16X (0.6) 14X (1.27) (9.3) 4220721/A 07/2016 SOIC - 2.65 mm max heightDW0016A SOIC NOTES: (continued) 8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 9. Board assembly site may have different recommendations for stencil design. SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL SCALE:7X SYMM SYMM 8 9
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