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Sample & Buy T echnical Documents Tools & Software Support & Community PGA2311 SBOS218B –DECEMBER 2001–REVISED JANUARY 2016 PGA2311StereoAudioVolumeControl
1 Features 3 Description
The PGA2311 device is a high-performance, stereo 1• Digitally-Controlled Analog Volume Control audio volume control designed for professional and– Two Independent Audio Channels high-end consumer audio systems. The PGA2311 – Serial Control Interface uses an internal high-performance operational amplifier to yield low noise and distortion. The– Zero Crossing Detection PGA2311 also provides the capability to drive 660-Ω– Mute Function loads directly without buffering. The 3-wire serial
- Wide Gain and Attenuation Range: +31.5 dB to control interface allows for connection to a wide −95.5 dB with 0.5-dB Steps variety of host controllers, in addition to support for daisy-chaining of multiple PGA2311 devices.• Low Noise and Distortion – 120-dB Dynamic Range Device Information(1) – 0.0004% THD+N at 1 kHz (U-Grade) PART NUMBER PACKAGE BODY SIZE (NOM) – 0.0002% THD+N at 1 kHz (A-Grade) SOIC (16) 7.5 mm × 10.30 mm PGA2311• Noise-Free Level Transitions PDIP (16) 6.35 mm × 19.30 mm
- Low Interchannel Crosstalk −130 dBFS (1) For all available packages, see the orderable addendum at the end of the data sheet.• Power Supplies: ±5-V Analog, +5-V Digital
- Available in DIP-16 and SOL-16 Packages Stereo Audio Volume Control
- Pin and Software Compatible With the Crystal CS3310
2 Applications
- Audio Amplifiers
- Mixing Consoles
- Multi-Track Recorders
- Broadcast Studio Equipment
- Musical Instruments
- Effects Processors
- A/V Receivers
- Car Audio Systems An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA.
SBOS218B –DECEMBER 2001–REVISED JANUARY 2016 www.ti.com Table of Contents
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision A (June 2002) to Revision B Page
- Added ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and
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Product Folder Links: PGA2311
www.ti.com SBOS218B –DECEMBER 2001–REVISED JANUARY 2016
5 Pin Configuration and Functions
NO. NAME
1 ZCEN I Zero crossing enable input (Active HIGH)
2 CS I Chip select input (Active LOW)
3 SDI I Serial data input
4 VD+ I Digital power supply, +5 V
5 DGND — Digital ground
6 SCLK I Serial clock input
7 SDO O Serial clock output
8 MUTE I Mute control input (Active LOW)
9 VINR I Analog input, Right channel
10 AGNDR — Analog ground, Right channel
11 VOUTR O Analog output, Right channel
12 VA+ I Analog power supply, +5 V
13 VA– I Analog power supply, –5 V
14 VOUTL O Analog output, Left channel
15 AGNDL — Analog ground, Left channel
16 VINL I Analog input, Left channel
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SBOS218B –DECEMBER 2001–REVISED JANUARY 2016 www.ti.com
6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1) MIN MAX UNIT VA+ 5.5 VA– –5.5 Supply voltage V VD+ 5.5 VA+ to VD+ < ±0.3 Analog input voltage 0 VA+, VA− V Digital input voltage –0.3 VD+ V Operating temperature –40 85 °C Junction temperature 150 °C Lead temperature (soldering, 10s) 300 °C Package temperature (IR reflow, 10s) 235 °C Storage temperature, Tstg –65 150 °C (1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
6.2 ESD Ratings
PGA2311 in 16-Pin SOIC Package Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±2000 V(ESD) Electrostatic discharge V Charged-device model (CDM), per JEDEC specification JESD22-C101(2) ±1500 PGA2311 in 16-Pin PDIP Package V(ESD) Electrostatic discharge Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±2000 V (1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. (2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted) MIN NOM MAX UNIT VA+ Positive analog power supply 4.75 5 5.25 V VA– Negative analog power supply –4.75 –5 –5.25 V VD+ Digital power supply 4.75 5 5.25 V Operating temperature –40 25 85 °C
6.4 Thermal Information
THERMAL METRIC(1) N (PDIP) DW (SOIC) UNIT
16 PINS 16 PINS
RθJA Junction-to-ambient thermal resistance 39.9 83 °C/W RθJC(top) Junction-to-case (top) thermal resistance 26.2 44 °C/W RθJB Junction-to-board thermal resistance 20.1 40.5 °C/W ψJT Junction-to-top characterization parameter 10.7 11.5 °C/W ψJB Junction-to-board characterization parameter 19.9 40.2 °C/W RθJC(bot) Junction-to-case (bottom) thermal resistance — — °C/W (1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report, SPRA953.
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www.ti.com SBOS218B –DECEMBER 2001–REVISED JANUARY 2016
6.5 Electrical Characteristics
At TA = +25°C, VA+ = +5 V, VA− = –5 V, VD+ = +5 V, RL = 100 kΩ, CL = 20 pF, BW measure = 10 Hz to 20 kHz, unless otherwise noted. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT DC CHARACTERISTICS Step size 0.5 dB Gain error Gain Setting = 31.5 dB ±0.05 dB Gain matching ±0.05 dB Input resistance 10 kΩ PGA2311P, U (U−Grade) 3 Input capacitance pF PGA2311PA, UA (A−Grade) 7 AC CHARACTERISTICS PGA2311P, 0.0004% 0.001%U (U−Grade)VIN = 2 Vrms, fTHD+N = 1 kHz PGA2311PA, 0.0002% 0.0004%UA (A−Grade) Dynamic range VIN = AGND, Gain = 0 dB 116 120 dB PGA2311P, U (U−Grade) (VA−) + 1.25 (VA+) –1.25 Voltage range, Output V PGA2311PA, UA (A−Grade) (VA−) + 1.5 (VA−) − 1.5 Voltage range, Input (without 2.5 Vrmsclipping) Output noise VIN = AGND, Gain = 0 dB 2.5 4 μVRMS Interchannel crosstalk f = 1 kHz –130 dBFS OUTPUT BUFFER Offset voltage VIN = AGND, Gain = 0 dB 0.25 0.5 mV Load capacitance stability 100 pF Short-circuit current 50 mA Unity-gain bandwidth, Small signal 10 MHz DIGITAL CHARACTERISTICS High-level input voltage, VIH 2 VD+ V Low-level input voltage, VIL –0.3 0.8 V PGA2311P, (VA+) − 1U (U−Grade)High-level output voltage, VOH IO = 200 μA V PGA2311PA, (VD+) − 1UA (A−Grade) Low-level output voltage, VOL IO = –3.2 mA 0.4 V Input leakage current 1 10 µA SWITCHING CHARACTERISTICS fSCLK Serial clock (SCLK) frequency 0 6.25 MHz tPL Serial clock (SCLK) pulse width low 80 ns tPH Serial clock (SCLK) pulse width high 80 ns tMI MUTE Pulse width low 2 ms INPUT TIMING tSDS SDI setup time 20 ns tSDH SDI hold time 20 ns tCSCR CS falling to SCLK rising 90 ns tCFCS SCLK falling to CS rising 35 ns OUTPUT TIMING tCSO CS low to SDO active 35 ns tCFDO SCLK falling to SDO data valid 60 ns tCSZ CS high to SDO high impedance 100 ns Copyright © 2001–2016, Texas Instruments Incorporated Submit Documentation Feedback 5 Product Folder Links: PGA2311
SDI is latched on the rising edge of SCLK. SDO transitions on the falling edge of SCLK. Figure 1. Serial Interface Protocol
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Figure 2. Serial Interface Timing Requirements
6.6 Typical Characteristics
otherwise noted. All plots taken with PGA2311 A−Grade. Figure 3. Amplitude vs Frequency Figure 4. THD + N vs Amplitude Figure 5. THD + N vs Amplitude Figure 6. THD + N vs Frequency Figure 8. THD + N vs Input Source ImpedanceFigure 7. THD + N vs Frequency
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7 Detailed Description
7.1 Overview
The PGA2311 is a stereo audio volume control that can be used in a wide array of professional and consumer audio equipment. The PGA2311 is fabricated in a sub−micron CMOS process. The heart of the PGA2311 is a resistor network, an analog switch array, and a high−performance operational amplifier stage. The switches select taps in the resistor network that determine the gain of the amplifier stage. Switch selections are programmed using a serial control port. The serial port allows connection to a wide variety of host controllers. Functional Block Diagram shows a model diagram of the PGA2311.
7.2 Functional Block Diagram
7.3 Feature Description
7.3.1 Analog Inputs and Outputs
The PGA2311 includes two independent channels (referred to as the left and right channels). Each channel has a corresponding input and output pin. The input and output pins are unbalanced, or referenced to analog ground (either AGNDR or AGNDL). The inputs are VINR (pin 9) and VINL (pin 16), while the outputs are VOUTR (pin 11) and VOUTL (pin 14). The input and output pins may swing within 1.25 V of the analog power supplies, VA+ (pin 12) and VA− (pin 13). Given VA+ = +5 V and VA− = −5 V, the maximum input or output voltage range is 7.5 Vp-p. For optimal performance, drive the PGA2311 with a low source impedance. A source impedance of 600 Ω or less is recommended. Source impedances up to 2 kΩ cause minimal degradation of THD+N. Refer to Figure 8 for more details.
7.3.2 Gain Settings
The gain for each channel is set by its corresponding 8−bit code, either R[7:0] or L[7:0] (see Figure 1). The gain code data is straight binary format. If N equals the decimal equivalent of R[7:0] or L[7:0], then the following relationships exist for the gain settings:
- For N = 0: Mute Condition. The input multiplexer is connected to analog ground (AGNDR or AGNDL).
- For N = 1 to 255: Gain (dB) = 31.5 − [0.5 w (255 − N)]
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This results in a gain range of +31.5 dB (with N = 255) to −95.5 dB (with N = 1). detector and timeout circuitry is discussed in Zero Crossing Detection.
7.3.3 Daisy-Chaining Multiple PGA2311 Devices
where N is the number of devices connected in the chain, to allow enough SCLK cycles to load all devices. Figure 12. Daisy-Chaining Multiple PGA2311 Devices
7.3.4 Zero Crossing Detection
enabled or disabled using the ZCEN input (pin 1). When ZCEN is LOW, zero crossing detection is disabled. When ZCEN is HIGH, zero crossing detection is enabled. elapsed. In the case of a time-out, the new gain setting takes effect with no attempt to minimize audible artifacts.
SBOS218B –DECEMBER 2001–REVISED JANUARY 2016 www.ti.com Feature Description (continued)
7.3.5 MUTE Function
Muting can be achieved by either hardware or software control. Hardware muting is accomplished through the MUTE input, and software muting by loading all zeroes into the volume control register. MUTE disconnects the internal buffer amplifiers from the output pins and terminates AOUTL and AOUTR with 10- kΩ resistors to ground. The mute is activated with a zero crossing detection (independent of the zero cross enable status), or an 16-ms time-out to eliminate any audible clicks or pops. MUTE also initiates an internal offset calibration. A software mute is implemented by loading all zeroes into the volume control register. The internal amplifier is set to unity gain, with the amplifier input connected to AGND.
7.4 Device Functional Modes
7.4.1 Power−Up State
On power up, power−up reset is activated for about 100 ms, during which the circuit is in hardware MUTE state and all internal flip-flops are reset. At the end of this period, the offset calibration is initiated without any external signals. Once this has been completed, the gain byte value for both the left and right channels are set to 00HEX, or the software MUTE condition. The gain remains at this setting until the host controller programs new settings for for each channel via the serial control port. If the power supply voltage drops below ±3.2 V during normal operation, the circuit enters a hardware MUTE state. A power-up sequence initiates if the power supply voltage returns to greater than ±3.2 V.
7.5 Programming
The serial control port is used to program the gain settings for the PGA2311. The serial control port includes three input pins and one output pin. The inputs include CS (pin 2), SDI (pin 3), and SCLK (pin 6). The sole output pin is SDO (pin 7). The CS pin functions as the chip select input. Data may be written to the PGA2311 only when CS is LOW. SDI is the serial data input pin. Control data is provided as a 16-bit word at the SDI pin, 8 bits each for the left and right channel gain settings. Data is formatted as MSB first, in straight binary code. SCLK is the serial clock input. Data is clocked into SDI on the rising edge of SCLK. SDO is the serial data output pin, and used when daisy-chaining multiple PGA2311 devices. Daisy-chain operation is described in Daisy-Chaining Multiple PGA2311 Devices. SDO is a tri-state output, and assumes a high impedance state when CS is HIGH. The protocol for the serial control port is shown in Figure 1. See Figure 2 for detailed timing specifications for the serial control port.
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8 Application and Implementation
validate and test their design implementation to confirm system functionality.
8.1 Application Information
through a serial interface in 0.5-dB steps, ranging from a gain of +31.5 dB down to an attenuation of −95.5 dB.
8.2 Typical Application
placed as close to the PGA2311 package as physically possible. Figure 13. Recommended Connection Diagram
8.2.1 Design Requirements
- Wide dynamic range, +35.5 dB to –95.5 dB
- Operate from 5-V digital supply and ±5-V analog supplies
- Digitally-controlled analog volume
8.2.2 Detailed Design Procedure
8.2.3 Application Curve
Figure 14. PGA2311 Operating at 0 dB, –6 dB and –12 dB
9 Power Supply Recommendations
the PGA2311 package as physically possible.
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10 Layout
10.1 Layout Guidelines
10.2 Layout Example
Figure 15. Typical PCB Layout Floor Plan
SBOS218B –DECEMBER 2001–REVISED JANUARY 2016 www.ti.com
11 Device and Documentation Support
11.1 Documentation Support
11.1.1 Related Documentation
For related documentation, see the following:
- Circuit Board Layout Techniques, SLOA089
- Shelf-Life Evaluation of Lead-Free Component Finishes, SZZA046
11.2 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use. TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help solve problems with fellow engineers. E2E Audio Amplifier Forum TI's Engineer-to-Engineer (E2E) Community for Audio Amplifiers. Created to foster collaboration among engineers. Ask questions and receive answers in real-time.
11.3 Trademarks
E2E is a trademark of Texas Instruments. All other trademarks are the property of their respective owners.
11.4 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates.
11.5 Glossary
SLYZ022 — TI Glossary. This glossary lists and explains terms, acronyms, and definitions.
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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www.ti.com 24-Apr-2015 Addendum-Page 1 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/Ball Finish (6) MSL Peak Temp (3) Op Temp (°C) Device Marking (4/5) Samples PGA2311P ACTIVE PDIP N 16 25 Green (RoHS & no Sb/Br) CU NIPDAU N / A for Pkg Type PGA2311P PGA2311PA ACTIVE PDIP N 16 25 Green (RoHS & no Sb/Br) CU NIPDAU N / A for Pkg Type PGA2311P A PGA2311PAG4 ACTIVE PDIP N 16 25 Green (RoHS & no Sb/Br) CU NIPDAU N / A for Pkg Type PGA2311P A PGA2311PG4 ACTIVE PDIP N 16 25 Green (RoHS & no Sb/Br) CU NIPDAU N / A for Pkg Type PGA2311P PGA2311U ACTIVE SOIC DW 16 40 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 85 PGA2311U PGA2311U/1K ACTIVE SOIC DW 16 1000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 85 PGA2311U PGA2311U/1KG4 ACTIVE SOIC DW 16 1000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 85 PGA2311U PGA2311UA ACTIVE SOIC DW 16 40 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR PGA2311U A PGA2311UA/1K ACTIVE SOIC DW 16 1000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR PGA2311U A PGA2311UAG4 ACTIVE SOIC DW 16 40 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR PGA2311U A PGA2311UG4 ACTIVE SOIC DW 16 40 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 85 PGA2311U (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
www.ti.com 24-Apr-2015 Addendum-Page 2 Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
*All dimensions are nominal Device Package Type Package Drawing Pins SPQ Reel Diameter (mm) Reel Width W1 (mm) (mm) (mm) (mm) (mm) W (mm) Pin1 Quadrant PACKAGE MATERIALS INFORMATION www.ti.com 21-Apr-2015 Pack Materials-Page 1
*All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) PGA2311U/1K SOIC DW 16 1000 367.0 367.0 38.0 PGA2311UA/1K SOIC DW 16 1000 367.0 367.0 38.0 PACKAGE MATERIALS INFORMATION www.ti.com 21-Apr-2015 Pack Materials-Page 2
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