PGA2310 TI | Alldatasheet
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VA+VA− VD+ DGND 12 13 4 5 1 1 Product Folder Sample & Buy T echnical Documents Tools & Software Support & Community PGA2310 SBOS207C –OCTOBER 2001–REVISED DECEMBER 2015 PGA2310StereoAudioVolumeControl
1 Features 3 Description
The PGA2310 is a high-performance, stereo audio 1• Digitally-Controlled Analog Volume Control: volume control designed for professional and high-– Two Independent Audio Channels end consumer audio systems. The ability to operate – Serial Control Interface from ±15-V analog power supplies enables the PGA2310 to process input signals with large voltage– Zero Crossing Detection swings, thereby preserving the dynamic range– Mute Function available in the overall signal path. Using high
- Wide Gain and Attenuation Range: 31.5 dB to performance operational amplifier stages internal to −95.5 dB With 0.5-dB Steps the PGA2310 yields low noise and distortion, while providing the capability to drive 600-Ω loads directly• Low Noise and Distortion: without buffering. The three-wire serial control– 120-dB Dynamic Range interface allows for connection to a wide variety of – 0.0004% THD+N at 1 kHz host controllers, in addition to support for daisy- chaining multiple PGA2310 devices.• Low Interchannel Crosstalk: −126 dBFS
- Noise-Free Level Transitions Device Information(1)
- Power Supplies: 15-V Analog, 5-V Digital PART NUMBER PACKAGE BODY SIZE (NOM)
- Available in DIP−16 and SOL−16 Packages SOIC (16) 7.50 mm × 10.30 mm PGA2310• Pin and Software Compatible With the PGA2311 PDIP (16) 6.35 mm × 19.30 mm and Cirrus Logic CS3310™ (1) For all available packages, see the orderable addendum at the end of the data sheet.
2 Applications
- Audio Amplifiers
- Mixing Consoles
- Multi-Track Recorders
- Broadcast Studio Equipment
- Musical Instruments
- Effects Processors
- A/V Receivers
- Car Audio Systems Stereo Audio Volume Control An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA.
SBOS207C –OCTOBER 2001–REVISED DECEMBER 2015 www.ti.com Table of Contents
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision B (June 2004) to Revision C Page
- Added ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and
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Product Folder Links: PGA2310
V V + A A VOUTR AGNDR VINR 1 1 PGA2310 PGA2310 www.ti.com SBOS207C –OCTOBER 2001–REVISED DECEMBER 2015
5 Pin Configuration and Functions
16 Pins SOIC and PDIP
NO. NAME
1 ZCEN I Zero Crossing Enable Input (Active High)
2 CS I Chip Select Input (Active Low)
3 SDI I Serial Data Input
4 VD+ I Digital Power Supply, 5 V
5 DGND — Digital Ground
6 SCLK I Serial Clock Input
7 SDO O Serial Data Output
8 MUTE I Mute Control Input (Active Low)
9 VINR I Analog Input, Right Channel
10 AGNDR — Analog Ground, Right Channel
11 VOUTR O Analog Output, Right Channel
12 VA+ I Analog Power Supply, 15 V
13 VA– I Analog Power Supply, –15 V
14 VOUTL O Analog Output, Left Channel
15 AGNDL — Analog Ground, Left Channel
16 VINL I Analog Input, Left Channel
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1) MIN MAX UNIT VA+ 16 Supply Voltage VA– –16 V VD+ 6.5 Analog input voltage 0 VA+,VA– V Digital input voltage –0.3 VD+ V Operating temperature –55 125 °C Junction temperature 150 °C Lead temperature (soldering, 10 s) 300 °C Package temperature (IR, reflow, 10 s) 235 °C Tstg Storage temperature –65 150 °C (1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
6.2 ESD Ratings
V(ESD) Electrostatic discharge Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±4000 V (1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted) MIN NOM MAX UNIT VA+ Positive analog power supply 4.5 15 15.5 V VA– Negative analog power supply –4.5 –15 –15.5 V VD+ Digital power supply 4.5 5 5.5 V Operating temperature –55 25 125 °C
6.4 Thermal Information
THERMAL METRIC(1) D (SOIC) P (PDIP) UNIT
16 PINS 16 PINS
RθJA Junction-to-ambient thermal resistance 83 39.9 °C/W RθJC(top) Junction-to-case (top) thermal resistance 44 26.2 °C/W RθJB Junction-to-board thermal resistance 40.5 20.1 °C/W ψJT Junction-to-top characterization parameter 11.5 10.7 °C/W ψJB Junction-to-board characterization parameter 40.2 19.9 °C/W RθJC(bot) Junction-to-case (bottom) thermal resistance N/A N/A °C/W (1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report, SPRA953.
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Product Folder Links: PGA2310
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6.5 Electrical Characteristics
At TA = 25°C, VA+ = 15 V, VA− = −15 V, VD+ = 5 V, RL = 100 kΩ, CL = 20 pF, BW measure = 10 Hz to 20 kHz, unless otherwise noted. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT DC CHARACTERISTICS Step Size 0.5 dB Gain Error Gain Setting = 31.5 dB ±0.05 dB Gain Matching ±0.05 dB Input Resistance 10 kΩ Input Capacitance 7 pF AC CHARACTERISTICS THD+N VIN = 10 VPP, f = 1 kHz 0.0004% 0.001% Dynamic Range VIN = AGND, Gain = 0 dB 116 120 dB Voltage Range, Input and Output (VA−) + 1.5 (VA−) − 1.5 V Output Noise VIN = AGND, Gain = 0 dB 9.5 13.5 μVRMS Interchannel Crosstalk f = 1 kHz –126 dBFS OUTPUT BUFFER Offset Voltage VIN = AGND, Gain = 0 dB 0.5 3 mV Load Capacitance Stability 1000 pF Short-Circuit Current 35 mA Unity-Gain Bandwidth, Small Signal 1.5 MHz DIGITAL CHARACTERISTICS High-Level Input Voltage, VIH 2 VD+ V Low-Level Input Voltage, VIL –0.3 0.8 V High-Level Output Voltage, VOH IO = 200 μA (VD+) − 1 V Low-Level Output Voltage, VOL IO = –3.2 mA 0.4 V Input Leakage Current 1 10 µA SWITCHING CHARACTERISTICS tSCLK Serial Clock (SCLK) Frequency 0 6.25 MHz tPL Serial Clock (SCLK) Pulse Width Low 80 ns tPH Serial Clock (SCLK) Pulse Width High 80 ns tMI MUTE Pulse Width Low 2 ms INPUT TIMING tSDS SDI Setup Time 20 ns tSDH SDI Hold Time 20 ns tCSCR CS Falling to SCLK Rising 90 ns tCFCS SCLK Falling to CS Rising 35 ns OUTPUT TIMING tCSO CS Low to SDO Active 35 ns tCFDO SCLK Falling to SDO Data Valid 60 ns tCSZ CS High to SDO High Impedance 100 ns POWER SUPPLY VA+ 4.5 15 15.5 Operating Voltage VA– –4.5 –15 –15.5 V VD+ 4.5 5 5.5 IA+ VA+ = 15 V 7.5 10 Quiescent Current IA– VA– = –15 V 7.7 10 mA ID+ VD+ = 5 V 0.8 1.5 Copyright © 2001–2015, Texas Instruments Incorporated Submit Documentation Feedback 5 Product Folder Links: PGA2310
6.6 Typical Characteristics
Figure 1. Frequency Response Figure 2. THD+N vs Amplitude Figure 3. THD+N vs Frequency Figure 4. THD+N vs Frequency
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7 Detailed Description
7.1 Overview
The PGA2310 is a stereo audio volume control that can be used in a wide array of professional and consumer audio equipment. The PGA2310 is fabricated in a mixed-signal BiCMOS process for superior analog characteristics. The heart of the PGA2310 is a resistor network, an analog switch array, and a high-performance bipolar op amp stage. The switches select taps in the resistor network that determine the gain of the amplifier stage. Switch selections are programmed using a serial control port. The serial port allows connection to a wide variety of host controllers.
7.2 Functional Block Diagram
7.3 Feature Description
7.3.1 Analog Inputs and Outputs
The PGA2310 includes two independent channels, referred to as the left and right channels. Each channel has a corresponding input and output pin. The input and output pins are unbalanced, or referenced to analog ground (either AGNDR or AGNDL). The inputs are VINR (pin 9) and VINL (pin 16), while the outputs are VOUTR (pin 11) and VOUTL (pin 14). The input and output pins may swing within 1.5 V of the analog power supplies, VA+ (pin 12) and VA− (pin 13). Given VA+ = 15 V and VA− = −15 V, the maximum input or output voltage range is 27 VPP. Drive the PGA2310 with a low source impedance. If a source impedance of greater than 600 Ω is used, the distortion performance of the PGA2310 begins to degrade.
7.3.2 Serial Control Port
The serial control port is used to program the gain settings for the PGA2310. The serial control port includes three input pins and one output pin. The inputs include CS (pin 2), SDI (pin 3), and SCLK (pin 6). The sole output pin is SDO (pin 7).
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Product Folder Links: PGA2310
SDI is latched on the rising edge of SCLK. SDO transitions on the falling edge of SCLK. is clocked into SDI on the rising edge of SCLK. high impedance state when CS is high. Figure 10. Serial Interface Protocol
Figure 11. Serial Interface Timing Requirements
7.3.3 Gain Settings
- For N = 0: Mute Condition. The input multiplexer is connected to analog ground (AGNDR or AGNDL). This results in a gain range of 31.5 dB (with N = 255) to −95.5 dB (with N = 1). Changes in gain setting may be made with or without zero crossing detection. The operation of the zero crossing detector and time-out circuitry is discussed in Zero Crossing Detection.
7.3.4 Daisy-Chaining Multiple PGA2310 Devices
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Figure 12. Daisy-Chaining Multiple PGA2310 Devices number of devices connected in the chain, to allow enough SCLK cycles to load all devices.
7.3.5 Zero Crossing Detection
disabled. When ZCEN is high, zero crossing detection is enabled. to minimize audible artifacts.
7.3.6 Mute Function
SBOS207C –OCTOBER 2001–REVISED DECEMBER 2015 www.ti.com
7.4 Device Functional Modes
7.4.1 Power-Up State
On power up, all internal flip-flops are reset. The gain byte value for both the left and right channels are set to 00HEX, or mute condition. The gain remains at this setting until the host controller programs new settings for each channel using the serial control port.
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Product Folder Links: PGA2310
C2, C3, C5 = 0.1µF ceramic or metal film. C1, C4, C6 = 10µF tantalum or aluminum electrolytic.
8 Application and Implementation
validate and test their design implementation to confirm system functionality.
8.1 Application Information
through a serial interface in 0.5-dB steps, ranging from a gain of 31.5 dB down to an attenuation of −95.5 dB.
8.2 Typical Application
Figure 13 depicts the recommended connections for the PGA2310. Figure 13. Recommended Connection Diagram
8.2.1 Design Requirements
- Wide dynamic range: 35.5 dB to –95.5 dB
- Operate from 5-V digital supply and ±15-V analog supplies
- Digitally controlled analog volume
8.2.2 Detailed Design Procedure
8.2.3 Application Curve
Figure 14. PGA2310 Operating at 0 dB, –6 dB and –12 dB
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9 Power Supply Recommendations
digital power supply ranging from 4.5 V to 5.5 V.
10 Layout
10.1 Layout Guidelines
recommended PCB floor plan for the PGA2310.
10.2 Layout Example
Figure 15. Typical PCB Layout Floor Plan
SBOS207C –OCTOBER 2001–REVISED DECEMBER 2015 www.ti.com
11 Device and Documentation Support
11.1 Device Support
11.1.1 Development Support
For immediate development support with the PGA2310, visit Audio Amplifiers Section of the TI E2E Support Community. Here you may view previously answered questions or submit a new question to the team of application experts.
11.2 Documentation Support
11.2.1 Related Documentation
For related documentation see the following:
- Circuit Board Layout Techniques, SLOA089
- Shelf-Life Evaluation of Lead-Free Component Finishes, SZZA046
- PGA2310-EVM: Evaluation Module User's Manual, SBOU012
11.3 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use. TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help solve problems with fellow engineers. Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and contact information for technical support.
11.4 Trademarks
E2E is a trademark of Texas Instruments. CS3310 is a trademark of Cirrus Logic, Inc.. All other trademarks are the property of their respective owners.
11.5 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates.
11.6 Glossary
SLYZ022 — TI Glossary. This glossary lists and explains terms, acronyms, and definitions.
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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Product Folder Links: PGA2310
www.ti.com 7-Oct-2025 PACKAGING INFORMATION Orderable part number Status (1) Material type (2) Package | Pins Package qty | Carrier RoHS (3) Lead finish/ Ball material (4) MSL rating/ Peak reflow (5) Op temp (°C) Part marking (6) PGA2310PA Active Production PDIP (N) | 16 25 | TUBE Yes NIPDAU N/A for Pkg Type -40 to 85 PGA2310PA PGA2310PA.A Active Production PDIP (N) | 16 25 | TUBE Yes NIPDAU N/A for Pkg Type -40 to 85 PGA2310PA PGA2310UA Active Production SOIC (DW) | 16 40 | TUBE Yes NIPDAU Level-2-260C-1 YEAR -40 to 85 PGA2310UA PGA2310UA.A Active Production SOIC (DW) | 16 40 | TUBE Yes NIPDAU Level-2-260C-1 YEAR -40 to 85 PGA2310UA PGA2310UA/1K Active Production SOIC (DW) | 16 1000 | LARGE T&R Yes NIPDAU Level-2-260C-1 YEAR -40 to 85 PGA2310UA PGA2310UA/1K.A Active Production SOIC (DW) | 16 1000 | LARGE T&R Yes NIPDAU Level-2-260C-1 YEAR -40 to 85 PGA2310UA (1) Status: For more details on status, see our product life cycle. (2) Material type: When designated, preproduction parts are prototypes/experimental devices, and are not yet approved or released for full production. Testing and final process, including without limitation quality assurance, reliability performance testing, and/or process qualification, may not yet be complete, and this item is subject to further changes or possible discontinuation. If available for ordering, purchases will be subject to an additional waiver at checkout, and are intended for early internal evaluation purposes only. These items are sold without warranties of any kind. (3) RoHS values: Yes, No, RoHS Exempt. See the TI RoHS Statement for additional information and value definition. (4) Lead finish/Ball material: Parts may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two lines if the finish value exceeds the maximum column width. (5) MSL rating/Peak reflow: The moisture sensitivity level ratings and peak solder (reflow) temperatures. In the event that a part has multiple moisture sensitivity ratings, only the lowest level per JEDEC standards is shown. Refer to the shipping label for the actual reflow temperature that will be used to mount the part to the printed circuit board. (6) Part marking: There may be an additional marking, which relates to the logo, the lot trace code information, or the environmental category of the part. Multiple part markings will be inside parentheses. Only one part marking contained in parentheses and separated by a "~" will appear on a part. If a line is indented then it is a continuation of the previous line and the two combined represent the entire part marking for that device. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 1
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PACKAGE MATERIALS INFORMATION www.ti.com 24-Jul-2025 TAPE AND REEL INFORMATION Reel Width (W1) REEL DIMENSIONS A0B0K0WDimension designed to accommodate the component lengthDimension designed to accommodate the component thicknessOverall width of the carrier tapePitch between successive cavity centersDimension designed to accommodate the component width TAPE DIMENSIONSK0 P1B0WA0Cavity QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE Pocket QuadrantsSprocket HolesQ1Q1Q2Q2Q3Q3Q4Q4User Direction of Feed P1ReelDiameter *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Reel Diameter (mm) Reel Width W1 (mm) (mm) (mm) (mm) (mm) W (mm) Pin1 Quadrant Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION www.ti.com 24-Jul-2025 TAPE AND REEL BOX DIMENSIONS Width (mm) W LH *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) PGA2310UA/1K SOIC DW 16 1000 353.0 353.0 32.0 Pack Materials-Page 2
PACKAGE MATERIALS INFORMATION www.ti.com 24-Jul-2025 TUBE L - Tube length T - Tube height W - Tube width B - Alignment groove width *All dimensions are nominal Device Package Name Package Type Pins SPQ L (mm) W (mm) T (µm) B (mm) PGA2310PA N PDIP 16 25 506 13.97 11230 4.32 PGA2310PA.A N PDIP 16 25 506 13.97 11230 4.32 PGA2310UA DW SOIC 16 40 507 12.83 5080 6.6 PGA2310UA.A DW SOIC 16 40 507 12.83 5080 6.6 Pack Materials-Page 3
www.ti.com GENERIC PACKAGE VIEW This image is a representation of the package family, actual package may vary. Refer to the product data sheet for package details. SOIC - 2.65 mm max heightDW 16 SMALL OUTLINE INTEGRATED CIRCUIT7.5 x 10.3, 1.27 mm pitch 4224780/A
www.ti.com PACKAGE OUTLINE C TYP10.63 9.97
2.65 MAX
14X 1.27 16X 0.51 0.31 8.89 TYP0.33 0.10 0 - 8 0.3 0.1 (1.4) 0.25 GAGE PLANE 1.27 0.40 A NOTE 3 10.5 10.1 B NOTE 4 7.6 7.4 4220721/A 07/2016 SOIC - 2.65 mm max heightDW0016A SOIC NOTES: 1. All linear dimensions are in millimeters. Dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed 0.15 mm, per side. 4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm, per side. 5. Reference JEDEC registration MS-013. 1 16
0.25 C A B
0.1 C SEE DETAIL A DETAIL A TYPICAL SCALE 1.500
www.ti.com EXAMPLE BOARD LAYOUT
0.07 MAX
0.07 MIN
(9.3) 14X (1.27) R0.05 TYP 16X (2) 16X (0.6) 4220721/A 07/2016 SOIC - 2.65 mm max heightDW0016A SOIC NOTES: (continued) 6. Publication IPC-7351 may have alternate designs. 7. Solder mask tolerances between and around signal pads can vary based on board fabrication site. METAL SOLDER MASK OPENING NON SOLDER MASK DEFINED SOLDER MASK DETAILS OPENING SOLDER MASK METAL SOLDER MASK DEFINED LAND PATTERN EXAMPLE SCALE:7X SYMM 8 9 SEE DETAILS SYMM
www.ti.com EXAMPLE STENCIL DESIGN R0.05 TYP 16X (2) 16X (0.6) 14X (1.27) (9.3) 4220721/A 07/2016 SOIC - 2.65 mm max heightDW0016A SOIC NOTES: (continued) 8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 9. Board assembly site may have different recommendations for stencil design. SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL SCALE:7X SYMM SYMM 8 9
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