PGA2310 BURR-BROWN | Alldatasheet
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Technical content
FEATURES
/C0068DIGITALLY-CONTROLLED ANALOG VOLUME CONTROL: Two Independent Audio Channels Serial Control Interface Zero Crossing Detection Mute Function /C0068WIDE GAIN AND ATTENUATION RANGE: +31.5dB to −95.5dB with 0.5dB Steps /C0068LOW NOISE AND DISTORTION: 120dB Dynamic Range 0.0004% THD+N at 1kHz /C0068LOW INTERCHANNEL CROSSTALK: −126dBFS /C0068NOISE-FREE LEVEL TRANSITIONS /C0068POWER SUPPLIES: /C004315V Analog, +5V Digital /C0068AVAILABLE IN DIP−16 AND SOL−16 PACKAGES /C0068PIN AND SOFTWARE COMPATIBLE WITH THE PGA2311 AND CIRRUS LOGIC CS3310 /C0069
APPLICATIONS
/C0068AUDIO AMPLIFIERS /C0068MIXING CONSOLES /C0068MULTI-TRACK RECORDERS /C0068BROADCAST STUDIO EQUIPMENT /C0068MUSICAL INSTRUMENTS /C0068EFFECTS PROCESSORS /C0068A/V RECEIVERS /C0068CAR AUDIO SYSTEMS
DESCRIPTION
The PGA2310 is a high-performance, stereo audio volume control designed for professional and high-end consumer audio systems. The ability to operate from ±15V analog power supplies enables the PGA2310 to process input signals with large voltage swings, thereby preserving the dynamic range available in the overall signal path. Using high performance operational amplifier stages internal to the PGA2310 yields low noise and distortion, while providing the capability to drive 600Ω loads directly without buffering. The three-wire serial control interface allows for connection to a wide variety of host controllers, in addition to support for daisy-chaining of multiple PGA2310 devices. PGA2310 SBOS207B − OCT OBER 2001 − REVISED JUNE 2004 Stereo Audio Volume Control www.ti.com Copyright 2001 − 2004, Texas Instruments Incorporated Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. All trademarks are the property of their respective owners. /C0080/C0082/C0079/C0068/C0085/C0067/C0084/C0073/C0079/C0078 /C0068/C0065/C0084/C0065 /C0105/C0110/C0102/C0111/C0114/C0109/C0097/C0116/C0105/C0111/C0110 /C0105/C0115 /C0099/C0117/C0114/C0114/C0101/C0110/C0116 /C0097/C0115 /C0111/C0102 /C0112/C0117/C0098/C0108/C0105/C0099/C0097/C0116/C0105/C0111/C0110 /C0100/C0097/C0116/C0101/C0046 /C0080/C0114/C0111/C0100/C0117/C0099/C0116/C0115 /C0099/C0111/C0110/C0102/C0111/C0114/C0109 /C0116/C0111 /C0115/C0112/C0101/C0099/C0105/C0102/C0105/C0099/C0097/C0116/C0105/C0111/C0110/C0115 /C0112/C0101/C0114 /C0116/C0104/C0101 /C0116/C0101/C0114/C0109/C0115 /C0111/C0102 /C0084/C0101/C0120/C0097/C0115 /C0073/C0110/C0115/C0116/C0114/C0117/C0109/C0101/C0110/C0116/C0115 /C0115/C0116/C0097/C0110/C0100/C0097/C0114/C0100 /C0119/C0097/C0114/C0114/C0097/C0110/C0116/C0121/C0046 /C0080/C0114/C0111/C0100/C0117/C0099/C0116/C0105/C0111/C0110 /C0112/C0114/C0111/C0099/C0101/C0115/C0115/C0105/C0110/C0103 /C0100/C0111/C0101/C0115 /C0110/C0111/C0116 /C0110/C0101/C0099/C0101/C0115/C0115/C0097/C0114/C0105/C0108/C0121 /C0105/C0110/C0099/C0108/C0117/C0100/C0101 /C0116/C0101/C0115/C0116/C0105/C0110/C0103 /C0111/C0102 /C0097/C0108/C0108 /C0112/C0097/C0114/C0097/C0109/C0101/C0116/C0101/C0114/C0115/C0046
/C0080/C0071/C0065/C0050/C0051/C0049/C0048 SBOS207B − OCT OBER 2001 − REVISED JUNE 2004 www.ti.com This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. ABSOLUTE MAXIMUM RATINGS over operating free-air temperature range unless otherwise noted(1) PGA2310 UNIT VA+ +16.0 V Supply voltage VA− −16.0 VSupply voltage VD + +6.5 V Analog input voltage 0 to VA+, VA− V Digital input voltage −0.3 to VD + V Operating temperature range −55 to +125 °C Storage temperature range −65 to +150 °C Junction temperature +150 °C Lead temperature (soldering, 10s) +300 °C Package temperature (IR, reflow, 10s) +235 °C (1)Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to absolute maximum conditions for extended periods may degrade device reliability. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those specified is not implied. ORDERING INFORMATION (1) PRODUCT PACKAGE−LEAD PACKAGE DESIGNATOR SPECIFIED TEMPERATURE RANGE PACKAGE MARKING ORDERING NUMBER TRANSPORT MEDIA, QUANTITY DIP-16 N PGA2310P A PGA2310P A Rails, 25 PGA2310 SOL-16 DW −40°C to +85°C PGA2310UA PGA2310UA Rails, 48PGA2310 SOL-16 DW −40 C to +85C PGA2310UA PGA2310UA/1K Tape and Reel, 1000 (1)For the most current package and ordering information, see the Package Option Addendum located at the end of this data sheet.
/C0080/C0071/C0065/C0050/C0051/C0049/C0048 SBOS207B − OCT OBER 2001 − REVISED JUNE 2004 www.ti.com
ELECTRICAL CHARACTERISTICS
At TA = +25°C, VA+ = +15V, VA− = −15V, VD + = +5V, RL = 100kΩ, CL = 20pF, BW measure = 10Hz to 20kHz, unless otherwise noted. PGA2310 PARAMETER TEST CONDITIONS MIN TYP MAX UNIT DC CHARACTERISTICS Step Size 0.5 dB Gain Error Gain Setting = 31.5dB ±0.05 dB Gain Matching ±0.05 dB Input Resistance 10 kΩ Input Capacitance 7 pF AC CHARACTERISTICS THD+N VIN = 10VPP, f = 1kHz 0.0004 0.001 % Dynamic Range VIN = AGND, Gain = 0dB 116 120 dB Voltage Range, Input and Output (VA−) + 1.5 (VA−) − 1.5 V Output Noise VIN = AGND, Gain = 0dB 9.5 13.5 µVRMS Interchannel Crosstalk f = 1kHz −126 dBFS OUTPUT BUFFER Offset Voltage VIN = AGND, Gain = 0dB 0.5 3 mV Load Capacitance Stability 1000 pF Short-Circuit Current 35 mA Unity-Gain Bandwidth, Small Signal 1.5 MHz DIGITAL CHARACTERISTICS High-Level Input Voltage, VIH +2.0 VD + V Low-Level Input Voltage, VIL −0.3 0.8 V High-Level Output Voltage, VOH IO = 200µA (VD +) − 1.0 V Low-Level Output Voltage, VOL IO = −3.2mA 0.4 V Input Leakage Current 1 10 µA SWITCHING CHARACTERISTICS Serial Clock (SCLK) Frequency tSCLK 0 6.25 MHz Serial Clock (SCLK) Pulse Width Low tPH 80 ns Serial Clock (SCLK) Pulse Width High tPL 80 ns MUTE Pulse Width Low tMI 2.0 ms Input Timing SDI Setup Time tSDS 20 ns SDI Hold Time tSDH 20 ns CS Falling to SCLK Rising tCSCR 90 ns SCLK Falling to CS Rising tCFCS 35 ns Output Timing CS Low to SDO Active tCSO 35 ns SCLK Falling to SDO Data Valid tCFDO 60 ns CS High to SDO High Impedance tCSZ 100 ns POWER SUPPLY Operating Voltage Quiescent Current IA+ VA+ = +15V 7.5 10 mA IA− VA− = −15V 7.7 10 mA ID + VD + = +5V 0.8 1.5 mA
/C0080/C0071/C0065/C0050/C0051/C0049/C0048 SBOS207B − OCT OBER 2001 − REVISED JUNE 2004 www.ti.com ELECTRICAL CHARACTERISTICS (continued) At TA = +25°C, VA+ = +15V, VA− = −15V, VD + = +5V, RL = 100kΩ, CL = 20pF, BW measure = 10Hz to 20kHz, unless otherwise noted. PGA2310 PARAMETER UNITMAXTYPMINTEST CONDITIONS TEMPERATURE RANGE Specified Range −40 +85 °C Operating Range −55 +125 °C Storage Range −65 +150 °C Thermal Resistance, θJC DIP−16 60 °C/W SOL−16 50 °C/W PIN CONFIGURATION Top View ZCEN CS SDI VD + DGND SCLK SDO MUTE VINL AGNDL VOUT L VA− VA+ VOUT R AGNDR VINR PGA2310 PIN ASSIGNMENTS PIN NAME FUNCTION
1 ZCEN Zero Crossing Enable Input (Active High)
2 CS Chip Select Input (Active Low)
3 SDI Serial Data input
4 VD + Digital Power Supply, +5V
5 DGND Digital Ground
6 SCLK Serial Clock Input
7 SDO Serial Data Output
8 MUTE Mute Control Input (Active Low)
9 VINR Analog Input, Right Channel
10 AGNDR Analog Ground, Right Channel
11 VOUT R Analog Output, Right Channel
12 VA+ Analog Power Supply, +15V
13 VA− Analog Power Supply, −15V
14 VOUT L Analog Output, Left Channel
15 AGNDL Analog Ground, Left Channel
16 VINL Analog Input, Left Channel
/C0080/C0071/C0065/C0050/C0051/C0049/C0048 SBOS207B − OCT OBER 2001 − REVISED JUNE 2004 www.ti.com TYPICAL CHARACTERISTICS At TA = +25°C, VA+ = +15V, VA− = −15V, VD + = +5V, RL = 100kΩ, CL = 20pF, BW measure = 10Hz to 20kHz, unless otherwise noted. 0.8 0.6 0.4 0.2 −0.2 −0.4 −0.6 −0.8 FREQUENCY RESPONSE 10 1k 10k100 200k Frequency (Hz) Amplitude (dB) 0.1 0.01 0.001 0.0001 THD+N vs AMPLITUDE 100m 1 9 Amplitude (VRMS ) THD+N (%) 0.05 0.01 0.001 0.0001 20 1k 10k100 20k Frequency (Hz) THD+N (%) THD+N vs FREQUENCY (VIN = 3.0VRMS , Load = 100kΩ) 0.05 0.01 0.001 0.0001 20 1k 10k100 20k Frequency (Hz) THD+N (%) THD+N vs FREQUENCY (VIN = 3.0VRMS , Load = 600Ω) 0.05 0.01 0.001 0.0001 20 1k 10k 100 20k Frequency (Hz) THD+N (%) THD+N vs FREQUENCY (VIN = 8.5VRMS , Load = 100kΩ) 0.05 0.01 0.001 0.0001 20 1k 10k100 20k Frequency (Hz) THD+N (%) THD+N vs FREQUENCY (VIN = 8.5VRMS , Load = 600Ω)
/C0080/C0071/C0065/C0050/C0051/C0049/C0048 SBOS207B − OCTOBER 2001 − REVISED JUNE 2004 www.ti.com TYPICAL CHARACTERISTICS (continued) At TA = +25°C, VA+ = +15V, VA− = −15V, VD + = +5V, RL = 100kΩ, CL = 20pF, BW measure = 10Hz to 20kHz, unless otherwise noted. −10 −20 −30 −40 −50 −60 −70 −80 −90 −100 −110 −120 −130 −140 −150 −160 AMPLITUDE vs FREQUENCY (Crosstalk with fIN =1 k H z ) 20 4k 6k2k 10k 12k 8k 16k 18k 20k14k 22k Frequency (Hz) Amplitude (dBFS) −10 −20 −30 −40 −50 −60 −70 −80 −90 −100 −110 −120 −130 −140 −150 −160 AMPLITUDE vs FREQUENCY (Crosstalk with fIN =1 0 k H z ) 04 k 6 k2k 10k 12k 8k 16k 18k 20k14k 22k Frequency (Hz) Amplitude (dBFS) −10 −20 −30 −40 −50 −60 −70 −80 −90 −100 −110 −120 −130 −140 −150 −160 AMPLITUDE vs FREQUENCY (Crosstalk with fIN = 20kHz) 0 4k 6k2k 10k 12k 8k 16k 18k 20k14k 22k Frequency (Hz) Amplitude (dBFS)
analog characteristics for which it offers. block diagram of the PGA2310. via the serial control port. VOUT R (pin 11) and VOUT L (pin 14). analog power supplies, VA+ (pin 12) and VA− (pin 13). output voltage range is 27VPP. Figure 1. PGA2310 Block Diagram
into SDI on the rising edge of SCLK. The protocol for the serial control port is shown in Figure 2. SDI is latched on the rising edge of SCLK. SDO transitions on the falling edge of SCLK. Figure 2. Serial Interface Protocol
analog ground (AGNDR or AGNDL). Figure 3. Serial Interface Timing Requirements
enough SCLK cycles to load all devices. to minimize audible artifacts. Figure 4. Daisy-Chaining Multiple PGA2310 Devices
recommended PCB floor plan for the PGA2310. through 16 are on the analog side of the board. Figure 6. Typical PCB Layout Floor Plan
ORDERABLE DEVICE STATUS(1) PACKAGE TYPE PACKAGE DRAWING PINS PACKAGE QTY PGA2310PA ACTIVE PDIP N 16 25 PGA2310UA ACTIVE SOIC DW 16 48 PGA2310UA/1K ACTIVE SOIC DW 16 1000 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. PACKAGE OPTION ADDENDUM www.ti.com 24-Jun-2004
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