PGA206UA

PGA206_16 TI1 | Alldatasheet

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© 1994 Burr-Brown Corporation PDS-1241B Printed in U.S.A. May, 1995 A 1 A 2 A 3 1010kΩ10kΩ 10kΩ10kΩ 4VIN VIN PGA206 PGA207 Ref VO Over-Voltage Protection Over-Voltage Protection Feedback Digitally Selected Feedback Network VO1 Digital Ground 6 9 8 VO2 V–VOS Adj High-Speed Programmable Gain INSTRUMENTATION AMPLIFIER

FEATURES

l DIGITALLY PROGRAMMABLE GAINS: PGA206: G=1, 2, 4, 8V/V PGA207: G=1, 2, 5, 10V/V l TRUE INSTRUMENTATION AMP INPUT l FAST SETTLING: 3.5µs to 0.01% l FET INPUT: IB = 100pA max l INPUT PROTECTION: ±40V l LOW OFFSET VOLTAGE: 1.5mV max l 16-PIN DIP, SOL-16 SOIC PACKAGES

APPLICATIONS

l MULTIPLE-CHANNEL DATA ACQUISITION l MEDICAL, PHYSIOLOGICAL AMPLIFIER l PC-CONTROLLED ANALOG INPUT BOARDS

DESCRIPTION

The PGA206 and PGA207 are digitally programmable gain instrumentation amplifiers that are ideally suited for data acquisition systems. The PGA206 and PGA207’s fast settling time allows multiplexed input channels for excellent system effi- ciency. FET inputs eliminate IB errors due to analog multiplexer series resistance. Gains are selected by two CMOS/TTL-compatible address lines. Analog inputs are internally protected for overloads up to ±40V, even with the power sup- plies off. The PGA206 and PGA207 are laser-trimmed for low offset voltage and low drift. The PGA206 and PGA207 are available in 16-pin plastic DIP and SOL-16 surface-mount packages. Both are specified for –40°C to +85°C operation. PGA206 PGA207 International Airport Industrial Park • Mailing Address: PO Box 11400, Tucson, AZ 85734 • Street Address: 6730 S. Tucson Blvd., Tucson, AZ 85706 • Tel: (520) 746-1111 • Twx: 910-952-1111 Internet: http://www.burr-brown.com/ • FAXLine: (800) 548-6133 (US/Canada Only) • Cable: BBRCORP • Telex: 066-6491 • FAX: (520) 889-1510 • Immediate Product Info: (800) 548-6132 PGA206 PGA207 SBOS033

PGA206P, U PGA206PA, UA PGA207P, U PGA207PA, UA PARAMETER CONDITIONS MIN TYP MAX MIN TYP MAX UNITS SPECIFICATIONS At TA = +25°C, VS = ±15V, RL = 2kΩ unless otherwise noted. The information provided herein is believed to be reliable; however, BURR-BROWN assumes no responsibility for inaccuracies or omissions. BURR-BROWN assumes no responsibility for the use of this information, and all use of such information shall be entirely at the user’s own risk. Prices and specifications are subject to change without notice. No patent rights or licenses to any of the circuits described herein are implied or granted to any third party. BURR-BROWN does not authorize or warrant any BURR-BROWN product for use in life support devices and/or systems. INPUT Offset Voltage, RTI All Gains Initial T vs Temperature T A = TMIN to TMAX , G = 8, 10 ±2 [ µV/°C vs Power Supply V S = ±4.5V to ±18V ±5 ±20 ±10 ±40 µV/V Long-Term Stability 4.5 [ µV/mo Impedance, Differential 10 13 || 1 [ Ω || pF Common-Mode 10 12 || 4 [ Ω || pF Common-Mode Voltage Range(1) VO = 0V ±(|VS|–4) ±(|VS| –2.5) [[ V Safe Input Voltage ±40 [ V Common-Mode Rejection V CM = ±11V, ΔR S = 1kΩ G = 1 80 92 75 86 dB G = 2 85 96 80 90 dB G = 4 or 5 90 100 84 94 dB G = 8 or 10 95 100 84 94 dB INPUT BIAS CURRENT VIN = 0 2 100 [[ pA vs Temperature See Typical Curve [ Offset Current 1 100 [[ pA vs Temperature See Typical Curve [ NOISE VOLTAGE, RTI G = 8,10; RS = 0Ω f = 10Hz 30 [ nV/√Hz f = 100Hz 20 [ nV/√Hz f = 1kHz 18 [ nV/√Hz fB = 0.1Hz to 10Hz 1 [ µVp-p Noise Current f = 1kHz 1.5 [ fA/√Hz GAIN All Gains, VO = ±11V Gain Error ±0.01 ±0.05 [ ±0.1 % Gain vs Temperature(2) ±1 ±10 [[ ppm/°C Nonlinearity ±0.0003 ±0.002 [ ±0.005 % of FSR OUTPUT Voltage, Positive (V+) –4 (V+) –2.3 [[ V Negative (V–) +4 (V–) +1.5 [[ V Load Capacitance Stability 1000 [ pF Short-Circuit Current ±17 [ mA FREQUENCY RESPONSE Bandwidth, –3dB G = 1 5 [ MHz G = 2 4 [ MHz G = 4, 5 1.3 [ MHz G = 8, 10 600 [ kHz Slew Rate V O = ±10V, G = 1 to 10 25 [ V/µs Settling Time, 0.1% 20V Step, All Gains 2 [ µs 0.01% 20V Step, All Gains 3.5 [ µs Output Overload Recovery 50% Overdrive 1.5 [ µs DIGITAL LOGIC INPUTS Digital Ground Voltage, VDG V– (V+) –4 [[ V Digital Low Voltage V– V DG + 0.8V [[ V Digital Input Current 1 [ pA Digital High Voltage V DG +2 V+ [[ V Gain Switching Time 500 [ ns POWER SUPPLY Voltage Range ±4.5 ±15 ±18 [[ [ V Current V IN = 0V +12.4/–11.2 ±13.5 [ mA TEMPERATURE RANGE Specification –40 +85 [[ °C Operating –40 +125 [[ °C Thermal Resistance, θJA 80 [ °C/W [ Specification same as PGA206P or PGA207P. NOTES: (1) Input common-mode range varies with output voltage—see typical curves. (2) Guaranteed by wafer test.

PRODUCT GAINS PACKAGE RANGE PGA206PA 1, 2, 4, 8V/V 16-Pin Plastic DIP –40 °C to +85°C PGA206P 1, 2, 4, 8V/V 16-Pin Plastic DIP –40 °C to +85°C PGA206UA 1, 2, 4, 8V/V SOL-16 Surface-Mount –40 °C to +85°C PGA206U 1, 2, 4, 8V/V SOL-16 Surface-Mount –40 °C to +85°C PGA207PA 1, 2, 5, 10V/V 16-Pin Plastic DIP –40 °C to +85°C PGA207P 1, 2, 5, 10V/V 16-Pin Plastic DIP –40 °C to +85°C PGA207UA 1, 2, 5, 10V/V SOL-16 Surface-Mount –40°C to +85°C PGA207U 1, 2, 5, 10V/V SOL-16 Surface-Mount –40 °C to +85°C ABSOLUTE MAXIMUM RATINGS

ORDERING INFORMATION

This integrated circuit can be damaged by ESD. Burr-Brown recommends that all integrated circuits be handled with ap- propriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. PIN CONFIGURATION Top View DIP SOL-16 VO1 NC NC VIN VIN VOS Adjust VOS Adjust Dig. Ground Sense V O Ref V NC: No Internal Connection

PACKAGE INFORMATION

PRODUCT PACKAGE NUMBER (1) PGA206PA 16-Pin Plastic DIP 180 PGA206P 16-Pin Plastic DIP 180 PGA206UA SOL-16 Surface Mount 211 PGA206U SOL-16 Surface Mount 211 PGA207PA 16-Pin Plastic DIP 180 PGA207P 16-Pin Plastic DIP 180 PGA207UA SOL-16 Surface Mount 211 PGA207U SOL-16 Surface Mount 211 NOTE: (1) For detailed drawing and dimension table, please see end of data sheet, or Appendix C of Burr-Brown IC Data Book.

TYPICAL PERFORMANCE CURVES At TA = +25°C, and VS = ±15V, unless otherwise noted. INPUT BIAS CURRENT vs TEMPERATURE Temperature (°C) Input Bias Current (A) 10n 100p 10p 100f 10f –75 0 –50 –25 25 50 75 100 125 IB IOS POWER SUPPLY REJECTION vs FREQUENCY Frequency (Hz) Power Supply Rejection (dB) 120 100 10 100 1k 10k 100k 1M 10M G = 10V/V G = 1V/V +PSR –PSR GAIN vs FREQUENCY Frequency (Hz) Gain (dB) 10k 100k 1M 10M –10 –20 G = 10 G = 8 G=5 G = 4 G = 2 G = 1 COMMON-MODE REJECTION vs FREQUENCY Common-Mode Rejection (dB) Frequency (Hz) 120 100 1k 10k 100k 1M 10M G = 10V/V G = 1V/V INPUT VOLTAGE NOISE vs FREQUENCY Frequency (Hz) Voltage Noise Density nV/√Hz 100 1 100 10 1k 10k 100k G = 1 G = 10 INPUT COMMON-MODE VOLTAGE RANGE vs OUTPUT VOLTAGE Output Voltage (V) Common-Mode Voltage (V) –15 –10 0 5 15 –5 –10 –15 Limited by A + Output Swing A3 – Output Swing Limit A3 + Output Swing Limit Limited by A – Output Swing Limited by A – Output Swing Limited by A + Output Swing VD/2 VD/2 VCM VO (Any Gain)

TYPICAL PERFORMANCE CURVES (CONT) At TA = +25°C, and VS = ±15V, unless otherwise noted. –40 –30 –20 –10 0 10 20 30 40 INPUT OVER-VOLTAGE V/I CHARACTERISTIC Input Voltage (V) Input Current (mA) V I +15V –15V Input current increases when the applied voltage exceeds the power supply voltage. This V/I characteristic does not vary with the voltage applied to the other input. TOTAL HARMONIC DISTORTION + NOISE vs FREQUENCY Frequency (Hz) THD + N (%) 0.1 0.01 0.001 10 100 1k 10k 100k G = 10V/V VO = 6Vrms G = 1V/V G = 1 R L = 2kΩ R L = 2kΩ R L = ∞ 0 ±5 ±10 ±15 ±20 Power Supply Voltage (V) QUIESCENT CURRENT vs POWER SUPPLY VOLTAGE Quiescent Current (mA) +25°C +125°C –55°C +IQ –IQ +125°C –55°C +25°C MAXIMUM OUTPUT VOLTAGE vs FREQUENCY Frequency (Hz) Maximum Output Voltage (Vp-p) 100k 1M 10M Maximum output voltage without slew-rate limiting or other large-signal distortion. Dotted region is beyond small signal bandwidth. G = 10V/V G = 2V/V G = 1V/V 100 –50 –100 01234 Time After Turn-On (minutes) OFFSET VOLTAGE WARM-UP TIME Offset Voltage Change (µV) OFFSET VOLTAGE TEMPERATURE DRIFT PRODUCTION DISTRIBUTION Units (%) Offset Voltage Drift (µV/°C) –10 –8 –6 –4 –2 0 2 4 6 8 10 Typical production distribution of packaged units. G = 8, 10V/V

G = 10, CL = 50pF 1µs/div 100mV/div SMALL SIGNAL RESPONSE G = 1, CL = 50pF 1µs/div LARGE SIGNAL RESPONSE G = 1, CL = 50pF TYPICAL PERFORMANCE CURVES (CONT) At TA = +25°C, and VS = ±15V, unless otherwise noted. LARGE SIGNAL RESPONSE G = 10, CL = 50pF 1µs/div 1µs/div 100mV/div 5V/div5V/div

FIGURE 4. Multiplexed-Input Signal Acquisition System. protected even if no power supply voltage is applied. differential input signals to a single PGA207. differential signal and common-mode noise.

www.ti.com 12-Aug-2016 Addendum-Page 1 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/Ball Finish (6) MSL Peak Temp (3) Op Temp (°C) Device Marking (4/5) Samples PGA206PA ACTIVE PDIP N 16 25 Green (RoHS & no Sb/Br) CU NIPDAU N / A for Pkg Type -40 to 85 PGA206PA PGA206PAG4 ACTIVE PDIP N 16 25 Green (RoHS & no Sb/Br) CU NIPDAU N / A for Pkg Type -40 to 85 PGA206PA PGA206UA ACTIVE SOIC DW 16 40 Green (RoHS & no Sb/Br) CU NIPDAU-DCC Level-3-260C-168 HR -40 to 85 PGA206UA PGA206UAG4 ACTIVE SOIC DW 16 40 Green (RoHS & no Sb/Br) CU NIPDAU-DCC Level-3-260C-168 HR -40 to 85 PGA206UA PGA207PA OBSOLETE PDIP N 16 TBD Call TI Call TI PGA207UA ACTIVE SOIC DW 16 40 Green (RoHS & no Sb/Br) CU NIPDAU-DCC Level-3-260C-168 HR -40 to 85 PGA207UA PGA207UA/1K ACTIVE SOIC DW 16 1000 Green (RoHS & no Sb/Br) Call TI Level-3-260C-168 HR -40 to 85 PGA207UA PGA207UAE4 ACTIVE SOIC DW 16 40 Green (RoHS & no Sb/Br) CU NIPDAU-DCC Level-3-260C-168 HR -40 to 85 PGA207UA (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

www.ti.com 12-Aug-2016 Addendum-Page 2 (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

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